1 /*
2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16 #include <drivers/arm/tzc380.h>
17 #include <drivers/console.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <lib/el3_runtime/context_mgmt.h>
20 #include <lib/mmio.h>
21 #include <lib/xlat_tables/xlat_tables_v2.h>
22 #include <plat/common/platform.h>
23
24 #include <dram.h>
25 #include <gpc.h>
26 #include <imx_aipstz.h>
27 #include <imx_uart.h>
28 #include <imx_rdc.h>
29 #include <imx8m_caam.h>
30 #include <imx8m_ccm.h>
31 #include <imx8m_csu.h>
32 #include <imx8m_snvs.h>
33 #include <plat_common.h>
34 #include <plat_imx8.h>
35
36 #define TRUSTY_PARAMS_LEN_BYTES (4096*2)
37
38 /*
39 * Note: DRAM region is mapped with entire size available and uses MT_RW
40 * attributes.
41 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section
42 * for explanation of this mapping scheme.
43 */
44 static const mmap_region_t imx_mmap[] = {
45 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW),
46 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
47 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */
48 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */
49 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */
50 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
51 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
52 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */
53 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */
54 {0},
55 };
56
57 static const struct aipstz_cfg aipstz[] = {
58 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
59 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
60 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
61 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
62 {0},
63 };
64
65 static struct imx_rdc_cfg rdc[] = {
66 /* Master domain assignment */
67 RDC_MDAn(RDC_MDA_M4, DID1),
68
69 /* peripherals domain permission */
70 RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W | D1R | D1W | D2R | D2W | D3R | D3W),
71 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
72 RDC_PDAPn(RDC_PDAP_UART3, D0R | D0W | D1R | D1W | D2R | D2W | D3R | D3W),
73 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
74
75 /* memory region */
76
77 /* Sentinel */
78 {0},
79 };
80
81 static const struct imx_csu_cfg csu_cfg[] = {
82 /* peripherals csl setting */
83 CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED),
84 CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED),
85 CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED),
86
87 /* master HP0~1 */
88
89 /* SA setting */
90 CSU_SA(CSU_SA_M4, NON_SEC_ACCESS, LOCKED),
91 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED),
92 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED),
93 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED),
94 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED),
95 CSU_SA(CSU_SA_VPU, NON_SEC_ACCESS, LOCKED),
96 CSU_SA(CSU_SA_GPU, NON_SEC_ACCESS, LOCKED),
97 CSU_SA(CSU_SA_APBHDMA, NON_SEC_ACCESS, LOCKED),
98 CSU_SA(CSU_SA_ENET, NON_SEC_ACCESS, LOCKED),
99 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED),
100 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED),
101 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED),
102 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED),
103 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED),
104 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED),
105 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED),
106 CSU_SA(CSU_SA_LCDIF, NON_SEC_ACCESS, LOCKED),
107 CSU_SA(CSU_SA_CSI, NON_SEC_ACCESS, LOCKED),
108
109 /* HP control setting */
110
111 /* Sentinel */
112 {0}
113 };
114
115 static entry_point_info_t bl32_image_ep_info;
116 static entry_point_info_t bl33_image_ep_info;
117
118 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)119 static uint32_t get_spsr_for_bl33_entry(void)
120 {
121 unsigned long el_status;
122 unsigned long mode;
123 uint32_t spsr;
124
125 /* figure out what mode we enter the non-secure world */
126 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
127 el_status &= ID_AA64PFR0_ELX_MASK;
128
129 mode = (el_status) ? MODE_EL2 : MODE_EL1;
130
131 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
132 return spsr;
133 }
134
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)135 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
136 u_register_t arg2, u_register_t arg3)
137 {
138 unsigned int console_base = IMX_BOOT_UART_BASE;
139 static console_t console;
140 int i, ret;
141
142 /* Enable CSU NS access permission */
143 for (i = 0; i < 64; i++) {
144 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
145 }
146
147 imx_aipstz_init(aipstz);
148
149 if (console_base == 0U) {
150 console_base = imx8m_uart_get_base();
151 }
152
153 imx_rdc_init(rdc, console_base);
154
155 imx_csu_init(csu_cfg);
156
157 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
158 IMX_CONSOLE_BAUDRATE, &console);
159 /* This console is only used for boot stage */
160 console_set_scope(&console, CONSOLE_FLAG_BOOT);
161
162 imx8m_caam_init();
163
164 /*
165 * tell BL3-1 where the non-secure software image is located
166 * and the entry state information.
167 */
168 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
169 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
170 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
171
172 #if defined(SPD_opteed) || defined(SPD_trusty)
173 /* Populate entry point information for BL32 */
174 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
175 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
176 bl32_image_ep_info.pc = BL32_BASE;
177 bl32_image_ep_info.spsr = 0;
178
179 /* Pass TEE base and size to bl33 */
180 bl33_image_ep_info.args.arg1 = BL32_BASE;
181 bl33_image_ep_info.args.arg2 = BL32_SIZE;
182
183 #ifdef SPD_trusty
184 bl32_image_ep_info.args.arg0 = BL32_SIZE;
185 bl32_image_ep_info.args.arg1 = BL32_BASE;
186 #else
187 /* Make sure memory is clean */
188 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
189 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
190 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
191 #endif
192 #endif
193 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE,
194 &bl32_image_ep_info, &bl33_image_ep_info);
195 if (ret != 0) {
196 ret = imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE,
197 &bl32_image_ep_info,
198 &bl33_image_ep_info);
199 }
200
201 #if !defined(SPD_opteed) && !defined(SPD_trusty)
202 enable_snvs_privileged_access();
203 #endif
204 }
205
206 #define MAP_BL31_TOTAL \
207 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE)
208 #define MAP_BL31_RO \
209 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
210 #define MAP_COHERENT_MEM \
211 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
212 MT_DEVICE | MT_RW | MT_SECURE)
213 #define MAP_BL32_TOTAL \
214 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW)
215
bl31_plat_arch_setup(void)216 void bl31_plat_arch_setup(void)
217 {
218 const mmap_region_t bl_regions[] = {
219 MAP_BL31_TOTAL,
220 MAP_BL31_RO,
221 #if USE_COHERENT_MEM
222 MAP_COHERENT_MEM,
223 #endif
224 #if defined(SPD_opteed) || defined(SPD_trusty)
225 /* Map TEE memory */
226 MAP_BL32_TOTAL,
227 #endif
228 {0}
229 };
230
231 setup_page_tables(bl_regions, imx_mmap);
232 enable_mmu_el3(0);
233 }
234
bl31_platform_setup(void)235 void bl31_platform_setup(void)
236 {
237 generic_delay_timer_init();
238
239 /* select the CKIL source to 32K OSC */
240 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
241
242 /* Init the dram info */
243 dram_info_init(SAVED_DRAM_TIMING_BASE);
244
245 plat_gic_driver_init();
246 plat_gic_init();
247
248 imx_gpc_init();
249 }
250
bl31_plat_get_next_image_ep_info(unsigned int type)251 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
252 {
253 if (type == NON_SECURE)
254 return &bl33_image_ep_info;
255 if (type == SECURE)
256 return &bl32_image_ep_info;
257
258 return NULL;
259 }
260
plat_get_syscnt_freq2(void)261 unsigned int plat_get_syscnt_freq2(void)
262 {
263 return COUNTER_FREQUENCY;
264 }
265
266 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)267 void plat_trusty_set_boot_args(aapcs64_params_t *args)
268 {
269 args->arg0 = BL32_SIZE;
270 args->arg1 = BL32_BASE;
271 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
272 }
273 #endif
274