1 /*
2 * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16 #include <drivers/arm/tzc380.h>
17 #include <drivers/console.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <lib/el3_runtime/context_mgmt.h>
20 #include <lib/mmio.h>
21 #include <lib/xlat_tables/xlat_tables_v2.h>
22 #include <plat/common/platform.h>
23
24 #include <dram.h>
25 #include <gpc.h>
26 #include <imx_aipstz.h>
27 #include <imx_uart.h>
28 #include <imx8m_caam.h>
29 #include <imx8m_ccm.h>
30 #include <plat_imx8.h>
31
32 #define TRUSTY_PARAMS_LEN_BYTES (4096*2)
33
34 /*
35 * Avoid the pointer dereference of the canonical mmio_read_8() implementation.
36 * This prevents the compiler from mis-interpreting the MMIO access as an
37 * illegal memory access to a very low address (the IMX ROM is mapped at 0).
38 */
mmio_read_8_ldrb(uintptr_t address)39 static uint8_t mmio_read_8_ldrb(uintptr_t address)
40 {
41 uint8_t reg;
42
43 __asm__ volatile ("ldrb %w0, [%1]" : "=r" (reg) : "r" (address));
44
45 return reg;
46 }
47
48 static const mmap_region_t imx_mmap[] = {
49 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */
50 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */
51 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
52 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
53 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */
54 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
55 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
56 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
57 {0},
58 };
59
60 static const struct aipstz_cfg aipstz[] = {
61 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
62 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
63 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
64 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
65 {0},
66 };
67
68 static entry_point_info_t bl32_image_ep_info;
69 static entry_point_info_t bl33_image_ep_info;
70
71 static uint32_t imx_soc_revision;
72
imx_soc_info_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3)73 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
74 u_register_t x3)
75 {
76 return imx_soc_revision;
77 }
78
79 #define ANAMIX_DIGPROG 0x6c
80 #define ROM_SOC_INFO_A0 0x800
81 #define ROM_SOC_INFO_B0 0x83C
82 #define OCOTP_SOC_INFO_B1 0x40
83
imx8mq_soc_info_init(void)84 static void imx8mq_soc_info_init(void)
85 {
86 uint32_t rom_version;
87 uint32_t ocotp_val;
88
89 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG);
90 rom_version = mmio_read_8_ldrb(IMX_ROM_BASE + ROM_SOC_INFO_A0);
91 if (rom_version == 0x10)
92 return;
93
94 rom_version = mmio_read_8_ldrb(IMX_ROM_BASE + ROM_SOC_INFO_B0);
95 if (rom_version == 0x20) {
96 imx_soc_revision &= ~0xff;
97 imx_soc_revision |= rom_version;
98 return;
99 }
100
101 /* 0xff0055aa is magic number for B1 */
102 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1);
103 if (ocotp_val == 0xff0055aa) {
104 imx_soc_revision &= ~0xff;
105 if (rom_version == 0x22) {
106 imx_soc_revision |= 0x22;
107 } else {
108 imx_soc_revision |= 0x21;
109 }
110 return;
111 }
112 }
113
114 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)115 static uint32_t get_spsr_for_bl33_entry(void)
116 {
117 unsigned long el_status;
118 unsigned long mode;
119 uint32_t spsr;
120
121 /* figure out what mode we enter the non-secure world */
122 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
123 el_status &= ID_AA64PFR0_ELX_MASK;
124
125 mode = (el_status) ? MODE_EL2 : MODE_EL1;
126
127 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
128 return spsr;
129 }
130
bl31_tz380_setup(void)131 static void bl31_tz380_setup(void)
132 {
133 unsigned int val;
134
135 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10);
136 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
137 return;
138
139 tzc380_init(IMX_TZASC_BASE);
140 /*
141 * Need to substact offset 0x40000000 from CPU address when
142 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW
143 */
144 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
145 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
146 }
147
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)148 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
149 u_register_t arg2, u_register_t arg3)
150 {
151 unsigned int console_base = IMX_BOOT_UART_BASE;
152 static console_t console;
153 int i;
154 /* enable CSU NS access permission */
155 for (i = 0; i < 64; i++) {
156 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
157 }
158
159 imx_aipstz_init(aipstz);
160
161 if (console_base == 0U) {
162 console_base = imx8m_uart_get_base();
163 }
164
165 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
166 IMX_CONSOLE_BAUDRATE, &console);
167 /* This console is only used for boot stage */
168 console_set_scope(&console, CONSOLE_FLAG_BOOT);
169
170 imx8m_caam_init();
171
172 /*
173 * tell BL3-1 where the non-secure software image is located
174 * and the entry state information.
175 */
176 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
177 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
178 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
179
180 #if defined(SPD_opteed) || defined(SPD_trusty)
181 /* Populate entry point information for BL32 */
182 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
183 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
184 bl32_image_ep_info.pc = BL32_BASE;
185 bl32_image_ep_info.spsr = 0;
186
187 /* Pass TEE base and size to bl33 */
188 bl33_image_ep_info.args.arg1 = BL32_BASE;
189 bl33_image_ep_info.args.arg2 = BL32_SIZE;
190
191 #ifdef SPD_trusty
192 bl32_image_ep_info.args.arg0 = BL32_SIZE;
193 bl32_image_ep_info.args.arg1 = BL32_BASE;
194 #else
195 /* Make sure memory is clean */
196 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
197 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
198 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
199 #endif
200 #endif
201
202 bl31_tz380_setup();
203 }
204
bl31_plat_arch_setup(void)205 void bl31_plat_arch_setup(void)
206 {
207 const mmap_region_t bl_regions[] = {
208 MAP_REGION_FLAT(BL31_START, BL31_SIZE,
209 MT_MEMORY | MT_RW | MT_SECURE),
210 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
211 MT_MEMORY | MT_RO | MT_SECURE),
212 #if SEPARATE_NOBITS_REGION
213 MAP_REGION_FLAT(BL_NOBITS_BASE, BL_NOBITS_END - BL_NOBITS_BASE,
214 MT_RW_DATA | MT_SECURE),
215 #endif
216 #if USE_COHERENT_MEM
217 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
218 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
219 MT_DEVICE | MT_RW | MT_SECURE),
220 #endif
221 #if defined(SPD_opteed) || defined(SPD_trusty)
222 /* Map TEE memory */
223 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW),
224 #endif
225 {0},
226 };
227
228 setup_page_tables(bl_regions, imx_mmap);
229 /* enable the MMU */
230 enable_mmu_el3(0);
231 }
232
bl31_platform_setup(void)233 void bl31_platform_setup(void)
234 {
235 generic_delay_timer_init();
236
237 /* init the GICv3 cpu and distributor interface */
238 plat_gic_driver_init();
239 plat_gic_init();
240
241 /* determine SOC revision for erratas */
242 imx8mq_soc_info_init();
243
244 /* gpc init */
245 imx_gpc_init();
246
247 dram_info_init(SAVED_DRAM_TIMING_BASE);
248 }
249
bl31_plat_get_next_image_ep_info(unsigned int type)250 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
251 {
252 if (type == NON_SECURE)
253 return &bl33_image_ep_info;
254 if (type == SECURE)
255 return &bl32_image_ep_info;
256
257 return NULL;
258 }
259
plat_get_syscnt_freq2(void)260 unsigned int plat_get_syscnt_freq2(void)
261 {
262 return COUNTER_FREQUENCY;
263 }
264
265 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)266 void plat_trusty_set_boot_args(aapcs64_params_t *args)
267 {
268 args->arg0 = BL32_SIZE;
269 args->arg1 = BL32_BASE;
270 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
271 }
272 #endif
273