1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <platform_def.h> 10 #include <plat/common/platform.h> 11 12 #include "socfpga_private.h" 13 socfpga_get_ns_image_entrypoint(void)14unsigned long socfpga_get_ns_image_entrypoint(void) 15 { 16 return PLAT_NS_IMAGE_OFFSET; 17 } 18 19 /****************************************************************************** 20 * Gets SPSR for BL32 entry 21 *****************************************************************************/ socfpga_get_spsr_for_bl32_entry(void)22uint32_t socfpga_get_spsr_for_bl32_entry(void) 23 { 24 /* 25 * The Secure Payload Dispatcher service is responsible for 26 * setting the SPSR prior to entry into the BL32 image. 27 */ 28 return 0; 29 } 30 31 /****************************************************************************** 32 * Gets SPSR for BL33 entry 33 *****************************************************************************/ socfpga_get_spsr_for_bl33_entry(void)34uint32_t socfpga_get_spsr_for_bl33_entry(void) 35 { 36 unsigned long el_status; 37 unsigned int mode; 38 uint32_t spsr; 39 40 /* Figure out what mode we enter the non-secure world in */ 41 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 42 el_status &= ID_AA64PFR0_ELX_MASK; 43 44 mode = (el_status) ? MODE_EL2 : MODE_EL1; 45 46 /* 47 * TODO: Consider the possibility of specifying the SPSR in 48 * the FIP ToC and allowing the platform to have a say as 49 * well. 50 */ 51 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 52 return spsr; 53 } 54 55