Merge changes I92c3e293,I95149f5e into integration

* changes:
fix(imx): match function parameters to declaration
fix(intel): match declaration with definition

fix(intel): match declaration with definition

Patch 2fcb37db8 changed the alignment to 8, but the `extern` definition
remained at 32 so bring in line. Also use the same macro for the size of
the arr

fix(intel): match declaration with definition

Patch 2fcb37db8 changed the alignment to 8, but the `extern` definition
remained at 32 so bring in line. Also use the same macro for the size of
the array.

Change-Id: I95149f5e3428a58c464e616c385250b10eda2834
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(intel): update nand driver to enable Linux OS boot" into integration

fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359

fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359378574b913b11d466c89389a2606
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): undo setting USB 3.1 reset pulse bit in BL2" into integration

fix(intel): undo setting USB 3.1 reset pulse bit in BL2

During testing of USB 3.1 in FreeRTOS, it is reported, setting
the reset pulse override bit is affecting the enumeration of
USB devices attach

fix(intel): undo setting USB 3.1 reset pulse bit in BL2

During testing of USB 3.1 in FreeRTOS, it is reported, setting
the reset pulse override bit is affecting the enumeration of
USB devices attached to the USB 3.1 controller. Hence,
reverting the bit change to its default state.

Change-Id: I5746a7ff6b579c39416a462ebef6696f4aa57051
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): select the DFI interface based on the hand-off data" into integration

fix(intel): select the DFI interface based on the hand-off data

Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data

fix(intel): select the DFI interface based on the hand-off data

Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data.

Change-Id: I097b7f84874368a5ed265d8fa7fff193f430b245
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): fix iossm driver timeout in agilex5" into integration

fix(intel): fix iossm driver timeout in agilex5

bl2_plat_setup.c: check return value for
agilex5_ddr_init. If init fail, it will go into
panic. This will help future debug to root cause
the actual i

fix(intel): fix iossm driver timeout in agilex5

bl2_plat_setup.c: check return value for
agilex5_ddr_init. If init fail, it will go into
panic. This will help future debug to root cause
the actual issue.

agilex5_iossm_mailbox.c: corrected divisor
for read_count in inline_ecc_bist_mem_init. Wrong
divisor will cause read_count to be 0. The same
value is also used in out_of_band_ecc_bist_mem_init.

Change-Id: I4c85d251b7e88f3176902917450572adb574b33a
Signed-off-by: Goh Shun Jing <shun.jing.goh@altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): configure usb3 system manager reg in TFA" into integration

fix(intel): configure usb3 system manager reg in TFA

Reset pulse override bit needs to be set for successful
reset staggering pulse generation.

The bit one of power over-current field actually refl

fix(intel): configure usb3 system manager reg in TFA

Reset pulse override bit needs to be set for successful
reset staggering pulse generation.

The bit one of power over-current field actually reflects
PIPE power present signal. This bit needs to be set to
avoid providing false information about VBus to the
HPS controller.

Change-Id: I123e2ec7c8ceaa15f47f90460fae5a325741dd10
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "feat(intel): add FDT support for Altera products" into integration

feat(intel): add FDT support for Altera products

Support FDT for Agilex5 platform
1. Created wrapper file socfpga_dt.c
2. Added in Agilex5 dts file
3. Implemented fdt_check_header
4. Implemented gic

feat(intel): add FDT support for Altera products

Support FDT for Agilex5 platform
1. Created wrapper file socfpga_dt.c
2. Added in Agilex5 dts file
3. Implemented fdt_check_header
4. Implemented gic configuration
5. Implemented dram configuration

Remove init of FDT as Agilex5 has no plan to roll
out FDT at the moment.

Change-Id: If3990ed9524c6da5b3cb8966b63bc4a95d01fcda
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): refactor SDMMC driver for Altera products" into integration

Merge "feat(intel): clock manager PLL configuration for Agilex5 platform" into integration

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): clock manager PLL configuration for Agilex5 platform

Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.

Change-Id: I3c5cbaf7a677

feat(intel): clock manager PLL configuration for Agilex5 platform

Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.

Change-Id: I3c5cbaf7a677a022ef24b0e679860e6ee195f16a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "feat(intel): update BL2 platform specific functions" into integration

feat(intel): update BL2 platform specific functions

Update and initialize the BL2 EL3 functions for agilex5
platform.

Change-Id: I673c622dfe4ff71d77edfa0866ebf6cd7163d793
Signed-off-by: Girisha Den

feat(intel): update BL2 platform specific functions

Update and initialize the BL2 EL3 functions for agilex5
platform.

Change-Id: I673c622dfe4ff71d77edfa0866ebf6cd7163d793
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update Agilex5 BL2 init flow and other misc changes" into integration

Merge "feat(intel): update Agilex5 DDR and IOSSM driver" into integration

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc u

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): update Agilex5 DDR and IOSSM driver

DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2

feat(intel): update Agilex5 DDR and IOSSM driver

DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge changes I23bdbbe1,Ic22ab741 into integration

* changes:
feat(intel): enable VAB support for Intel products
feat(intel): add in SHA384 authentication