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Searched refs:ID_AA64PFR0_EL2_SHIFT (Results 1 – 17 of 17) sorted by relevance

/rk3399_ARM-atf/plat/imx/common/
H A Dimx_bl31_common.c16 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in plat_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/intel/soc/common/aarch64/
H A Dplatform_common.c41 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in socfpga_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/marvell/armada/common/aarch64/
H A Dmarvell_common.c115 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in marvell_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dbl2_plat_setup.c68 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in poplar_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx93/
H A Dimx93_bl31_setup.c50 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/ti/common/
H A Dti_bl31_setup.c39 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in k3_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl2_plat_setup.c149 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dbl2_plat_setup.c162 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c224 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_bl31_setup.c98 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in sq_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/
H A Dimx8mn_bl31_setup.c97 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dimx8mq_bl31_setup.c122 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/
H A Dimx8mm_bl31_setup.c126 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/
H A Dimx8mp_bl31_setup.c128 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8qx/
H A Dimx8qx_bl31_setup.c103 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8qm/
H A Dimx8qm_bl31_setup.c82 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/include/arch/aarch64/
H A Darch.h216 #define ID_AA64PFR0_EL2_SHIFT U(8) macro