Searched refs:ID_AA64PFR0_EL2_SHIFT (Results 1 – 17 of 17) sorted by relevance
16 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in plat_get_spsr_for_bl33_entry()
41 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in socfpga_get_spsr_for_bl33_entry()
115 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in marvell_get_spsr_for_bl33_entry()
68 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in poplar_get_spsr_for_bl33_entry()
50 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
39 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in k3_get_spsr_for_bl33_entry()
149 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
162 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
224 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
98 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in sq_get_spsr_for_bl33_entry()
97 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
122 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
126 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
128 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
103 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
82 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
216 #define ID_AA64PFR0_EL2_SHIFT U(8) macro