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Searched refs:rk_clrreg (Results 1 – 25 of 25) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3368/
H A Drk3368.c116 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); in mcu_init()
267 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); in sgrf_init()
268 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); in sgrf_init()
269 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); in sgrf_init()
283 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
284 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); in sgrf_init()
297 rk_clrreg(PMU_GRF_SOC_CON0, 1 << 7); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3399/
H A Drk3399.c100 rk_clrreg(&sgrf->slv_secure_con4, 0x2000); in arch_cpu_init()
104 rk_clrreg(&grf->emmccore_con[11], 0x0ff); in arch_cpu_init()
107 rk_clrreg(&pmugrf->soc_con0, 1 << 5); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk322x/
H A Drk322x.c28 rk_clrreg(SGRF_DDR_CON0, 0x4000); in arch_cpu_init()
41 rk_clrreg(CRU_MISC_CON, 1 << 13); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/drivers/rng/
H A Drockchip_rng.c186 rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START); in cryptov1_rng_read()
220 rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff); in cryptov2_rng_read()
287 rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff); in rkrng_init()
322 rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff); in rkrng_rng_read()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3562/
H A Drk3562.c535 rk_clrreg(PMU_BASE_ADDR + PMU2_PWR_GATE_SFTCON0, in qos_priority_init()
550 rk_clrreg(PMU_BASE_ADDR + PMU2_MEM_SD_SFTCON0, BIT(i)); in qos_priority_init()
553 rk_clrreg(PMU_BASE_ADDR + PMU2_BIU_IDLE_SFTCON0, in qos_priority_init()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dhardware.h18 #define rk_clrreg(addr, clr) writel((clr) << 16, addr) macro
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3328/
H A Drk3328.c65 rk_clrreg(CRU_MISC_CON, 1 << 13); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/px30/
H A Dpx30.c217 rk_clrreg(PMU_PWRDN_CON, 1 << 13); in arch_cpu_init()
243 rk_clrreg(PMU_PWRDN_CON, 1 << 13); in arch_cpu_init()
250 rk_clrreg(GRF_CPU_CON1, 1 << 7); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c146 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
154 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
347 rk_clrreg(&cru->softrst_con[10], phy_reset); in ddrctl_reset()
349 rk_clrreg(&cru->softrst_con[10], ctl_reset); in ddrctl_reset()
H A Dsdram_rk322x.c101 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | in phy_pctrl_reset()
105 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
H A Dsdram_rk3288.c456 rk_clrreg(&grf->soc_con0, 1 << (8 + channel)); in set_bandwidth_ratio()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c378 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | in phy_pctrl_reset()
382 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3288/
H A Drk3288.c227 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); in rk3288_detect_reset_reason()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3288.c263 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
1199 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
1204 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); in rk3288_clk_set_rate()
1209 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
H A Dclk_pll.c301 rk_clrreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
457 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
H A Dclk_rk3328.c996 rk_clrreg(&grf->mac_con[1], BIT(10)); in rk3328_gmac2io_set_parent()
1033 rk_clrreg(&grf->soc_con[4], BIT(14)); in rk3328_gmac2io_ext_set_parent()
1070 rk_clrreg(&grf->mac_con[2], BIT(10)); in rk3328_gmac2phy_set_parent()
H A Dclk_rk3066.c136 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
H A Dclk_rk3368.c280 rk_clrreg(&pll->con3, PLL_RESET_MASK); in rkclk_set_pll()
1092 rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); in rk3368_gmac_set_parent()
H A Dclk_rk3188.c134 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
H A Dclk_rk3036.c93 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
H A Dclk_rv1108.c102 rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); in rkclk_set_pll()
H A Dclk_rk3308.c1232 rk_clrreg(&priv->cru->clksel_con[43], BIT(14)); in rk3308_mac_set_parent()
H A Dclk_rk3399.c1305 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); in rk3399_gmac_set_parent()
H A Dclk_px30.c257 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3308/
H A Drk3308.c204 rk_clrreg(&sgrf->con_secure0, 0x2b83); in arch_cpu_init()