1 /*
2 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/arch/bootrom.h>
9 #include <asm/arch/hardware.h>
10 #include <asm/arch/grf_rk3328.h>
11 #include <asm/arch/uart.h>
12 #include <asm/armv8/mmu.h>
13 #include <asm/io.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #define CRU_BASE 0xFF440000
18 #define GRF_BASE 0xFF100000
19 #define UART2_BASE 0xFF130000
20
21 #define CRU_MISC_CON 0xff440084
22 #define FW_DDR_CON_REG 0xff7c0040
23
24 static struct mm_region rk3328_mem_map[] = {
25 {
26 .virt = 0x0UL,
27 .phys = 0x0UL,
28 .size = 0xff000000UL,
29 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
30 PTE_BLOCK_INNER_SHARE
31 }, {
32 .virt = 0xff000000UL,
33 .phys = 0xff000000UL,
34 .size = 0x1000000UL,
35 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
36 PTE_BLOCK_NON_SHARE |
37 PTE_BLOCK_PXN | PTE_BLOCK_UXN
38 }, {
39 /* List terminator */
40 0,
41 }
42 };
43
44 struct mm_region *mem_map = rk3328_mem_map;
45
46 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
47 [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000",
48 [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000",
49 };
50
51 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)52 int arch_cpu_init(void)
53 {
54 #ifdef CONFIG_SPL_BUILD
55 struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
56 /* We do some SoC one time setting here. */
57
58 /* Disable the ddr secure region setting to make it non-secure */
59 rk_setreg(FW_DDR_CON_REG, 0x200);
60
61 /* Enable force to jtag, jtag_tclk/tms iomuxed with sdmmc0_d2/d3 */
62 rk_setreg(&grf->soc_con[4], 1 << 12);
63
64 /* HDMI phy clock source select HDMIPHY clock out */
65 rk_clrreg(CRU_MISC_CON, 1 << 13);
66
67 /* TODO: ECO version */
68 #endif
69 return 0;
70 }
71 #endif
72
board_debug_uart_init(void)73 void board_debug_uart_init(void)
74 {
75 #ifdef CONFIG_TPL_BUILD
76 struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
77 struct rk_uart * const uart = (void *)UART2_BASE;
78 enum{
79 GPIO2A0_SEL_SHIFT = 0,
80 GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
81 GPIO2A0_UART2_TX_M1 = 1,
82
83 GPIO2A1_SEL_SHIFT = 2,
84 GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
85 GPIO2A1_UART2_RX_M1 = 1,
86 };
87 enum {
88 IOMUX_SEL_UART2_SHIFT = 0,
89 IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
90 IOMUX_SEL_UART2_M0 = 0,
91 IOMUX_SEL_UART2_M1,
92 };
93
94 /* uart_sel_clk default select 24MHz */
95 writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
96
97 /* init uart baud rate 1500000 */
98 writel(0x83, &uart->lcr);
99 writel(0x1, &uart->rbr);
100 writel(0x3, &uart->lcr);
101
102 /* Enable early UART2 */
103 rk_clrsetreg(&grf->com_iomux,
104 IOMUX_SEL_UART2_MASK,
105 IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
106 rk_clrsetreg(&grf->gpio2a_iomux,
107 GPIO2A0_SEL_MASK,
108 GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
109 rk_clrsetreg(&grf->gpio2a_iomux,
110 GPIO2A1_SEL_MASK,
111 GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
112
113 /* enable FIFO */
114 writel(0x1, &uart->sfe);
115 #endif
116 }
117