1 /*
2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6 #include <common.h>
7 #include <bitfield.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/hardware.h>
14 #include <div64.h>
15
16 static struct rockchip_pll_rate_table rockchip_auto_table;
17
18 #define PLL_MODE_MASK 0x3
19 #define PLL_RK3328_MODE_MASK 0x1
20
21 #define RK3036_PLLCON0_FBDIV_MASK 0xfff
22 #define RK3036_PLLCON0_FBDIV_SHIFT 0
23 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12
24 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12
25 #define RK3036_PLLCON1_REFDIV_MASK 0x3f
26 #define RK3036_PLLCON1_REFDIV_SHIFT 0
27 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6
28 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6
29 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12
30 #define RK3036_PLLCON1_DSMPD_SHIFT 12
31 #define RK3036_PLLCON2_FRAC_MASK 0xffffff
32 #define RK3036_PLLCON2_FRAC_SHIFT 0
33 #define RK3036_PLLCON1_PWRDOWN_SHIT 13
34
35 #define MHZ 1000000
36 #define KHZ 1000
37
38 #define OSC_HZ (24UL * MHZ)
39 #define VCO_MAX_HZ (3200UL * MHZ)
40 #define VCO_MIN_HZ (800UL * MHZ)
41 #define OUTPUT_MAX_HZ (3200UL * MHZ)
42 #define OUTPUT_MIN_HZ (24UL * MHZ)
43 #define MIN_FOUTVCO_FREQ (800UL * MHZ)
44 #define MAX_FOUTVCO_FREQ (2000UL * MHZ)
45
46 #define RK3588_VCO_MIN_HZ (2250UL * MHZ)
47 #define RK3588_VCO_MAX_HZ (4500UL * MHZ)
48 #define RK3588_FOUT_MIN_HZ (37UL * MHZ)
49 #define RK3588_FOUT_MAX_HZ (4500UL * MHZ)
50
gcd(int m,int n)51 int gcd(int m, int n)
52 {
53 int t;
54
55 while (m > 0) {
56 if (n > m) {
57 t = m;
58 m = n;
59 n = t;
60 } /* swap */
61 m -= n;
62 }
63 return n;
64 }
65
66 /*
67 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
68 * Formulas also embedded within the Fractional PLL Verilog model:
69 * If DSMPD = 1 (DSM is disabled, "integer mode")
70 * FOUTVCO = FREF / REFDIV * FBDIV
71 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
72 * Where:
73 * FOUTVCO = Fractional PLL non-divided output frequency
74 * FOUTPOSTDIV = Fractional PLL divided output frequency
75 * (output of second post divider)
76 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
77 * REFDIV = Fractional PLL input reference clock divider
78 * FBDIV = Integer value programmed into feedback divide
79 *
80 */
81
rockchip_pll_clk_set_postdiv(ulong fout_hz,u32 * postdiv1,u32 * postdiv2,u32 * foutvco)82 static int rockchip_pll_clk_set_postdiv(ulong fout_hz,
83 u32 *postdiv1,
84 u32 *postdiv2,
85 u32 *foutvco)
86 {
87 ulong freq;
88
89 if (fout_hz < MIN_FOUTVCO_FREQ) {
90 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
91 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
92 freq = fout_hz * (*postdiv1) * (*postdiv2);
93 if (freq >= MIN_FOUTVCO_FREQ &&
94 freq <= MAX_FOUTVCO_FREQ) {
95 *foutvco = freq;
96 return 0;
97 }
98 }
99 }
100 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n",
101 fout_hz);
102 } else {
103 *postdiv1 = 1;
104 *postdiv2 = 1;
105 }
106 return 0;
107 }
108
109 static struct rockchip_pll_rate_table *
rockchip_pll_clk_set_by_auto(ulong fin_hz,ulong fout_hz)110 rockchip_pll_clk_set_by_auto(ulong fin_hz,
111 ulong fout_hz)
112 {
113 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
114 /* FIXME set postdiv1/2 always 1*/
115 u32 foutvco = fout_hz;
116 ulong fin_64, frac_64;
117 u32 f_frac, postdiv1, postdiv2;
118 ulong clk_gcd = 0;
119
120 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
121 return NULL;
122
123 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
124 rate_table->postdiv1 = postdiv1;
125 rate_table->postdiv2 = postdiv2;
126 rate_table->dsmpd = 1;
127
128 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
129 fin_hz /= MHZ;
130 foutvco /= MHZ;
131 clk_gcd = gcd(fin_hz, foutvco);
132 rate_table->refdiv = fin_hz / clk_gcd;
133 rate_table->fbdiv = foutvco / clk_gcd;
134
135 rate_table->frac = 0;
136
137 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n",
138 fin_hz, fout_hz, clk_gcd);
139 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n",
140 rate_table->refdiv,
141 rate_table->fbdiv, rate_table->postdiv1,
142 rate_table->postdiv2);
143 } else {
144 debug("frac div,fin_hz = %ld,fout_hz = %ld\n",
145 fin_hz, fout_hz);
146 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n",
147 rate_table->postdiv1, rate_table->postdiv2, foutvco);
148 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
149 rate_table->refdiv = fin_hz / MHZ / clk_gcd;
150 rate_table->fbdiv = foutvco / MHZ / clk_gcd;
151 debug("frac get refdiv = %d, fbdiv = %d\n",
152 rate_table->refdiv, rate_table->fbdiv);
153
154 rate_table->frac = 0;
155
156 f_frac = (foutvco % MHZ);
157 fin_64 = fin_hz;
158 fin_64 = fin_64 / rate_table->refdiv;
159 frac_64 = f_frac << 24;
160 frac_64 = frac_64 / fin_64;
161 rate_table->frac = frac_64;
162 if (rate_table->frac > 0)
163 rate_table->dsmpd = 0;
164 debug("frac = %x\n", rate_table->frac);
165 }
166 return rate_table;
167 }
168
169 static struct rockchip_pll_rate_table *
rk3588_pll_clk_set_by_auto(unsigned long fin_hz,unsigned long fout_hz)170 rk3588_pll_clk_set_by_auto(unsigned long fin_hz,
171 unsigned long fout_hz)
172 {
173 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
174 u32 p, m, s;
175 ulong fvco, fref, fout, ffrac;
176
177 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
178 return NULL;
179
180 if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ)
181 return NULL;
182
183 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
184 for (s = 0; s <= 6; s++) {
185 fvco = fout_hz << s;
186 if (fvco < RK3588_VCO_MIN_HZ ||
187 fvco > RK3588_VCO_MAX_HZ)
188 continue;
189 for (p = 2; p <= 4; p++) {
190 for (m = 64; m <= 1023; m++) {
191 if (fvco == m * fin_hz / p) {
192 rate_table->p = p;
193 rate_table->m = m;
194 rate_table->s = s;
195 rate_table->k = 0;
196 return rate_table;
197 }
198 }
199 }
200 }
201 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
202 } else {
203 for (s = 0; s <= 6; s++) {
204 fvco = fout_hz << s;
205 if (fvco < RK3588_VCO_MIN_HZ ||
206 fvco > RK3588_VCO_MAX_HZ)
207 continue;
208 for (p = 1; p <= 4; p++) {
209 for (m = 64; m <= 1023; m++) {
210 if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) {
211 rate_table->p = p;
212 rate_table->m = m;
213 rate_table->s = s;
214 fref = fin_hz / p;
215 ffrac = fvco - (m * fref);
216 fout = ffrac * 65536;
217 rate_table->k = fout / fref;
218 return rate_table;
219 }
220 }
221 }
222 }
223 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
224 }
225 return NULL;
226 }
227
228 static const struct rockchip_pll_rate_table *
rockchip_get_pll_settings(struct rockchip_pll_clock * pll,ulong rate)229 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)
230 {
231 struct rockchip_pll_rate_table *rate_table = pll->rate_table;
232
233 while (rate_table->rate) {
234 if (rate_table->rate == rate)
235 break;
236 rate_table++;
237 }
238 if (rate_table->rate != rate) {
239 if (pll->type == pll_rk3588)
240 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate);
241 else
242 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
243 } else {
244 return rate_table;
245 }
246 }
247
rk3036_pll_set_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id,ulong drate)248 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
249 void __iomem *base, ulong pll_id,
250 ulong drate)
251 {
252 const struct rockchip_pll_rate_table *rate;
253 int timeout = 100;
254
255 rate = rockchip_get_pll_settings(pll, drate);
256 if (!rate) {
257 printf("%s unsupport rate\n", __func__);
258 return -EINVAL;
259 }
260
261 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n",
262 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv);
263 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n",
264 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac);
265
266 /*
267 * When power on or changing PLL setting,
268 * we must force PLL into slow mode to ensure output stable clock.
269 */
270 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
271 rk_clrsetreg(base + pll->mode_offset,
272 pll->mode_mask << pll->mode_shift,
273 RKCLK_PLL_MODE_SLOW << pll->mode_shift);
274 }
275
276 /* Power down */
277 rk_setreg(base + pll->con_offset + 0x4,
278 1 << RK3036_PLLCON1_PWRDOWN_SHIT);
279
280 rk_clrsetreg(base + pll->con_offset,
281 (RK3036_PLLCON0_POSTDIV1_MASK |
282 RK3036_PLLCON0_FBDIV_MASK),
283 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) |
284 rate->fbdiv);
285 rk_clrsetreg(base + pll->con_offset + 0x4,
286 (RK3036_PLLCON1_POSTDIV2_MASK |
287 RK3036_PLLCON1_REFDIV_MASK),
288 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT |
289 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT));
290 if (!rate->dsmpd) {
291 rk_clrsetreg(base + pll->con_offset + 0x4,
292 RK3036_PLLCON1_DSMPD_MASK,
293 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);
294 writel((readl(base + pll->con_offset + 0x8) &
295 (~RK3036_PLLCON2_FRAC_MASK)) |
296 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT),
297 base + pll->con_offset + 0x8);
298 }
299
300 /* Power Up */
301 rk_clrreg(base + pll->con_offset + 0x4,
302 1 << RK3036_PLLCON1_PWRDOWN_SHIT);
303
304 /* waiting for pll lock */
305 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) {
306 udelay(1);
307 timeout--;
308 }
309
310 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
311 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id);
312
313 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
314 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
315 RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
316 }
317
318 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
319 pll, readl(base + pll->con_offset),
320 readl(base + pll->con_offset + 0x4),
321 readl(base + pll->con_offset + 0x8),
322 readl(base + pll->mode_offset));
323
324 return 0;
325 }
326
rk3036_pll_get_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id)327 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
328 void __iomem *base, ulong pll_id)
329 {
330 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
331 u32 con = 0, shift, mask;
332 ulong rate;
333 int mode;
334
335 con = readl(base + pll->mode_offset);
336 shift = pll->mode_shift;
337 mask = pll->mode_mask << shift;
338
339 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
340 mode = (con & mask) >> shift;
341 else
342 mode = RKCLK_PLL_MODE_NORMAL;
343
344 switch (mode) {
345 case RKCLK_PLL_MODE_SLOW:
346 return OSC_HZ;
347 case RKCLK_PLL_MODE_NORMAL:
348 /* normal mode */
349 con = readl(base + pll->con_offset);
350 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >>
351 RK3036_PLLCON0_POSTDIV1_SHIFT;
352 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >>
353 RK3036_PLLCON0_FBDIV_SHIFT;
354 con = readl(base + pll->con_offset + 0x4);
355 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >>
356 RK3036_PLLCON1_POSTDIV2_SHIFT;
357 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >>
358 RK3036_PLLCON1_REFDIV_SHIFT;
359 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >>
360 RK3036_PLLCON1_DSMPD_SHIFT;
361 con = readl(base + pll->con_offset + 0x8);
362 frac = (con & RK3036_PLLCON2_FRAC_MASK) >>
363 RK3036_PLLCON2_FRAC_SHIFT;
364 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
365 if (dsmpd == 0) {
366 u64 frac_rate = OSC_HZ * (u64)frac;
367
368 do_div(frac_rate, refdiv);
369 frac_rate >>= 24;
370 do_div(frac_rate, postdiv1);
371 do_div(frac_rate, postdiv1);
372 rate += frac_rate;
373 }
374 return rate;
375 case RKCLK_PLL_MODE_DEEP:
376 default:
377 return 32768;
378 }
379 }
380
381 #define RK3588_PLLCON(i) ((i) * 0x4)
382 #define RK3588_PLLCON0_M_MASK 0x3ff << 0
383 #define RK3588_PLLCON0_M_SHIFT 0
384 #define RK3588_PLLCON1_P_MASK 0x3f << 0
385 #define RK3588_PLLCON1_P_SHIFT 0
386 #define RK3588_PLLCON1_S_MASK 0x7 << 6
387 #define RK3588_PLLCON1_S_SHIFT 6
388 #define RK3588_PLLCON2_K_MASK 0xffff
389 #define RK3588_PLLCON2_K_SHIFT 0
390 #define RK3588_PLLCON1_PWRDOWN BIT(13)
391 #define RK3588_PLLCON6_LOCK_STATUS BIT(15)
392 #define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300)
393 #define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300)
394 #define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300)
395 #define RK3588_CORE_DIV_MASK 0x1f
396 #define RK3588_CORE_L02_DIV_SHIFT 0
397 #define RK3588_CORE_L13_DIV_SHIFT 7
398 #define RK3588_CORE_B02_DIV_SHIFT 8
399 #define RK3588_CORE_B13_DIV_SHIFT 0
400
rk3588_pll_set_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id,ulong drate)401 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll,
402 void __iomem *base, ulong pll_id,
403 ulong drate)
404 {
405 const struct rockchip_pll_rate_table *rate;
406
407 rate = rockchip_get_pll_settings(pll, drate);
408 if (!rate) {
409 printf("%s unsupported rate\n", __func__);
410 return -EINVAL;
411 }
412
413 debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n",
414 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
415
416 /*
417 * When power on or changing PLL setting,
418 * we must force PLL into slow mode to ensure output stable clock.
419 */
420 if (pll_id == 3)
421 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1);
422
423 rk_clrsetreg(base + pll->mode_offset,
424 pll->mode_mask << pll->mode_shift,
425 RKCLK_PLL_MODE_SLOW << pll->mode_shift);
426 if (pll_id == 0)
427 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
428 pll->mode_mask << 6,
429 RKCLK_PLL_MODE_SLOW << 6);
430 else if (pll_id == 1)
431 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
432 pll->mode_mask << 6,
433 RKCLK_PLL_MODE_SLOW << 6);
434 else if (pll_id == 2)
435 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
436 pll->mode_mask << 14,
437 RKCLK_PLL_MODE_SLOW << 14);
438
439 /* Power down */
440 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1),
441 RK3588_PLLCON1_PWRDOWN);
442
443 rk_clrsetreg(base + pll->con_offset,
444 RK3588_PLLCON0_M_MASK,
445 (rate->m << RK3588_PLLCON0_M_SHIFT));
446 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1),
447 (RK3588_PLLCON1_P_MASK |
448 RK3588_PLLCON1_S_MASK),
449 (rate->p << RK3588_PLLCON1_P_SHIFT |
450 rate->s << RK3588_PLLCON1_S_SHIFT));
451 if (rate->k) {
452 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),
453 RK3588_PLLCON2_K_MASK,
454 rate->k << RK3588_PLLCON2_K_SHIFT);
455 }
456 /* Power up */
457 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1),
458 RK3588_PLLCON1_PWRDOWN);
459
460 /* waiting for pll lock */
461 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) &
462 RK3588_PLLCON6_LOCK_STATUS)) {
463 udelay(1);
464 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id);
465 }
466
467 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
468 RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
469 if (pll_id == 0) {
470 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
471 pll->mode_mask << 6,
472 2 << 6);
473 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
474 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT,
475 0 << RK3588_CORE_B02_DIV_SHIFT);
476 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1),
477 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
478 0 << RK3588_CORE_B13_DIV_SHIFT);
479 } else if (pll_id == 1) {
480 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
481 pll->mode_mask << 6,
482 2 << 6);
483 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
484 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT,
485 0 << RK3588_CORE_B02_DIV_SHIFT);
486 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1),
487 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
488 0 << RK3588_CORE_B13_DIV_SHIFT);
489 } else if (pll_id == 2) {
490 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
491 pll->mode_mask << 14,
492 2 << 14);
493 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6),
494 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT,
495 0 << RK3588_CORE_L13_DIV_SHIFT);
496 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6),
497 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT,
498 0 << RK3588_CORE_L02_DIV_SHIFT);
499 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7),
500 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT,
501 0 << RK3588_CORE_L13_DIV_SHIFT);
502 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7),
503 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT,
504 0 << RK3588_CORE_L02_DIV_SHIFT);
505 }
506
507 if (pll_id == 3)
508 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0);
509
510 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
511 pll, readl(base + pll->con_offset),
512 readl(base + pll->con_offset + 0x4),
513 readl(base + pll->con_offset + 0x8),
514 readl(base + pll->mode_offset));
515
516 return 0;
517 }
518
rk3588_pll_get_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id)519 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll,
520 void __iomem *base, ulong pll_id)
521 {
522 u32 m, p, s, k;
523 u32 con = 0, shift, mode;
524 u64 rate, postdiv;
525
526 con = readl(base + pll->mode_offset);
527 shift = pll->mode_shift;
528 if (pll_id == 8)
529 mode = RKCLK_PLL_MODE_NORMAL;
530 else
531 mode = (con & (pll->mode_mask << shift)) >> shift;
532 switch (mode) {
533 case RKCLK_PLL_MODE_SLOW:
534 return OSC_HZ;
535 case RKCLK_PLL_MODE_NORMAL:
536 /* normal mode */
537 con = readl(base + pll->con_offset);
538 m = (con & RK3588_PLLCON0_M_MASK) >>
539 RK3588_PLLCON0_M_SHIFT;
540 con = readl(base + pll->con_offset + RK3588_PLLCON(1));
541 p = (con & RK3588_PLLCON1_P_MASK) >>
542 RK3036_PLLCON0_FBDIV_SHIFT;
543 s = (con & RK3588_PLLCON1_S_MASK) >>
544 RK3588_PLLCON1_S_SHIFT;
545 con = readl(base + pll->con_offset + RK3588_PLLCON(2));
546 k = (con & RK3588_PLLCON2_K_MASK) >>
547 RK3588_PLLCON2_K_SHIFT;
548
549 rate = OSC_HZ / p;
550 rate *= m;
551 if (k) {
552 /* fractional mode */
553 u64 frac_rate64 = OSC_HZ * k;
554
555 postdiv = p * 65536;
556 do_div(frac_rate64, postdiv);
557 rate += frac_rate64;
558 }
559 rate = rate >> s;
560 return rate;
561 case RKCLK_PLL_MODE_DEEP:
562 default:
563 return 32768;
564 }
565 }
566
rockchip_pll_get_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id)567 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
568 void __iomem *base,
569 ulong pll_id)
570 {
571 ulong rate = 0;
572
573 switch (pll->type) {
574 case pll_rk3036:
575 pll->mode_mask = PLL_MODE_MASK;
576 rate = rk3036_pll_get_rate(pll, base, pll_id);
577 break;
578 case pll_rk3328:
579 pll->mode_mask = PLL_RK3328_MODE_MASK;
580 rate = rk3036_pll_get_rate(pll, base, pll_id);
581 break;
582 case pll_rk3588:
583 pll->mode_mask = PLL_MODE_MASK;
584 rate = rk3588_pll_get_rate(pll, base, pll_id);
585 break;
586 default:
587 printf("%s: Unknown pll type for pll clk %ld\n",
588 __func__, pll_id);
589 }
590 return rate;
591 }
592
rockchip_pll_set_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id,ulong drate)593 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
594 void __iomem *base, ulong pll_id,
595 ulong drate)
596 {
597 int ret = 0;
598
599 if (rockchip_pll_get_rate(pll, base, pll_id) == drate)
600 return 0;
601
602 switch (pll->type) {
603 case pll_rk3036:
604 pll->mode_mask = PLL_MODE_MASK;
605 ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
606 break;
607 case pll_rk3328:
608 pll->mode_mask = PLL_RK3328_MODE_MASK;
609 ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
610 break;
611 case pll_rk3588:
612 pll->mode_mask = PLL_MODE_MASK;
613 ret = rk3588_pll_set_rate(pll, base, pll_id, drate);
614 break;
615 default:
616 printf("%s: Unknown pll type for pll clk %ld\n",
617 __func__, pll_id);
618 }
619 return ret;
620 }
621
622 const struct rockchip_cpu_rate_table *
rockchip_get_cpu_settings(struct rockchip_cpu_rate_table * cpu_table,ulong rate)623 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
624 ulong rate)
625 {
626 struct rockchip_cpu_rate_table *ps = cpu_table;
627
628 while (ps->rate) {
629 if (ps->rate == rate)
630 break;
631 ps++;
632 }
633 if (ps->rate != rate)
634 return NULL;
635 else
636 return ps;
637 }
638
639