1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/arch/bootrom.h>
9*4882a593Smuzhiyun #include <asm/arch/hardware.h>
10*4882a593Smuzhiyun #include <asm/arch/grf_rk3328.h>
11*4882a593Smuzhiyun #include <asm/arch/uart.h>
12*4882a593Smuzhiyun #include <asm/armv8/mmu.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define CRU_BASE 0xFF440000
18*4882a593Smuzhiyun #define GRF_BASE 0xFF100000
19*4882a593Smuzhiyun #define UART2_BASE 0xFF130000
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define CRU_MISC_CON 0xff440084
22*4882a593Smuzhiyun #define FW_DDR_CON_REG 0xff7c0040
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static struct mm_region rk3328_mem_map[] = {
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun .virt = 0x0UL,
27*4882a593Smuzhiyun .phys = 0x0UL,
28*4882a593Smuzhiyun .size = 0xff000000UL,
29*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
30*4882a593Smuzhiyun PTE_BLOCK_INNER_SHARE
31*4882a593Smuzhiyun }, {
32*4882a593Smuzhiyun .virt = 0xff000000UL,
33*4882a593Smuzhiyun .phys = 0xff000000UL,
34*4882a593Smuzhiyun .size = 0x1000000UL,
35*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
36*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE |
37*4882a593Smuzhiyun PTE_BLOCK_PXN | PTE_BLOCK_UXN
38*4882a593Smuzhiyun }, {
39*4882a593Smuzhiyun /* List terminator */
40*4882a593Smuzhiyun 0,
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct mm_region *mem_map = rk3328_mem_map;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
47*4882a593Smuzhiyun [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000",
48*4882a593Smuzhiyun [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000",
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)52*4882a593Smuzhiyun int arch_cpu_init(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
55*4882a593Smuzhiyun struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
56*4882a593Smuzhiyun /* We do some SoC one time setting here. */
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Disable the ddr secure region setting to make it non-secure */
59*4882a593Smuzhiyun rk_setreg(FW_DDR_CON_REG, 0x200);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Enable force to jtag, jtag_tclk/tms iomuxed with sdmmc0_d2/d3 */
62*4882a593Smuzhiyun rk_setreg(&grf->soc_con[4], 1 << 12);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* HDMI phy clock source select HDMIPHY clock out */
65*4882a593Smuzhiyun rk_clrreg(CRU_MISC_CON, 1 << 13);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* TODO: ECO version */
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun #endif
72*4882a593Smuzhiyun
board_debug_uart_init(void)73*4882a593Smuzhiyun void board_debug_uart_init(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun #ifdef CONFIG_TPL_BUILD
76*4882a593Smuzhiyun struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
77*4882a593Smuzhiyun struct rk_uart * const uart = (void *)UART2_BASE;
78*4882a593Smuzhiyun enum{
79*4882a593Smuzhiyun GPIO2A0_SEL_SHIFT = 0,
80*4882a593Smuzhiyun GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
81*4882a593Smuzhiyun GPIO2A0_UART2_TX_M1 = 1,
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun GPIO2A1_SEL_SHIFT = 2,
84*4882a593Smuzhiyun GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
85*4882a593Smuzhiyun GPIO2A1_UART2_RX_M1 = 1,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun enum {
88*4882a593Smuzhiyun IOMUX_SEL_UART2_SHIFT = 0,
89*4882a593Smuzhiyun IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
90*4882a593Smuzhiyun IOMUX_SEL_UART2_M0 = 0,
91*4882a593Smuzhiyun IOMUX_SEL_UART2_M1,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* uart_sel_clk default select 24MHz */
95*4882a593Smuzhiyun writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* init uart baud rate 1500000 */
98*4882a593Smuzhiyun writel(0x83, &uart->lcr);
99*4882a593Smuzhiyun writel(0x1, &uart->rbr);
100*4882a593Smuzhiyun writel(0x3, &uart->lcr);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Enable early UART2 */
103*4882a593Smuzhiyun rk_clrsetreg(&grf->com_iomux,
104*4882a593Smuzhiyun IOMUX_SEL_UART2_MASK,
105*4882a593Smuzhiyun IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
106*4882a593Smuzhiyun rk_clrsetreg(&grf->gpio2a_iomux,
107*4882a593Smuzhiyun GPIO2A0_SEL_MASK,
108*4882a593Smuzhiyun GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
109*4882a593Smuzhiyun rk_clrsetreg(&grf->gpio2a_iomux,
110*4882a593Smuzhiyun GPIO2A1_SEL_MASK,
111*4882a593Smuzhiyun GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* enable FIFO */
114*4882a593Smuzhiyun writel(0x1, &uart->sfe);
115*4882a593Smuzhiyun #endif
116*4882a593Smuzhiyun }
117