1 /*
2 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
3 * Copyright (c) 2016 Andreas Färber
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <asm/armv8/mmu.h>
10 #include <asm/arch/bootrom.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/cru_rk3368.h>
14 #include <asm/arch/grf_rk3368.h>
15 #include <syscon.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define IMEM_BASE 0xFF8C0000
20
21 /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 8K) */
22 #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 8)
23 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
24 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
25 /* exsram may using by mcu to accessing dram(0x0-0x20000000) */
26 #define MCU_EXSRAM_BASE (0)
27 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
28 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
29 /* experi no used, reserved value = 0 */
30 #define MCU_EXPERI_BASE (0)
31 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
32 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
33
34 #define DDR_LATENCY_BASE (0xffac0000 + 0x14)
35 #define DDR_READ_LATENCY_VALUE 0x34
36
37 #define CPU_AXI_QOS_PRIORITY_BASE 0xffad0300
38 #define CPU_AXI_QOS_PRIORITY 0x08
39 #define QOS_PRIORITY_LEVEL_H 2
40 #define QOS_PRIORITY_LEVEL_L 2
41
42 #define ISP_R0_QOS_BASE 0xffad0080
43 #define QOS_ISP_R0_PRIORITY_LEVEL_H 1
44 #define QOS_ISP_R0_PRIORITY_LEVEL_L 1
45
46 #define ISP_R1_QOS_BASE 0xffad0100
47 #define QOS_ISP_R1_PRIORITY_LEVEL_H 1
48 #define QOS_ISP_R1_PRIORITY_LEVEL_L 1
49
50 #define ISP_W0_QOS_BASE 0xffad0180
51 #define QOS_ISP_W0_PRIORITY_LEVEL_H 3
52 #define QOS_ISP_W0_PRIORITY_LEVEL_L 3
53
54 #define ISP_W1_QOS_BASE 0xffad0200
55 #define QOS_ISP_W1_PRIORITY_LEVEL_H 3
56 #define QOS_ISP_W1_PRIORITY_LEVEL_L 3
57
58 /* cpu axi qos priority */
59 #define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
60 ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
61
62 #define GRF_SOC_CON15 0xff77043c
63 #define PMU_GRF_SOC_CON0 0xff738100
64
65 static struct mm_region rk3368_mem_map[] = {
66 {
67 .virt = 0x0UL,
68 .phys = 0x0UL,
69 .size = 0xfe000000UL,
70 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
71 PTE_BLOCK_INNER_SHARE
72 }, {
73 .virt = 0xfe000000UL,
74 .phys = 0xfe000000UL,
75 .size = 0x02000000UL,
76 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
77 PTE_BLOCK_NON_SHARE |
78 PTE_BLOCK_PXN | PTE_BLOCK_UXN
79 }, {
80 /* List terminator */
81 0,
82 }
83 };
84
85 struct mm_region *mem_map = rk3368_mem_map;
86
87 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
88 [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
89 [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
90 };
91
92 #ifdef CONFIG_ARCH_EARLY_INIT_R
mcu_init(void)93 static int mcu_init(void)
94 {
95 struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
96 struct rk3368_cru *cru = rockchip_get_cru();
97
98 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
99 MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
100 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
101 MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
102 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
103 MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
104 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
105 MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
106 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
107 MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
108 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
109 MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
110
111 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
112 (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
113 (5 << MCU_CLK_DIV_SHIFT));
114
115 /* mcu dereset, for start running */
116 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
117
118 return 0;
119 }
120
arch_early_init_r(void)121 int arch_early_init_r(void)
122 {
123 return mcu_init();
124 }
125 #endif
126
board_debug_uart_init(void)127 void board_debug_uart_init(void)
128 {
129 /*
130 * N.B.: This is called before the device-model has been
131 * initialised. For this reason, we can not access
132 * the GRF address range using the syscon API.
133 */
134 struct rk3368_grf * const grf __maybe_unused =
135 (struct rk3368_grf * const)0xff770000;
136
137 enum {
138 /* UART0 */
139 GPIO2D1_MASK = GENMASK(3, 2),
140 GPIO2D1_GPIO = 0,
141 GPIO2D1_UART0_SOUT = (1 << 2),
142
143 GPIO2D0_MASK = GENMASK(1, 0),
144 GPIO2D0_GPIO = 0,
145 GPIO2D0_UART0_SIN = (1 << 0),
146
147 /* UART2 */
148 GPIO2A6_MASK = GENMASK(13, 12),
149 GPIO2A6_GPIO = 0,
150 GPIO2A6_UART0_SIN = (1 << 13),
151 GPIO2A6_UART2_SIN = (2 << 12),
152
153 GPIO2A5_MASK = GENMASK(11, 10),
154 GPIO2A5_GPIO = 0,
155 GPIO2A5_UART0_SOUT = (1 << 11),
156 GPIO2A5_UART2_SOUT = (2 << 10),
157 };
158
159 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
160 /* Enable early UART0 on the RK3368 */
161 rk_clrsetreg(&grf->gpio2d_iomux,
162 GPIO2D0_MASK, GPIO2D0_UART0_SIN);
163 rk_clrsetreg(&grf->gpio2d_iomux,
164 GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
165 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
166 struct rk3368_pmu_grf * const pmugrf __maybe_unused =
167 (struct rk3368_pmu_grf * const)0xff738000;
168
169 enum {
170 /* UART4 */
171 GPIO0D2_MASK = GENMASK(5, 4),
172 GPIO0D2_GPIO = 0,
173 GPIO0D2_UART4_SOUT = (3 << 4),
174
175 GPIO0D3_MASK = GENMASK(7, 6),
176 GPIO0D3_GPIO = 0,
177 GPIO0D3_UART4_SIN = (3 << 6),
178 };
179
180 /* Enable early UART4 on the PX5 */
181 rk_clrsetreg(&pmugrf->gpio0d_iomux,
182 GPIO0D2_MASK | GPIO0D3_MASK,
183 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
184 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
185 /* Enable early UART2 on the RK3368 */
186 rk_clrsetreg(&grf->gpio2a_iomux,
187 GPIO2A6_MASK, GPIO2A6_UART2_SIN);
188 rk_clrsetreg(&grf->gpio2a_iomux,
189 GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
190 #endif
191 }
192
193 #ifndef CONFIG_TPL_BUILD
cpu_axi_qos_prority_level_config(void)194 static void cpu_axi_qos_prority_level_config(void)
195 {
196 u32 level;
197
198 /* Set lcdc cpu axi qos priority level */
199 level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_PRIORITY_LEVEL_H,
200 QOS_PRIORITY_LEVEL_L);
201 writel(level, CPU_AXI_QOS_PRIORITY_BASE + CPU_AXI_QOS_PRIORITY);
202
203 /* Set cpu isp r0 qos priority level */
204 level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_ISP_R0_PRIORITY_LEVEL_H,
205 QOS_ISP_R0_PRIORITY_LEVEL_L);
206 writel(level, ISP_R0_QOS_BASE + CPU_AXI_QOS_PRIORITY);
207
208 /* Set cpu isp r1 qos priority level */
209 level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_ISP_R1_PRIORITY_LEVEL_H,
210 QOS_ISP_R1_PRIORITY_LEVEL_L);
211 writel(level, ISP_R1_QOS_BASE + CPU_AXI_QOS_PRIORITY);
212
213 /* Set cpu isp w0 qos priority level */
214 level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_ISP_W0_PRIORITY_LEVEL_H,
215 QOS_ISP_W0_PRIORITY_LEVEL_L);
216 writel(level, ISP_W0_QOS_BASE + CPU_AXI_QOS_PRIORITY);
217
218 /* Set cpu isp w1 qos priority level */
219 level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_ISP_W1_PRIORITY_LEVEL_H,
220 QOS_ISP_W1_PRIORITY_LEVEL_L);
221 writel(level, ISP_W1_QOS_BASE + CPU_AXI_QOS_PRIORITY);
222 }
223
224 #ifdef CONFIG_SPL_BUILD
225 /*
226 * The SPL (and also the full U-Boot stage on the RK3368) will run in
227 * secure mode (i.e. EL3) and an ATF will eventually be booted before
228 * starting up the operating system... so we can initialize the SGRF
229 * here and rely on the ATF installing the final (secure) policy
230 * later.
231 */
sgrf_soc_con_addr(unsigned no)232 static inline uintptr_t sgrf_soc_con_addr(unsigned no)
233 {
234 const uintptr_t SGRF_BASE =
235 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
236
237 return SGRF_BASE + sizeof(u32) * no;
238 }
239
sgrf_busdmac_addr(unsigned no)240 static inline uintptr_t sgrf_busdmac_addr(unsigned no)
241 {
242 const uintptr_t SGRF_BASE =
243 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
244 const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
245 const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
246
247 return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
248 }
249
sgrf_init(void)250 static void sgrf_init(void)
251 {
252 struct rk3368_cru * const cru =
253 (struct rk3368_cru * const)rockchip_get_cru();
254 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
255 const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
256 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
257
258 /* Set all configurable IP to 'non secure'-mode */
259 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
260 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
261 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
262
263 /*
264 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
265 * Original comment: "ddr space set no secure mode"
266 */
267 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
268 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
269 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
270
271 /* Set 'secure dma' to 'non secure'-mode */
272 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
273 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
274
275 dsb(); /* barrier */
276
277 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
278 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
279
280 dsb(); /* barrier */
281 udelay(10);
282
283 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
284 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
285 }
286 #endif
287
arch_cpu_init(void)288 int arch_cpu_init(void)
289 {
290 /* DDR read latency config */
291 writel(DDR_READ_LATENCY_VALUE, DDR_LATENCY_BASE);
292
293 /* PWMs select rkpwm clock source */
294 rk_setreg(GRF_SOC_CON15, 1 << 12);
295
296 /* PWM2 select 32KHz clock source */
297 rk_clrreg(PMU_GRF_SOC_CON0, 1 << 7);
298
299 /* Enable force jtag */
300 rk_setreg(GRF_SOC_CON15, 1 << 13);
301
302 /* Cpu axi qos config */
303 cpu_axi_qos_prority_level_config();
304
305 #ifdef CONFIG_SPL_BUILD
306 /* Reset security, so we can use DMA in the MMC drivers */
307 sgrf_init();
308 #endif
309
310 return 0;
311 }
312 #endif
313