1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_HARDWARE_H 8*4882a593Smuzhiyun #define _ASM_ARCH_HARDWARE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) 11*4882a593Smuzhiyun #define RK_SETBITS(set) RK_CLRSETBITS(0, set) 12*4882a593Smuzhiyun #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define TIMER7_BASE 0xff810020 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define rk_clrsetreg(addr, clr, set) \ 17*4882a593Smuzhiyun writel((((clr) | (set)) << 16) | (set), addr) 18*4882a593Smuzhiyun #define rk_clrreg(addr, clr) writel((clr) << 16, addr) 19*4882a593Smuzhiyun #define rk_setreg(addr, set) writel((set) << 16 | (set), addr) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #endif 22