1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <asm/io.h>
7*4882a593Smuzhiyun #include <asm/arch/bootrom.h>
8*4882a593Smuzhiyun #include <asm/arch/hardware.h>
9*4882a593Smuzhiyun #include <asm/arch/grf_rk322x.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define GRF_BASE 0x11000000
12*4882a593Smuzhiyun #define CRU_MISC_CON 0x110e0134
13*4882a593Smuzhiyun #define SGRF_DDR_CON0 0x10150000
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
16*4882a593Smuzhiyun [BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000",
17*4882a593Smuzhiyun [BROM_BOOTSOURCE_SD] = "/dwmmc@30000000",
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)21*4882a593Smuzhiyun int arch_cpu_init(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun static struct rk322x_grf * const grf = (void *)GRF_BASE;
24*4882a593Smuzhiyun /* We do some SoC one time setting here. */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
27*4882a593Smuzhiyun /* Disable the ddr secure region setting to make it non-secure */
28*4882a593Smuzhiyun rk_clrreg(SGRF_DDR_CON0, 0x4000);
29*4882a593Smuzhiyun #endif
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* PWMs select rkpwm clock source */
32*4882a593Smuzhiyun rk_setreg(&grf->soc_con[2], 1 << 0);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* PWM0~3 io select */
35*4882a593Smuzhiyun rk_setreg(&grf->con_iomux, 0xf << 0);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* UART1~2 io select */
38*4882a593Smuzhiyun rk_setreg(&grf->con_iomux, (1 << 11) | (1 << 8));
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* HDMI phy clock source select HDMIPHY clock out */
41*4882a593Smuzhiyun rk_clrreg(CRU_MISC_CON, 1 << 13);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * The integrated macphy is enabled by default, disable it
45*4882a593Smuzhiyun * for saving power consuming.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK,
48*4882a593Smuzhiyun 0 << MACPHY_CFG_ENABLE_SHIFT);
49*4882a593Smuzhiyun /* TODO: ECO version */
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun
board_debug_uart_init(void)55*4882a593Smuzhiyun void board_debug_uart_init(void)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun static struct rk322x_grf * const grf = (void *)GRF_BASE;
58*4882a593Smuzhiyun enum {
59*4882a593Smuzhiyun GPIO1B2_SHIFT = 4,
60*4882a593Smuzhiyun GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
61*4882a593Smuzhiyun GPIO1B2_GPIO = 0,
62*4882a593Smuzhiyun GPIO1B2_UART21_SIN = 2,
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun GPIO1B1_SHIFT = 2,
65*4882a593Smuzhiyun GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
66*4882a593Smuzhiyun GPIO1B1_GPIO = 0,
67*4882a593Smuzhiyun GPIO1B1_UART1_SOUT,
68*4882a593Smuzhiyun GPIO1B1_UART21_SOUT,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun enum {
71*4882a593Smuzhiyun CON_IOMUX_UART2SEL_SHIFT= 8,
72*4882a593Smuzhiyun CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
73*4882a593Smuzhiyun CON_IOMUX_UART2SEL_2 = 0,
74*4882a593Smuzhiyun CON_IOMUX_UART2SEL_21,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Enable early UART2 channel 1 on the RK322x */
78*4882a593Smuzhiyun rk_clrsetreg(&grf->gpio1b_iomux,
79*4882a593Smuzhiyun GPIO1B1_MASK | GPIO1B2_MASK,
80*4882a593Smuzhiyun GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
81*4882a593Smuzhiyun GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
82*4882a593Smuzhiyun /* Set channel C as UART2 input */
83*4882a593Smuzhiyun rk_clrsetreg(&grf->con_iomux,
84*4882a593Smuzhiyun CON_IOMUX_UART2SEL_MASK,
85*4882a593Smuzhiyun CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
86*4882a593Smuzhiyun }
87