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Searched refs:SCLK_PWM1 (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Dpx30-cru.h50 #define SCLK_PWM1 35 macro
H A Drk1808-cru.h86 #define SCLK_PWM1 85 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dpx30-cru.h37 #define SCLK_PWM1 35 macro
H A Drk3308-cru.h124 #define SCLK_PWM1 120 macro
H A Drk1808-cru.h86 #define SCLK_PWM1 85 macro
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk1808.c331 case SCLK_PWM1: in rk1808_pwm_get_clk()
363 case SCLK_PWM1: in rk1808_pwm_set_clk()
951 case SCLK_PWM1: in rk1808_clk_get_rate()
1055 case SCLK_PWM1: in rk1808_clk_set_rate()
H A Dclk_px30.c660 case SCLK_PWM1: in px30_pwm_get_clk()
688 case SCLK_PWM1: in px30_pwm_set_clk()
1340 case SCLK_PWM1: in px30_clk_get_rate()
1426 case SCLK_PWM1: in px30_clk_set_rate()
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk1808.dtsi392 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
403 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
414 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
425 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
H A Dpx30.dtsi603 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
614 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
625 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
636 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi757 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
769 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
781 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
793 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
H A Drk1808.dtsi856 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
867 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
878 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
889 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
H A Dpx30.dtsi1092 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1103 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1114 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1125 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3308.c400 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
H A Dclk-px30.c731 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
H A Dclk-rk1808.c964 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,