1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/display/media-bus-format.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/rockchip.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/suspend/rockchip-rk3308.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 compatible = "rockchip,rk3308"; 19 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ethernet0 = &mac; 26 gpio0 = &gpio0; 27 gpio1 = &gpio1; 28 gpio2 = &gpio2; 29 gpio3 = &gpio3; 30 gpio4 = &gpio4; 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 serial0 = &uart0; 36 serial1 = &uart1; 37 serial2 = &uart2; 38 serial3 = &uart3; 39 serial4 = &uart4; 40 spi0 = &spi0; 41 spi1 = &spi1; 42 spi2 = &spi2; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35"; 52 reg = <0x0 0x0>; 53 enable-method = "psci"; 54 clocks = <&cru ARMCLK>; 55 #cooling-cells = <2>; 56 dynamic-power-coefficient = <83>; 57 operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>; 58 cpu-idle-states = <&CPU_SLEEP>; 59 next-level-cache = <&l2>; 60 power-model { 61 compatible = "simple-power-model"; 62 leakage-range= <5 50>; 63 ls = <6086 6346 (-63)>; 64 static-coefficient = <100000>; 65 ts = <(-109130) 101460 (-1620) 30>; 66 thermal-zone = "soc-thermal"; 67 }; 68 }; 69 70 cpu1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a35"; 73 reg = <0x0 0x1>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>; 76 cpu-idle-states = <&CPU_SLEEP>; 77 next-level-cache = <&l2>; 78 }; 79 80 cpu2: cpu@2 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a35"; 83 reg = <0x0 0x2>; 84 enable-method = "psci"; 85 operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>; 86 cpu-idle-states = <&CPU_SLEEP>; 87 next-level-cache = <&l2>; 88 }; 89 90 cpu3: cpu@3 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a35"; 93 reg = <0x0 0x3>; 94 enable-method = "psci"; 95 operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>; 96 cpu-idle-states = <&CPU_SLEEP>; 97 next-level-cache = <&l2>; 98 }; 99 100 idle-states { 101 entry-method = "psci"; 102 103 CPU_SLEEP: cpu-sleep { 104 compatible = "arm,idle-state"; 105 local-timer-stop; 106 arm,psci-suspend-param = <0x0010000>; 107 entry-latency-us = <120>; 108 exit-latency-us = <250>; 109 min-residency-us = <900>; 110 }; 111 }; 112 113 l2: l2-cache { 114 compatible = "cache"; 115 }; 116 }; 117 118 cpu0_opp_table: cpu0-opp-table { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 rockchip,temp-hysteresis = <5000>; 123 rockchip,low-temp = <0>; 124 rockchip,low-temp-min-volt = <1000000>; 125 rockchip,max-volt = <1325000>; 126 rockchip,low-temp-adjust-volt = < 127 /* MHz MHz uV */ 128 0 1296 50000 129 >; 130 131 rockchip,evb-irdrop = <25000>; 132 nvmem-cells = <&cpu_leakage>; 133 nvmem-cell-names = "leakage"; 134 135 rockchip,pvtm-voltage-sel = < 136 0 54000 0 137 54001 56000 1 138 56001 58500 2 139 58501 61000 3 140 61001 63500 4 141 63501 99999 5 142 >; 143 rockchip,pvtm-freq = <408000>; 144 rockchip,pvtm-volt = <1025000>; 145 rockchip,pvtm-ch = <0 0>; 146 rockchip,pvtm-sample-time = <1000>; 147 rockchip,pvtm-number = <10>; 148 rockchip,pvtm-error = <1000>; 149 rockchip,pvtm-ref-temp = <35>; 150 rockchip,pvtm-temp-prop = <(-15) (-37)>; 151 rockchip,thermal-zone = "soc-thermal"; 152 153 opp-408000000 { 154 opp-hz = /bits/ 64 <408000000>; 155 opp-microvolt = <950000 950000 1325000>; 156 clock-latency-ns = <40000>; 157 opp-suspend; 158 }; 159 opp-600000000 { 160 opp-hz = /bits/ 64 <600000000>; 161 opp-microvolt = <950000 950000 1325000>; 162 clock-latency-ns = <40000>; 163 }; 164 opp-816000000 { 165 opp-hz = /bits/ 64 <816000000>; 166 opp-microvolt = <1025000 1025000 1325000>; 167 opp-microvolt-L0 = <1025000 1025000 1325000>; 168 opp-microvolt-L1 = <1025000 1025000 1325000>; 169 opp-microvolt-L2 = <1025000 1025000 1325000>; 170 opp-microvolt-L3 = <1000000 1000000 1325000>; 171 opp-microvolt-L4 = <975000 975000 1325000>; 172 opp-microvolt-L5 = <950000 950000 1325000>; 173 clock-latency-ns = <40000>; 174 }; 175 opp-1008000000 { 176 opp-hz = /bits/ 64 <1008000000>; 177 opp-microvolt = <1125000 1125000 1325000>; 178 opp-microvolt-L0 = <1125000 1125000 1325000>; 179 opp-microvolt-L1 = <1100000 1100000 1325000>; 180 opp-microvolt-L2 = <1100000 1100000 1325000>; 181 opp-microvolt-L3 = <1075000 1075000 1325000>; 182 opp-microvolt-L4 = <1050000 1050000 1325000>; 183 opp-microvolt-L5 = <1025000 1025000 1325000>; 184 clock-latency-ns = <40000>; 185 }; 186 opp-1200000000 { 187 opp-hz = /bits/ 64 <1200000000>; 188 opp-microvolt = <1250000 1250000 1325000>; 189 opp-microvolt-L0 = <1250000 1250000 1325000>; 190 opp-microvolt-L1 = <1225000 1225000 1325000>; 191 opp-microvolt-L2 = <1200000 1200000 1325000>; 192 opp-microvolt-L3 = <1175000 1175000 1325000>; 193 opp-microvolt-L4 = <1150000 1150000 1325000>; 194 opp-microvolt-L5 = <1125000 1125000 1325000>; 195 clock-latency-ns = <40000>; 196 status = "disabled"; 197 }; 198 opp-1296000000 { 199 opp-hz = /bits/ 64 <1296000000>; 200 opp-microvolt = <1300000 1300000 1325000>; 201 opp-microvolt-L0 = <1300000 1300000 1325000>; 202 opp-microvolt-L1 = <1275000 1275000 1325000>; 203 opp-microvolt-L2 = <1250000 1250000 1325000>; 204 opp-microvolt-L3 = <1225000 1225000 1325000>; 205 opp-microvolt-L4 = <1200000 1200000 1325000>; 206 opp-microvolt-L5 = <1175000 1175000 1325000>; 207 clock-latency-ns = <40000>; 208 status = "disabled"; 209 }; 210 }; 211 212 rk3308bs_cpu0_opp_table: rk3308bs-cpu0-opp-table { 213 compatible = "operating-points-v2"; 214 opp-shared; 215 216 rockchip,temp-hysteresis = <5000>; 217 rockchip,low-temp = <0>; 218 rockchip,low-temp-min-volt = <900000>; 219 rockchip,max-volt = <1200000>; 220 rockchip,low-temp-adjust-volt = < 221 /* MHz MHz uV */ 222 0 1200 50000 223 >; 224 225 rockchip,evb-irdrop = <25000>; 226 nvmem-cells = <&cpu_leakage>; 227 nvmem-cell-names = "leakage"; 228 229 opp-408000000 { 230 opp-hz = /bits/ 64 <408000000>; 231 opp-microvolt = <850000 850000 1200000>; 232 clock-latency-ns = <40000>; 233 opp-suspend; 234 }; 235 opp-600000000 { 236 opp-hz = /bits/ 64 <600000000>; 237 opp-microvolt = <900000 900000 1200000>; 238 clock-latency-ns = <40000>; 239 }; 240 opp-816000000 { 241 opp-hz = /bits/ 64 <816000000>; 242 opp-microvolt = <1000000 1000000 1200000>; 243 clock-latency-ns = <40000>; 244 }; 245 opp-1008000000 { 246 opp-hz = /bits/ 64 <1008000000>; 247 opp-microvolt = <1125000 1125000 1200000>; 248 clock-latency-ns = <40000>; 249 status = "disabled"; 250 }; 251 opp-1104000000 { 252 opp-hz = /bits/ 64 <1104000000>; 253 opp-microvolt = <1200000 1200000 1200000>; 254 clock-latency-ns = <40000>; 255 status = "disabled"; 256 }; 257 }; 258 259 arm-pmu { 260 compatible = "arm,cortex-a35-pmu"; 261 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 266 }; 267 268 cpuinfo { 269 compatible = "rockchip,cpuinfo"; 270 nvmem-cells = <&otp_id>; 271 nvmem-cell-names = "id"; 272 }; 273 274 display_subsystem: display-subsystem { 275 compatible = "rockchip,display-subsystem"; 276 ports = <&vop_out>; 277 logo-memory-region = <&drm_logo>; 278 status = "disabled"; 279 280 route { 281 route_rgb: route-rgb { 282 status = "disabled"; 283 logo,uboot = "logo.bmp"; 284 /* logo,kernel = "logo_kernel.bmp"; */ 285 logo,mode = "center"; 286 charge_logo,mode = "center"; 287 connect = <&vop_out_rgb>; 288 }; 289 }; 290 }; 291 292 dmc: dmc { 293 compatible = "rockchip,rk3308-dmc"; 294 clocks = <&cru SCLK_DDRCLK>; 295 clock-names = "dmc_clk"; 296 operating-points-v2 = <&dmc_opp_table>, <&rk3308bs_dmc_opp_table>; 297 status = "disabled"; 298 }; 299 300 dmc_opp_table: dmc-opp-table { 301 compatible = "operating-points-v2"; 302 303 rockchip,evb-irdrop = <25000>; 304 305 opp-394000000 { 306 opp-hz = /bits/ 64 <394000000>; 307 opp-microvolt = <950000>; 308 }; 309 opp-452000000 { 310 opp-hz = /bits/ 64 <452000000>; 311 opp-microvolt = <975000>; 312 }; 313 opp-590000000 { 314 opp-hz = /bits/ 64 <590000000>; 315 opp-microvolt = <1000000>; 316 }; 317 }; 318 319 rk3308bs_dmc_opp_table: rk3308bs-dmc-opp-table { 320 compatible = "operating-points-v2"; 321 322 opp-394000000 { 323 opp-hz = /bits/ 64 <394000000>; 324 opp-microvolt = <900000>; 325 }; 326 opp-452000000 { 327 opp-hz = /bits/ 64 <452000000>; 328 opp-microvolt = <900000>; 329 }; 330 opp-590000000 { 331 opp-hz = /bits/ 64 <590000000>; 332 opp-microvolt = <900000>; 333 }; 334 }; 335 336 fiq_debugger: fiq-debugger { 337 compatible = "rockchip,fiq-debugger"; 338 rockchip,serial-id = <2>; 339 rockchip,wake-irq = <0>; 340 rockchip,irq-mode-enable = <1>; 341 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 342 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 343 status = "disabled"; 344 }; 345 346 mac_clkin: external-mac-clock { 347 compatible = "fixed-clock"; 348 clock-frequency = <50000000>; 349 clock-output-names = "mac_clkin"; 350 #clock-cells = <0>; 351 }; 352 353 psci { 354 compatible = "arm,psci-1.0"; 355 method = "smc"; 356 }; 357 358 ramoops_mem: ramoops_mem { 359 reg = <0x0 0x110000 0x0 0xf0000>; 360 reg-names = "ramoops_mem"; 361 }; 362 363 ramoops: ramoops { 364 compatible = "ramoops"; 365 record-size = <0x0 0x30000>; 366 console-size = <0x0 0xc0000>; 367 ftrace-size = <0x0 0x00000>; 368 pmsg-size = <0x0 0x00000>; 369 memory-region = <&ramoops_mem>; 370 }; 371 372 rgb: rgb { 373 compatible = "rockchip,rk3308-rgb"; 374 status = "disabled"; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&lcdc_ctl>; 377 378 ports { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 382 port@0 { 383 reg = <0>; 384 385 #address-cells = <1>; 386 #size-cells = <0>; 387 388 rgb_in_vop: endpoint@0 { 389 reg = <0>; 390 remote-endpoint = <&vop_out_rgb>; 391 }; 392 }; 393 394 }; 395 }; 396 397 reserved-memory { 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 402 drm_logo: drm-logo@00000000 { 403 compatible = "rockchip,drm-logo"; 404 reg = <0x0 0x0 0x0 0x0>; 405 }; 406 }; 407 408 rockchip_suspend: rockchip-suspend { 409 compatible = "rockchip,pm-rk3308"; 410 status = "disabled"; 411 rockchip,sleep-mode-config = < 412 (0 413 | RKPM_PMU_HW_PLLS_PD 414 ) 415 >; 416 rockchip,wakeup-config = < 417 (0 418 | RKPM_GPIO0_WAKEUP_EN 419 ) 420 >; 421 }; 422 423 timer { 424 compatible = "arm,armv8-timer"; 425 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 426 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 427 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 428 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 429 }; 430 431 xin24m: xin24m { 432 compatible = "fixed-clock"; 433 #clock-cells = <0>; 434 clock-frequency = <24000000>; 435 clock-output-names = "xin24m"; 436 }; 437 438 grf: grf@ff000000 { 439 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 440 reg = <0x0 0xff000000 0x0 0x10000>; 441 442 io_domains: io-domains { 443 compatible = "rockchip,rk3308-io-voltage-domain"; 444 status = "disabled"; 445 }; 446 447 pmu_pvtm: pmu-pvtm { 448 compatible = "rockchip,rk3308-pmu-pvtm"; 449 clocks = <&cru SCLK_PVTM_PMU>; 450 clock-names = "pmu"; 451 }; 452 453 reboot-mode { 454 compatible = "syscon-reboot-mode"; 455 offset = <0x500>; 456 mode-bootloader = <BOOT_BL_DOWNLOAD>; 457 mode-loader = <BOOT_BL_DOWNLOAD>; 458 mode-normal = <BOOT_NORMAL>; 459 mode-recovery = <BOOT_RECOVERY>; 460 mode-fastboot = <BOOT_FASTBOOT>; 461 mode-panic = <BOOT_PANIC>; 462 mode-watchdog = <BOOT_WATCHDOG>; 463 }; 464 }; 465 466 usb2phy_grf: syscon@ff008000 { 467 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; 468 reg = <0x0 0xff008000 0x0 0x4000>; 469 #address-cells = <1>; 470 #size-cells = <1>; 471 472 u2phy: usb2phy@100 { 473 compatible = "rockchip,rk3308-usb2phy"; 474 reg = <0x100 0x10>; 475 assigned-clocks = <&cru USB480M>; 476 assigned-clock-parents = <&u2phy>; 477 clocks = <&cru SCLK_USBPHY_REF>; 478 clock-names = "phyclk"; 479 clock-output-names = "usb480m_phy"; 480 #clock-cells = <0>; 481 status = "disabled"; 482 483 u2phy_otg: otg-port { 484 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "otg-bvalid", "otg-id", 488 "linestate"; 489 #phy-cells = <0>; 490 status = "disabled"; 491 }; 492 493 u2phy_host: host-port { 494 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "linestate"; 496 #phy-cells = <0>; 497 status = "disabled"; 498 }; 499 }; 500 }; 501 502 detect_grf: syscon@ff00b000 { 503 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 504 reg = <0x0 0xff00b000 0x0 0x1000>; 505 #address-cells = <1>; 506 #size-cells = <1>; 507 }; 508 509 core_grf: syscon@ff00c000 { 510 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 511 reg = <0x0 0xff00c000 0x0 0x1000>; 512 #address-cells = <1>; 513 #size-cells = <1>; 514 515 pvtm: pvtm { 516 compatible = "rockchip,rk3308-pvtm"; 517 clocks = <&cru SCLK_PVTM_CORE>; 518 clock-names = "core"; 519 }; 520 }; 521 522 i2c0: i2c@ff040000 { 523 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 524 reg = <0x0 0xff040000 0x0 0x1000>; 525 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 526 clock-names = "i2c", "pclk"; 527 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&i2c0_xfer>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 status = "disabled"; 533 }; 534 535 i2c1: i2c@ff050000 { 536 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 537 reg = <0x0 0xff050000 0x0 0x1000>; 538 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 539 clock-names = "i2c", "pclk"; 540 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&i2c1_xfer>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 status = "disabled"; 546 }; 547 548 i2c2: i2c@ff060000 { 549 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 550 reg = <0x0 0xff060000 0x0 0x1000>; 551 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 552 clock-names = "i2c", "pclk"; 553 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c2_xfer>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 i2c3: i2c@ff070000 { 562 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 563 reg = <0x0 0xff070000 0x0 0x1000>; 564 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 565 clock-names = "i2c", "pclk"; 566 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&i2c3m0_xfer>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 status = "disabled"; 572 }; 573 574 wdt: watchdog@ff080000 { 575 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; 576 reg = <0x0 0xff080000 0x0 0x100>; 577 clocks = <&cru PCLK_WDT>; 578 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 579 status = "disabled"; 580 }; 581 582 uart0: serial@ff0a0000 { 583 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 584 reg = <0x0 0xff0a0000 0x0 0x100>; 585 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 587 clock-names = "baudclk", "apb_pclk"; 588 reg-shift = <2>; 589 reg-io-width = <4>; 590 dmas = <&dmac0 4>, <&dmac0 5>; 591 dma-names = "tx", "rx"; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 594 status = "disabled"; 595 }; 596 597 uart1: serial@ff0b0000 { 598 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 599 reg = <0x0 0xff0b0000 0x0 0x100>; 600 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 602 clock-names = "baudclk", "apb_pclk"; 603 reg-shift = <2>; 604 reg-io-width = <4>; 605 dmas = <&dmac0 6>, <&dmac0 7>; 606 dma-names = "tx", "rx"; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 609 status = "disabled"; 610 }; 611 612 uart2: serial@ff0c0000 { 613 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 614 reg = <0x0 0xff0c0000 0x0 0x100>; 615 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 617 clock-names = "baudclk", "apb_pclk"; 618 reg-shift = <2>; 619 reg-io-width = <4>; 620 dmas = <&dmac0 8>, <&dmac0 9>; 621 dma-names = "tx", "rx"; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&uart2m0_xfer>; 624 status = "disabled"; 625 }; 626 627 uart3: serial@ff0d0000 { 628 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 629 reg = <0x0 0xff0d0000 0x0 0x100>; 630 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 632 clock-names = "baudclk", "apb_pclk"; 633 reg-shift = <2>; 634 reg-io-width = <4>; 635 dmas = <&dmac0 10>, <&dmac0 11>; 636 dma-names = "tx", "rx"; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&uart3_xfer>; 639 status = "disabled"; 640 }; 641 642 uart4: serial@ff0e0000 { 643 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 644 reg = <0x0 0xff0e0000 0x0 0x100>; 645 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 647 clock-names = "baudclk", "apb_pclk"; 648 reg-shift = <2>; 649 reg-io-width = <4>; 650 dmas = <&dmac1 18>, <&dmac1 19>; 651 dma-names = "tx", "rx"; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 654 status = "disabled"; 655 }; 656 657 spi0: spi@ff120000 { 658 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 659 reg = <0x0 0xff120000 0x0 0x1000>; 660 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 664 clock-names = "spiclk", "apb_pclk"; 665 dmas = <&dmac0 0>, <&dmac0 1>; 666 dma-names = "tx", "rx"; 667 pinctrl-names = "default", "high_speed"; 668 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 669 pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>; 670 status = "disabled"; 671 }; 672 673 spi1: spi@ff130000 { 674 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 675 reg = <0x0 0xff130000 0x0 0x1000>; 676 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 680 clock-names = "spiclk", "apb_pclk"; 681 dmas = <&dmac0 2>, <&dmac0 3>; 682 dma-names = "tx", "rx"; 683 pinctrl-names = "default", "high_speed"; 684 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 685 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>; 686 status = "disabled"; 687 }; 688 689 spi2: spi@ff140000 { 690 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 691 reg = <0x0 0xff140000 0x0 0x1000>; 692 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 696 clock-names = "spiclk", "apb_pclk"; 697 dmas = <&dmac1 16>, <&dmac1 17>; 698 dma-names = "tx", "rx"; 699 pinctrl-names = "default", "high_speed"; 700 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 701 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; 702 status = "disabled"; 703 }; 704 705 pwm8: pwm@ff160000 { 706 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 707 reg = <0x0 0xff160000 0x0 0x10>; 708 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 710 clock-names = "pwm", "pclk"; 711 pinctrl-names = "active"; 712 pinctrl-0 = <&pwm8_pin>; 713 #pwm-cells = <3>; 714 status = "disabled"; 715 }; 716 717 pwm9: pwm@ff160010 { 718 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 719 reg = <0x0 0xff160010 0x0 0x10>; 720 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 722 clock-names = "pwm", "pclk"; 723 pinctrl-names = "active"; 724 pinctrl-0 = <&pwm9_pin>; 725 #pwm-cells = <3>; 726 status = "disabled"; 727 }; 728 729 pwm10: pwm@ff160020 { 730 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 731 reg = <0x0 0xff160020 0x0 0x10>; 732 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 734 clock-names = "pwm", "pclk"; 735 pinctrl-names = "active"; 736 pinctrl-0 = <&pwm10_pin>; 737 #pwm-cells = <3>; 738 status = "disabled"; 739 }; 740 741 pwm11: pwm@ff160030 { 742 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 743 reg = <0x0 0xff160030 0x0 0x10>; 744 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 746 clock-names = "pwm", "pclk"; 747 pinctrl-names = "active"; 748 pinctrl-0 = <&pwm11_pin>; 749 #pwm-cells = <3>; 750 status = "disabled"; 751 }; 752 753 pwm4: pwm@ff170000 { 754 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 755 reg = <0x0 0xff170000 0x0 0x10>; 756 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 758 clock-names = "pwm", "pclk"; 759 pinctrl-names = "active"; 760 pinctrl-0 = <&pwm4_pin>; 761 #pwm-cells = <3>; 762 status = "disabled"; 763 }; 764 765 pwm5: pwm@ff170010 { 766 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 767 reg = <0x0 0xff170010 0x0 0x10>; 768 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 770 clock-names = "pwm", "pclk"; 771 pinctrl-names = "active"; 772 pinctrl-0 = <&pwm5_pin>; 773 #pwm-cells = <3>; 774 status = "disabled"; 775 }; 776 777 pwm6: pwm@ff170020 { 778 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 779 reg = <0x0 0xff170020 0x0 0x10>; 780 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 782 clock-names = "pwm", "pclk"; 783 pinctrl-names = "active"; 784 pinctrl-0 = <&pwm6_pin>; 785 #pwm-cells = <3>; 786 status = "disabled"; 787 }; 788 789 pwm7: pwm@ff170030 { 790 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 791 reg = <0x0 0xff170030 0x0 0x10>; 792 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 794 clock-names = "pwm", "pclk"; 795 pinctrl-names = "active"; 796 pinctrl-0 = <&pwm7_pin>; 797 #pwm-cells = <3>; 798 status = "disabled"; 799 }; 800 801 pwm0: pwm@ff180000 { 802 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 803 reg = <0x0 0xff180000 0x0 0x10>; 804 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 806 clock-names = "pwm", "pclk"; 807 pinctrl-names = "active"; 808 pinctrl-0 = <&pwm0_pin>; 809 #pwm-cells = <3>; 810 status = "disabled"; 811 }; 812 813 pwm1: pwm@ff180010 { 814 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 815 reg = <0x0 0xff180010 0x0 0x10>; 816 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 818 clock-names = "pwm", "pclk"; 819 pinctrl-names = "active"; 820 pinctrl-0 = <&pwm1_pin>; 821 #pwm-cells = <3>; 822 status = "disabled"; 823 }; 824 825 pwm2: pwm@ff180020 { 826 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 827 reg = <0x0 0xff180020 0x0 0x10>; 828 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 830 clock-names = "pwm", "pclk"; 831 pinctrl-names = "active"; 832 pinctrl-0 = <&pwm2_pin>; 833 #pwm-cells = <3>; 834 status = "disabled"; 835 }; 836 837 pwm3: pwm@ff180030 { 838 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 839 reg = <0x0 0xff180030 0x0 0x10>; 840 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 842 clock-names = "pwm", "pclk"; 843 pinctrl-names = "active"; 844 pinctrl-0 = <&pwm3_pin>; 845 #pwm-cells = <3>; 846 status = "disabled"; 847 }; 848 849 rktimer: rktimer@ff1a0000 { 850 compatible = "rockchip,rk3288-timer"; 851 reg = <0x0 0xff1a0000 0x0 0x20>; 852 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 854 clock-names = "pclk", "timer"; 855 }; 856 857 rk_timer_rtc: rk-timer-rtc@ff1a0020 { 858 compatible = "rockchip,rk3308-timer-rtc"; 859 reg = <0x0 0xff1a0020 0x0 0x20>; 860 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 862 clock-names = "pclk", "timer"; 863 status = "disabled"; 864 }; 865 866 saradc: saradc@ff1e0000 { 867 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 868 reg = <0x0 0xff1e0000 0x0 0x100>; 869 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 871 clock-names = "saradc", "apb_pclk"; 872 #io-channel-cells = <1>; 873 resets = <&cru SRST_SARADC_P>; 874 reset-names = "saradc-apb"; 875 status = "disabled"; 876 }; 877 878 thermal_zones: thermal-zones { 879 880 soc_thermal: soc-thermal { 881 polling-delay-passive = <20>; 882 polling-delay = <1000>; 883 sustainable-power = <360>; 884 885 thermal-sensors = <&tsadc 0>; 886 887 trips { 888 threshold: trip-point@0 { 889 temperature = <70000>; 890 hysteresis = <2000>; 891 type = "passive"; 892 }; 893 target: trip-point@1 { 894 temperature = <85000>; 895 hysteresis = <2000>; 896 type = "passive"; 897 }; 898 soc_crit: soc-crit { 899 temperature = <115000>; 900 hysteresis = <2000>; 901 type = "critical"; 902 }; 903 }; 904 905 cooling-maps { 906 map0 { 907 trip = <&target>; 908 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 909 contribution = <4096>; 910 }; 911 }; 912 }; 913 914 gpu_thermal: gpu-thermal { 915 polling-delay-passive = <100>; /* milliseconds */ 916 polling-delay = <1000>; /* milliseconds */ 917 918 thermal-sensors = <&tsadc 1>; 919 }; 920 }; 921 922 tsadc: tsadc@ff1f0000 { 923 compatible = "rockchip,rk3308-tsadc"; 924 reg = <0x0 0xff1f0000 0x0 0x100>; 925 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 926 rockchip,grf = <&grf>; 927 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 928 clock-names = "tsadc", "apb_pclk"; 929 assigned-clocks = <&cru SCLK_TSADC>; 930 assigned-clock-rates = <50000>; 931 resets = <&cru SRST_TSADC>; 932 reset-names = "tsadc-apb"; 933 pinctrl-names = "gpio", "otpout"; 934 pinctrl-0 = <&tsadc_otp_pin>; 935 pinctrl-1 = <&tsadc_otp_out>; 936 #thermal-sensor-cells = <1>; 937 rockchip,hw-tshut-temp = <120000>; 938 status = "disabled"; 939 }; 940 941 otp: otp@ff210000 { 942 compatible = "rockchip,rk3308-otp"; 943 reg = <0x0 0xff210000 0x0 0x4000>; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 947 <&cru PCLK_OTP_PHY>; 948 clock-names = "otp", "apb_pclk", "phy"; 949 resets = <&cru SRST_OTP_PHY>; 950 reset-names = "otp_phy"; 951 952 /* Data cells */ 953 otp_id: id@7 { 954 reg = <0x07 0x10>; 955 }; 956 cpu_leakage: cpu-leakage@17 { 957 reg = <0x17 0x1>; 958 }; 959 logic_leakage: logic-leakage@18 { 960 reg = <0x18 0x1>; 961 }; 962 }; 963 964 dmac0: dma-controller@ff2c0000 { 965 compatible = "arm,pl330", "arm,primecell"; 966 reg = <0x0 0xff2c0000 0x0 0x4000>; 967 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 969 arm,pl330-periph-burst; 970 clocks = <&cru ACLK_DMAC0>; 971 clock-names = "apb_pclk"; 972 #dma-cells = <1>; 973 }; 974 975 dmac1: dma-controller@ff2d0000 { 976 compatible = "arm,pl330", "arm,primecell"; 977 reg = <0x0 0xff2d0000 0x0 0x4000>; 978 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 980 arm,pl330-periph-burst; 981 clocks = <&cru ACLK_DMAC1>; 982 clock-names = "apb_pclk"; 983 #dma-cells = <1>; 984 }; 985 986 vop: vop@ff2e0000 { 987 compatible = "rockchip,rk3308-vop"; 988 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 989 reg-names = "regs", "gamma_lut"; 990 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 992 <&cru HCLK_VOP>; 993 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 994 status = "disabled"; 995 996 vop_out: port { 997 #address-cells = <1>; 998 #size-cells = <0>; 999 1000 vop_out_rgb: endpoint@0 { 1001 reg = <0>; 1002 remote-endpoint = <&rgb_in_vop>; 1003 }; 1004 }; 1005 }; 1006 1007 rng: rng@ff2f0400 { 1008 compatible = "rockchip,cryptov2-rng"; 1009 reg = <0x0 0xff2f0400 0x0 0x80>; 1010 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, 1011 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; 1012 clock-names = "clk_crypto", "clk_crypto_apk", 1013 "aclk_crypto", "hclk_crypto"; 1014 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, 1015 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; 1016 assigned-clock-rates = <150000000>, <150000000>, 1017 <200000000>, <100000000>; 1018 resets = <&cru SRST_CRYPTO>; 1019 reset-names = "reset"; 1020 status = "disabled"; 1021 }; 1022 1023 i2s_8ch_0: i2s@ff300000 { 1024 compatible = "rockchip,rk3308-i2s-tdm"; 1025 reg = <0x0 0xff300000 0x0 0x1000>; 1026 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>, 1028 <&cru SCLK_I2S0_8CH_TX_SRC>, 1029 <&cru SCLK_I2S0_8CH_RX_SRC>, 1030 <&cru PLL_VPLL0>, 1031 <&cru PLL_VPLL1>; 1032 clock-names = "mclk_tx", "mclk_rx", "hclk", 1033 "mclk_tx_src", "mclk_rx_src", 1034 "mclk_root0", "mclk_root1"; 1035 dmas = <&dmac1 0>, <&dmac1 1>; 1036 dma-names = "tx", "rx"; 1037 resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>; 1038 reset-names = "tx-m", "rx-m"; 1039 rockchip,cru = <&cru>; 1040 rockchip,grf = <&grf>; 1041 rockchip,mclk-calibrate; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&i2s_8ch_0_sclktx 1044 &i2s_8ch_0_sclkrx 1045 &i2s_8ch_0_lrcktx 1046 &i2s_8ch_0_lrckrx 1047 &i2s_8ch_0_sdi0 1048 &i2s_8ch_0_sdi1 1049 &i2s_8ch_0_sdi2 1050 &i2s_8ch_0_sdi3 1051 &i2s_8ch_0_sdo0 1052 &i2s_8ch_0_sdo1 1053 &i2s_8ch_0_sdo2 1054 &i2s_8ch_0_sdo3 1055 &i2s_8ch_0_mclk>; 1056 status = "disabled"; 1057 }; 1058 1059 i2s_8ch_1: i2s@ff310000 { 1060 compatible = "rockchip,rk3308-i2s-tdm"; 1061 reg = <0x0 0xff310000 0x0 0x1000>; 1062 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>, 1064 <&cru SCLK_I2S1_8CH_TX_SRC>, 1065 <&cru SCLK_I2S1_8CH_RX_SRC>, 1066 <&cru PLL_VPLL0>, 1067 <&cru PLL_VPLL1>; 1068 clock-names = "mclk_tx", "mclk_rx", "hclk", 1069 "mclk_tx_src", "mclk_rx_src", 1070 "mclk_root0", "mclk_root1"; 1071 dmas = <&dmac1 2>, <&dmac1 3>; 1072 dma-names = "tx", "rx"; 1073 resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>; 1074 reset-names = "tx-m", "rx-m"; 1075 rockchip,cru = <&cru>; 1076 rockchip,grf = <&grf>; 1077 rockchip,mclk-calibrate; 1078 rockchip,io-multiplex; 1079 status = "disabled"; 1080 }; 1081 1082 i2s_8ch_2: i2s@ff320000 { 1083 compatible = "rockchip,rk3308-i2s-tdm"; 1084 reg = <0x0 0xff320000 0x0 0x1000>; 1085 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&cru SCLK_I2S2_8CH_TX>, <&cru SCLK_I2S2_8CH_RX>, <&cru HCLK_I2S2_8CH>, 1087 <&cru SCLK_I2S2_8CH_TX_SRC>, 1088 <&cru SCLK_I2S2_8CH_RX_SRC>, 1089 <&cru PLL_VPLL0>, 1090 <&cru PLL_VPLL1>; 1091 clock-names = "mclk_tx", "mclk_rx", "hclk", 1092 "mclk_tx_src", "mclk_rx_src", 1093 "mclk_root0", "mclk_root1"; 1094 dmas = <&dmac1 4>, <&dmac1 5>; 1095 dma-names = "tx", "rx"; 1096 resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>; 1097 reset-names = "tx-m", "rx-m"; 1098 rockchip,cru = <&cru>; 1099 rockchip,grf = <&grf>; 1100 rockchip,mclk-calibrate; 1101 status = "disabled"; 1102 }; 1103 1104 i2s_8ch_3: i2s@ff330000 { 1105 compatible = "rockchip,rk3308-i2s-tdm"; 1106 reg = <0x0 0xff330000 0x0 0x1000>; 1107 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&cru SCLK_I2S3_8CH_TX>, <&cru SCLK_I2S3_8CH_RX>, <&cru HCLK_I2S3_8CH>, 1109 <&cru SCLK_I2S3_8CH_TX_SRC>, 1110 <&cru SCLK_I2S3_8CH_RX_SRC>, 1111 <&cru PLL_VPLL0>, 1112 <&cru PLL_VPLL1>; 1113 clock-names = "mclk_tx", "mclk_rx", "hclk", 1114 "mclk_tx_src", "mclk_rx_src", 1115 "mclk_root0", "mclk_root1"; 1116 dmas = <&dmac1 7>; 1117 dma-names = "rx"; 1118 resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>; 1119 reset-names = "tx-m", "rx-m"; 1120 rockchip,cru = <&cru>; 1121 rockchip,grf = <&grf>; 1122 rockchip,mclk-calibrate; 1123 status = "disabled"; 1124 }; 1125 1126 i2s_2ch_0: i2s@ff350000 { 1127 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 1128 reg = <0x0 0xff350000 0x0 0x1000>; 1129 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 1131 clock-names = "i2s_clk", "i2s_hclk"; 1132 dmas = <&dmac1 8>, <&dmac1 9>; 1133 dma-names = "tx", "rx"; 1134 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 1135 reset-names = "reset-m", "reset-h"; 1136 rockchip,clk-trcm = <1>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&i2s_2ch_0_sclk 1139 &i2s_2ch_0_lrck 1140 &i2s_2ch_0_sdi 1141 &i2s_2ch_0_sdo>; 1142 status = "disabled"; 1143 }; 1144 1145 i2s_2ch_1: i2s@ff360000 { 1146 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 1147 reg = <0x0 0xff360000 0x0 0x1000>; 1148 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 1150 clock-names = "i2s_clk", "i2s_hclk"; 1151 dmas = <&dmac1 11>; 1152 dma-names = "rx"; 1153 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 1154 reset-names = "reset-m", "reset-h"; 1155 status = "disabled"; 1156 }; 1157 1158 pdm_8ch: pdm@ff380000 { 1159 compatible = "rockchip,rk3308-pdm", "rockchip,pdm"; 1160 reg = <0x0 0xff380000 0x0 0x1000>; 1161 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 1162 clock-names = "pdm_clk", "pdm_hclk"; 1163 dmas = <&dmac1 12>; 1164 dma-names = "rx"; 1165 resets = <&cru SRST_PDM_M>; 1166 reset-names = "pdm-m"; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&pdm_m2_clk 1169 &pdm_m2_sdi0 1170 &pdm_m2_sdi1 1171 &pdm_m2_sdi2 1172 &pdm_m2_sdi3>; 1173 status = "disabled"; 1174 }; 1175 1176 spdif_tx: spdif-tx@ff3a0000 { 1177 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; 1178 reg = <0x0 0xff3a0000 0x0 0x1000>; 1179 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1180 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 1181 clock-names = "mclk", "hclk"; 1182 dmas = <&dmac1 13>; 1183 dma-names = "tx"; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&spdif_out>; 1186 status = "disabled"; 1187 }; 1188 1189 spdif_rx: spdif-rx@ff3b0000 { 1190 compatible = "rockchip,rk3308-spdifrx"; 1191 reg = <0x0 0xff3b0000 0x0 0x1000>; 1192 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&cru SCLK_SPDIF_RX>, <&cru HCLK_SPDIFRX>; 1194 clock-names = "mclk", "hclk"; 1195 dmas = <&dmac1 14>; 1196 dma-names = "rx"; 1197 resets = <&cru SRST_SPDIFRX_M>; 1198 reset-names = "spdifrx-m"; 1199 pinctrl-names = "default"; 1200 pinctrl-0 = <&spdif_in>; 1201 status = "disabled"; 1202 }; 1203 1204 vad: vad@ff3c0000 { 1205 compatible = "rockchip,rk3308-vad"; 1206 reg = <0x0 0xff3c0000 0x0 0x10000>; 1207 reg-names = "vad"; 1208 clocks = <&cru HCLK_VAD>; 1209 clock-names = "hclk"; 1210 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1211 rockchip,audio-sram = <&vad_sram>; 1212 rockchip,audio-src = <0>; 1213 rockchip,det-channel = <0>; 1214 rockchip,mode = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 usb20_otg: usb@ff400000 { 1219 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 1220 "snps,dwc2"; 1221 reg = <0x0 0xff400000 0x0 0x40000>; 1222 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&cru HCLK_OTG>; 1224 clock-names = "otg"; 1225 dr_mode = "otg"; 1226 g-np-tx-fifo-size = <16>; 1227 g-rx-fifo-size = <280>; 1228 g-tx-fifo-size = <256 128 128 64 32 16>; 1229 phys = <&u2phy_otg>; 1230 phy-names = "usb2-phy"; 1231 status = "disabled"; 1232 }; 1233 1234 usb_host0_ehci: usb@ff440000 { 1235 compatible = "generic-ehci"; 1236 reg = <0x0 0xff440000 0x0 0x10000>; 1237 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 1239 clock-names = "usbhost", "arbiter", "utmi"; 1240 phys = <&u2phy_host>; 1241 phy-names = "usb"; 1242 status = "disabled"; 1243 }; 1244 1245 usb_host0_ohci: usb@ff450000 { 1246 compatible = "generic-ohci"; 1247 reg = <0x0 0xff450000 0x0 0x10000>; 1248 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1249 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 1250 clock-names = "usbhost", "arbiter", "utmi"; 1251 phys = <&u2phy_host>; 1252 phy-names = "usb"; 1253 status = "disabled"; 1254 }; 1255 1256 sdmmc: mmc@ff480000 { 1257 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 1258 reg = <0x0 0xff480000 0x0 0x4000>; 1259 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1260 bus-width = <4>; 1261 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 1262 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1263 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1264 fifo-depth = <0x100>; 1265 max-frequency = <150000000>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1268 status = "disabled"; 1269 }; 1270 1271 emmc: mmc@ff490000 { 1272 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 1273 reg = <0x0 0xff490000 0x0 0x4000>; 1274 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1275 bus-width = <8>; 1276 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1277 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1279 fifo-depth = <0x100>; 1280 max-frequency = <150000000>; 1281 status = "disabled"; 1282 }; 1283 1284 sdio: mmc@ff4a0000 { 1285 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 1286 reg = <0x0 0xff4a0000 0x0 0x4000>; 1287 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1288 bus-width = <4>; 1289 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1290 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1291 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1292 fifo-depth = <0x100>; 1293 max-frequency = <150000000>; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 1296 status = "disabled"; 1297 }; 1298 1299 nfc: nand-controller@ff4b0000 { 1300 compatible = "rockchip,rk3308-nfc", 1301 "rockchip,rv1108-nfc"; 1302 reg = <0x0 0xff4b0000 0x0 0x4000>; 1303 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 1305 clock-names = "ahb", "nfc"; 1306 assigned-clocks = <&cru SCLK_NANDC>; 1307 assigned-clock-rates = <150000000>; 1308 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 1309 &flash_rdn &flash_rdy &flash_wrn>; 1310 pinctrl-names = "default"; 1311 status = "disabled"; 1312 }; 1313 1314 nandc: nandc@ff4b0000 { 1315 compatible = "rockchip,rk-nandc"; 1316 reg = <0x0 0xff4b0000 0x0 0x4000>; 1317 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1318 nandc_id = <0>; 1319 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 1320 clock-names = "clk_nandc", "hclk_nandc"; 1321 status = "disabled"; 1322 }; 1323 1324 mac: ethernet@ff4e0000 { 1325 compatible = "rockchip,rk3308-mac"; 1326 reg = <0x0 0xff4e0000 0x0 0x10000>; 1327 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1328 interrupt-names = "macirq"; 1329 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 1330 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 1331 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 1332 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 1333 clock-names = "stmmaceth", "mac_clk_rx", 1334 "mac_clk_tx", "clk_mac_ref", 1335 "clk_mac_refout", "aclk_mac", 1336 "pclk_mac", "clk_mac_speed"; 1337 phy-mode = "rmii"; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 1340 resets = <&cru SRST_MAC_A>; 1341 reset-names = "stmmaceth"; 1342 rockchip,grf = <&grf>; 1343 status = "disabled"; 1344 }; 1345 1346 sfc: spi@ff4c0000 { 1347 compatible = "rockchip,sfc"; 1348 reg = <0x0 0xff4c0000 0x0 0x4000>; 1349 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1351 clock-names = "clk_sfc", "hclk_sfc"; 1352 assigned-clocks = <&cru SCLK_SFC>; 1353 assigned-clock-rates = <100000000>; 1354 status = "disabled"; 1355 }; 1356 1357 cru: clock-controller@ff500000 { 1358 compatible = "rockchip,rk3308-cru"; 1359 reg = <0x0 0xff500000 0x0 0x1000>; 1360 rockchip,grf = <&grf>; 1361 rockchip,boost = <&cpu_boost>; 1362 #clock-cells = <1>; 1363 #reset-cells = <1>; 1364 assigned-clocks = <&cru SCLK_RTC32K>; 1365 assigned-clock-rates = <32768>; 1366 }; 1367 1368 cpu_boost: cpu-boost@ff550000 { 1369 compatible = "syscon"; 1370 reg = <0x0 0xff550000 0x0 0x1000>; 1371 }; 1372 1373 acodec: acodec@ff560000 { 1374 compatible = "rockchip,rk3308-codec"; 1375 reg = <0x0 0xff560000 0x0 0x10000>; 1376 rockchip,grf = <&grf>; 1377 rockchip,detect-grf = <&detect_grf>; 1378 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1380 clocks = <&cru PCLK_ACODEC>, 1381 <&cru SCLK_I2S2_8CH_TX_OUT>, 1382 <&cru SCLK_I2S2_8CH_RX_OUT>; 1383 clock-names = "acodec", "mclk_tx", "mclk_rx"; 1384 resets = <&cru SRST_ACODEC_P>; 1385 reset-names = "acodec-reset"; 1386 spk_ctl-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 1387 status = "disabled"; 1388 }; 1389 1390 gic: interrupt-controller@ff580000 { 1391 compatible = "arm,gic-400"; 1392 reg = <0x0 0xff581000 0x0 0x1000>, 1393 <0x0 0xff582000 0x0 0x2000>, 1394 <0x0 0xff584000 0x0 0x2000>, 1395 <0x0 0xff586000 0x0 0x2000>; 1396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1397 #interrupt-cells = <3>; 1398 interrupt-controller; 1399 #address-cells = <0>; 1400 }; 1401 1402 sram: sram@fff80000 { 1403 compatible = "mmio-sram"; 1404 reg = <0x0 0xfff80000 0x0 0x40000>; 1405 ranges = <0 0x0 0xfff80000 0x40000>; 1406 #address-cells = <1>; 1407 #size-cells = <1>; 1408 1409 /* reserved for ddr dvfs and system suspend/resume */ 1410 ddr-sram@0 { 1411 reg = <0x0 0x8000>; 1412 }; 1413 1414 /* reserved for vad audio buffer */ 1415 vad_sram: vad-sram@8000 { 1416 reg = <0x8000 0x38000>; 1417 }; 1418 }; 1419 1420 rockchip_system_monitor: rockchip-system-monitor { 1421 compatible = "rockchip,system-monitor"; 1422 1423 rockchip,thermal-zone = "soc-thermal"; 1424 rockchip,polling-delay = <200>; /* milliseconds */ 1425 }; 1426 1427 pinctrl: pinctrl { 1428 compatible = "rockchip,rk3308-pinctrl"; 1429 rockchip,grf = <&grf>; 1430 #address-cells = <2>; 1431 #size-cells = <2>; 1432 ranges; 1433 1434 gpio0: gpio0@ff220000 { 1435 compatible = "rockchip,gpio-bank"; 1436 reg = <0x0 0xff220000 0x0 0x100>; 1437 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1438 clocks = <&cru PCLK_GPIO0>; 1439 gpio-controller; 1440 #gpio-cells = <2>; 1441 interrupt-controller; 1442 #interrupt-cells = <2>; 1443 }; 1444 1445 gpio1: gpio1@ff230000 { 1446 compatible = "rockchip,gpio-bank"; 1447 reg = <0x0 0xff230000 0x0 0x100>; 1448 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1449 clocks = <&cru PCLK_GPIO1>; 1450 gpio-controller; 1451 #gpio-cells = <2>; 1452 interrupt-controller; 1453 #interrupt-cells = <2>; 1454 }; 1455 1456 gpio2: gpio2@ff240000 { 1457 compatible = "rockchip,gpio-bank"; 1458 reg = <0x0 0xff240000 0x0 0x100>; 1459 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1460 clocks = <&cru PCLK_GPIO2>; 1461 gpio-controller; 1462 #gpio-cells = <2>; 1463 interrupt-controller; 1464 #interrupt-cells = <2>; 1465 }; 1466 1467 gpio3: gpio3@ff250000 { 1468 compatible = "rockchip,gpio-bank"; 1469 reg = <0x0 0xff250000 0x0 0x100>; 1470 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1471 clocks = <&cru PCLK_GPIO3>; 1472 gpio-controller; 1473 #gpio-cells = <2>; 1474 interrupt-controller; 1475 #interrupt-cells = <2>; 1476 }; 1477 1478 gpio4: gpio4@ff260000 { 1479 compatible = "rockchip,gpio-bank"; 1480 reg = <0x0 0xff260000 0x0 0x100>; 1481 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1482 clocks = <&cru PCLK_GPIO4>; 1483 gpio-controller; 1484 #gpio-cells = <2>; 1485 interrupt-controller; 1486 #interrupt-cells = <2>; 1487 }; 1488 1489 pcfg_pull_up: pcfg-pull-up { 1490 bias-pull-up; 1491 }; 1492 1493 pcfg_pull_down: pcfg-pull-down { 1494 bias-pull-down; 1495 }; 1496 1497 pcfg_pull_none: pcfg-pull-none { 1498 bias-disable; 1499 }; 1500 1501 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1502 bias-disable; 1503 drive-strength = <2>; 1504 }; 1505 1506 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1507 bias-pull-up; 1508 drive-strength = <2>; 1509 }; 1510 1511 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1512 bias-pull-up; 1513 drive-strength = <4>; 1514 }; 1515 1516 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1517 bias-disable; 1518 drive-strength = <4>; 1519 }; 1520 1521 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1522 bias-pull-down; 1523 drive-strength = <4>; 1524 }; 1525 1526 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1527 bias-disable; 1528 drive-strength = <8>; 1529 }; 1530 1531 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1532 bias-pull-up; 1533 drive-strength = <8>; 1534 }; 1535 1536 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1537 bias-disable; 1538 drive-strength = <12>; 1539 }; 1540 1541 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1542 bias-pull-up; 1543 drive-strength = <12>; 1544 }; 1545 1546 pcfg_pull_none_smt: pcfg-pull-none-smt { 1547 bias-disable; 1548 input-schmitt-enable; 1549 }; 1550 1551 pcfg_output_high: pcfg-output-high { 1552 output-high; 1553 }; 1554 1555 pcfg_output_low: pcfg-output-low { 1556 output-low; 1557 }; 1558 1559 pcfg_input_high: pcfg-input-high { 1560 bias-pull-up; 1561 input-enable; 1562 }; 1563 1564 pcfg_input: pcfg-input { 1565 input-enable; 1566 }; 1567 1568 can-m0 { 1569 canm0_pins: canm0-pins { 1570 rockchip,pins = 1571 /* can_rxd_m0 */ 1572 <0 RK_PB3 2 &pcfg_pull_none>, 1573 /* can_txd_m0 */ 1574 <0 RK_PB4 2 &pcfg_pull_none>; 1575 }; 1576 }; 1577 1578 can-m1 { 1579 canm1_pins: canm1-pins { 1580 rockchip,pins = 1581 /* can_rxd_m1 */ 1582 <1 RK_PC6 5 &pcfg_pull_none>, 1583 /* can_txd_m1 */ 1584 <1 RK_PC7 5 &pcfg_pull_none>; 1585 }; 1586 }; 1587 1588 can-m2 { 1589 canm2_pins: canm2-pins { 1590 rockchip,pins = 1591 /* can_rxd_m2 */ 1592 <2 RK_PA2 4 &pcfg_pull_none>, 1593 /* can_txd_m2 */ 1594 <2 RK_PA3 4 &pcfg_pull_none>; 1595 }; 1596 }; 1597 1598 emmc { 1599 emmc_clk: emmc-clk { 1600 rockchip,pins = 1601 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 1602 }; 1603 1604 emmc_cmd: emmc-cmd { 1605 rockchip,pins = 1606 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 1607 }; 1608 1609 emmc_pwren: emmc-pwren { 1610 rockchip,pins = 1611 <3 RK_PB3 2 &pcfg_pull_none>; 1612 }; 1613 1614 emmc_rstn: emmc-rstn { 1615 rockchip,pins = 1616 <3 RK_PB2 2 &pcfg_pull_none>; 1617 }; 1618 1619 emmc_bus1: emmc-bus1 { 1620 rockchip,pins = 1621 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 1622 }; 1623 1624 emmc_bus4: emmc-bus4 { 1625 rockchip,pins = 1626 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1627 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1628 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1629 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 1630 }; 1631 1632 emmc_bus8: emmc-bus8 { 1633 rockchip,pins = 1634 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1635 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1636 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1637 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 1638 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 1639 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 1640 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 1641 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 1642 }; 1643 }; 1644 1645 ext_micbias { 1646 ext_micbias_en: ext-micbias-en { 1647 rockchip,pins = 1648 <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 1649 }; 1650 }; 1651 1652 flash { 1653 flash_csn0: flash-csn0 { 1654 rockchip,pins = 1655 <3 RK_PB5 1 &pcfg_pull_none>; 1656 }; 1657 1658 flash_rdy: flash-rdy { 1659 rockchip,pins = 1660 <3 RK_PB4 1 &pcfg_pull_none>; 1661 }; 1662 1663 flash_ale: flash-ale { 1664 rockchip,pins = 1665 <3 RK_PB3 1 &pcfg_pull_none>; 1666 }; 1667 1668 flash_cle: flash-cle { 1669 rockchip,pins = 1670 <3 RK_PB1 1 &pcfg_pull_none>; 1671 }; 1672 1673 flash_wrn: flash-wrn { 1674 rockchip,pins = 1675 <3 RK_PB0 1 &pcfg_pull_none>; 1676 }; 1677 1678 flash_rdn: flash-rdn { 1679 rockchip,pins = 1680 <3 RK_PB2 1 &pcfg_pull_none>; 1681 }; 1682 1683 flash_bus8: flash-bus8 { 1684 rockchip,pins = 1685 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1686 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1687 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1688 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1689 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1690 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1691 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1692 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1693 }; 1694 }; 1695 1696 gmac { 1697 rmii_pins: rmii-pins { 1698 rockchip,pins = 1699 /* mac_txen */ 1700 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1701 /* mac_txd1 */ 1702 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1703 /* mac_txd0 */ 1704 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1705 /* mac_rxd0 */ 1706 <1 RK_PC4 3 &pcfg_pull_none>, 1707 /* mac_rxd1 */ 1708 <1 RK_PC5 3 &pcfg_pull_none>, 1709 /* mac_rxer */ 1710 <1 RK_PB7 3 &pcfg_pull_none>, 1711 /* mac_rxdv */ 1712 <1 RK_PC0 3 &pcfg_pull_none>, 1713 /* mac_mdio */ 1714 <1 RK_PB6 3 &pcfg_pull_none>, 1715 /* mac_mdc */ 1716 <1 RK_PB5 3 &pcfg_pull_none>; 1717 }; 1718 1719 mac_refclk_12ma: mac-refclk-12ma { 1720 rockchip,pins = 1721 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1722 }; 1723 1724 mac_refclk: mac-refclk { 1725 rockchip,pins = 1726 <1 RK_PB4 3 &pcfg_pull_none>; 1727 }; 1728 }; 1729 1730 gmac-m1 { 1731 rmiim1_pins: rmiim1-pins { 1732 rockchip,pins = 1733 /* mac_txen */ 1734 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 1735 /* mac_txd1 */ 1736 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 1737 /* mac_txd0 */ 1738 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 1739 /* mac_rxd0 */ 1740 <4 RK_PA2 2 &pcfg_pull_none>, 1741 /* mac_rxd1 */ 1742 <4 RK_PA3 2 &pcfg_pull_none>, 1743 /* mac_rxer */ 1744 <4 RK_PA0 2 &pcfg_pull_none>, 1745 /* mac_rxdv */ 1746 <4 RK_PA1 2 &pcfg_pull_none>, 1747 /* mac_mdio */ 1748 <4 RK_PB6 2 &pcfg_pull_none>, 1749 /* mac_mdc */ 1750 <4 RK_PB5 2 &pcfg_pull_none>; 1751 }; 1752 1753 macm1_refclk_12ma: macm1-refclk-12ma { 1754 rockchip,pins = 1755 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 1756 }; 1757 1758 macm1_refclk: macm1-refclk { 1759 rockchip,pins = 1760 <4 RK_PB4 2 &pcfg_pull_none>; 1761 }; 1762 }; 1763 1764 i2c0 { 1765 i2c0_xfer: i2c0-xfer { 1766 rockchip,pins = 1767 <1 RK_PD0 2 &pcfg_pull_none_smt>, 1768 <1 RK_PD1 2 &pcfg_pull_none_smt>; 1769 }; 1770 }; 1771 1772 i2c1 { 1773 i2c1_xfer: i2c1-xfer { 1774 rockchip,pins = 1775 <0 RK_PB3 1 &pcfg_pull_none_smt>, 1776 <0 RK_PB4 1 &pcfg_pull_none_smt>; 1777 }; 1778 }; 1779 1780 i2c2 { 1781 i2c2_xfer: i2c2-xfer { 1782 rockchip,pins = 1783 <2 RK_PA2 3 &pcfg_pull_none_smt>, 1784 <2 RK_PA3 3 &pcfg_pull_none_smt>; 1785 }; 1786 }; 1787 1788 i2c3-m0 { 1789 i2c3m0_xfer: i2c3m0-xfer { 1790 rockchip,pins = 1791 <0 RK_PB7 2 &pcfg_pull_none_smt>, 1792 <0 RK_PC0 2 &pcfg_pull_none_smt>; 1793 }; 1794 }; 1795 1796 i2c3-m1 { 1797 i2c3m1_xfer: i2c3m1-xfer { 1798 rockchip,pins = 1799 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1800 <3 RK_PB5 2 &pcfg_pull_none_smt>; 1801 }; 1802 }; 1803 1804 i2c3-m2 { 1805 i2c3m2_xfer: i2c3m2-xfer { 1806 rockchip,pins = 1807 <2 RK_PA1 3 &pcfg_pull_none_smt>, 1808 <2 RK_PA0 3 &pcfg_pull_none_smt>; 1809 }; 1810 }; 1811 1812 i2s_2ch_0 { 1813 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 1814 rockchip,pins = 1815 <4 RK_PB4 1 &pcfg_pull_none_smt>; 1816 }; 1817 1818 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 1819 rockchip,pins = 1820 <4 RK_PB5 1 &pcfg_pull_none_smt>; 1821 }; 1822 1823 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 1824 rockchip,pins = 1825 <4 RK_PB6 1 &pcfg_pull_none_smt>; 1826 }; 1827 1828 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 1829 rockchip,pins = 1830 <4 RK_PB7 1 &pcfg_pull_none>; 1831 }; 1832 1833 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 1834 rockchip,pins = 1835 <4 RK_PC0 1 &pcfg_pull_none>; 1836 }; 1837 }; 1838 1839 i2s_8ch_0 { 1840 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 1841 rockchip,pins = 1842 <2 RK_PA4 1 &pcfg_pull_none_smt>; 1843 }; 1844 1845 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 1846 rockchip,pins = 1847 <2 RK_PA5 1 &pcfg_pull_none_smt>; 1848 }; 1849 1850 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 1851 rockchip,pins = 1852 <2 RK_PA6 1 &pcfg_pull_none_smt>; 1853 }; 1854 1855 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 1856 rockchip,pins = 1857 <2 RK_PA7 1 &pcfg_pull_none_smt>; 1858 }; 1859 1860 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 1861 rockchip,pins = 1862 <2 RK_PB0 1 &pcfg_pull_none_smt>; 1863 }; 1864 1865 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 1866 rockchip,pins = 1867 <2 RK_PB1 1 &pcfg_pull_none>; 1868 }; 1869 1870 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 1871 rockchip,pins = 1872 <2 RK_PB2 1 &pcfg_pull_none>; 1873 }; 1874 1875 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 1876 rockchip,pins = 1877 <2 RK_PB3 1 &pcfg_pull_none>; 1878 }; 1879 1880 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 1881 rockchip,pins = 1882 <2 RK_PB4 1 &pcfg_pull_none>; 1883 }; 1884 1885 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 1886 rockchip,pins = 1887 <2 RK_PB5 1 &pcfg_pull_none>; 1888 }; 1889 1890 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 1891 rockchip,pins = 1892 <2 RK_PB6 1 &pcfg_pull_none>; 1893 }; 1894 1895 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 1896 rockchip,pins = 1897 <2 RK_PB7 1 &pcfg_pull_none>; 1898 }; 1899 1900 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 1901 rockchip,pins = 1902 <2 RK_PC0 1 &pcfg_pull_none>; 1903 }; 1904 }; 1905 1906 i2s_8ch_1_m0 { 1907 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 1908 rockchip,pins = 1909 <1 RK_PA2 2 &pcfg_pull_none_smt>; 1910 }; 1911 1912 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 1913 rockchip,pins = 1914 <1 RK_PA3 2 &pcfg_pull_none_smt>; 1915 }; 1916 1917 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 1918 rockchip,pins = 1919 <1 RK_PA4 2 &pcfg_pull_none_smt>; 1920 }; 1921 1922 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 1923 rockchip,pins = 1924 <1 RK_PA5 2 &pcfg_pull_none_smt>; 1925 }; 1926 1927 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 1928 rockchip,pins = 1929 <1 RK_PA6 2 &pcfg_pull_none_smt>; 1930 }; 1931 1932 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1933 rockchip,pins = 1934 <1 RK_PA7 2 &pcfg_pull_none>; 1935 }; 1936 1937 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1938 rockchip,pins = 1939 <1 RK_PB0 2 &pcfg_pull_none>; 1940 }; 1941 1942 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1943 rockchip,pins = 1944 <1 RK_PB1 2 &pcfg_pull_none>; 1945 }; 1946 1947 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1948 rockchip,pins = 1949 <1 RK_PB2 2 &pcfg_pull_none>; 1950 }; 1951 1952 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1953 rockchip,pins = 1954 <1 RK_PB3 2 &pcfg_pull_none>; 1955 }; 1956 }; 1957 1958 i2s_8ch_1_m1 { 1959 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1960 rockchip,pins = 1961 <1 RK_PB4 2 &pcfg_pull_none_smt>; 1962 }; 1963 1964 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1965 rockchip,pins = 1966 <1 RK_PB5 2 &pcfg_pull_none_smt>; 1967 }; 1968 1969 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1970 rockchip,pins = 1971 <1 RK_PB6 2 &pcfg_pull_none_smt>; 1972 }; 1973 1974 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1975 rockchip,pins = 1976 <1 RK_PB7 2 &pcfg_pull_none_smt>; 1977 }; 1978 1979 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1980 rockchip,pins = 1981 <1 RK_PC0 2 &pcfg_pull_none_smt>; 1982 }; 1983 1984 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1985 rockchip,pins = 1986 <1 RK_PC1 2 &pcfg_pull_none>; 1987 }; 1988 1989 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1990 rockchip,pins = 1991 <1 RK_PC2 2 &pcfg_pull_none>; 1992 }; 1993 1994 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1995 rockchip,pins = 1996 <1 RK_PC3 2 &pcfg_pull_none>; 1997 }; 1998 1999 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 2000 rockchip,pins = 2001 <1 RK_PC4 2 &pcfg_pull_none>; 2002 }; 2003 2004 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 2005 rockchip,pins = 2006 <1 RK_PC5 2 &pcfg_pull_none>; 2007 }; 2008 }; 2009 2010 lcdc { 2011 lcdc_ctl: lcdc-ctl { 2012 rockchip,pins = 2013 /* dclk */ 2014 <1 RK_PA0 1 &pcfg_pull_none_4ma>, 2015 /* hsync */ 2016 <1 RK_PA1 1 &pcfg_pull_none_4ma>, 2017 /* vsync */ 2018 <1 RK_PA2 1 &pcfg_pull_none_4ma>, 2019 /* den */ 2020 <1 RK_PA3 1 &pcfg_pull_none_4ma>, 2021 /* d0 */ 2022 <1 RK_PA4 1 &pcfg_pull_none_4ma>, 2023 /* d1 */ 2024 <1 RK_PA5 1 &pcfg_pull_none_4ma>, 2025 /* d2 */ 2026 <1 RK_PA6 1 &pcfg_pull_none_4ma>, 2027 /* d3 */ 2028 <1 RK_PA7 1 &pcfg_pull_none_4ma>, 2029 /* d4 */ 2030 <1 RK_PB0 1 &pcfg_pull_none_4ma>, 2031 /* d5 */ 2032 <1 RK_PB1 1 &pcfg_pull_none_4ma>, 2033 /* d6 */ 2034 <1 RK_PB2 1 &pcfg_pull_none_4ma>, 2035 /* d7 */ 2036 <1 RK_PB3 1 &pcfg_pull_none_4ma>, 2037 /* d8 */ 2038 <1 RK_PB4 1 &pcfg_pull_none_4ma>, 2039 /* d9 */ 2040 <1 RK_PB5 1 &pcfg_pull_none_4ma>, 2041 /* d10 */ 2042 <1 RK_PB6 1 &pcfg_pull_none_4ma>, 2043 /* d11 */ 2044 <1 RK_PB7 1 &pcfg_pull_none_4ma>, 2045 /* d12 */ 2046 <1 RK_PC0 1 &pcfg_pull_none_4ma>, 2047 /* d13 */ 2048 <1 RK_PC1 1 &pcfg_pull_none_4ma>, 2049 /* d14 */ 2050 <1 RK_PC2 1 &pcfg_pull_none_4ma>, 2051 /* d15 */ 2052 <1 RK_PC3 1 &pcfg_pull_none_4ma>, 2053 /* d16 */ 2054 <1 RK_PC4 1 &pcfg_pull_none_4ma>, 2055 /* d17 */ 2056 <1 RK_PC5 1 &pcfg_pull_none_4ma>; 2057 }; 2058 2059 lcdc_rgb888_m0: lcdc-rgb888-m0 { 2060 rockchip,pins = 2061 /* d18 */ 2062 <1 RK_PC6 6 &pcfg_pull_none_4ma>, 2063 /* d19 */ 2064 <1 RK_PC7 6 &pcfg_pull_none_4ma>, 2065 /* d20 */ 2066 <2 RK_PB1 3 &pcfg_pull_none_4ma>, 2067 /* d21 */ 2068 <2 RK_PB2 3 &pcfg_pull_none_4ma>, 2069 /* d22 */ 2070 <2 RK_PB7 3 &pcfg_pull_none_4ma>, 2071 /* d23 */ 2072 <2 RK_PC0 3 &pcfg_pull_none_4ma>; 2073 }; 2074 2075 lcdc_rgb888_m1: lcdc-rgb888-m1 { 2076 rockchip,pins = 2077 /* d18 */ 2078 <3 RK_PA6 3 &pcfg_pull_none_4ma>, 2079 /* d19 */ 2080 <3 RK_PA7 3 &pcfg_pull_none_4ma>, 2081 /* d20 */ 2082 <3 RK_PB0 3 &pcfg_pull_none_4ma>, 2083 /* d21 */ 2084 <3 RK_PB1 3 &pcfg_pull_none_4ma>, 2085 /* d22 */ 2086 <3 RK_PB2 4 &pcfg_pull_none_4ma>, 2087 /* d23 */ 2088 <3 RK_PB3 4 &pcfg_pull_none_4ma>; 2089 }; 2090 }; 2091 2092 owire-m0 { 2093 owirem0_pins: owirem0-pins { 2094 rockchip,pins = 2095 /* owire_m0 */ 2096 <0 RK_PB3 3 &pcfg_pull_none>; 2097 }; 2098 }; 2099 2100 owire-m1 { 2101 owirem1_pins: owirem1-pins { 2102 rockchip,pins = 2103 /* owire_m1 */ 2104 <1 RK_PC6 7 &pcfg_pull_none>; 2105 }; 2106 }; 2107 2108 owire-m2 { 2109 owirem2_pins: owirem2-pins { 2110 rockchip,pins = 2111 /* owire_m2 */ 2112 <2 RK_PA2 5 &pcfg_pull_none>; 2113 }; 2114 }; 2115 2116 pdm_m0 { 2117 pdm_m0_clk: pdm-m0-clk { 2118 rockchip,pins = 2119 <1 RK_PA4 3 &pcfg_pull_none>; 2120 }; 2121 2122 pdm_m0_sdi0: pdm-m0-sdi0 { 2123 rockchip,pins = 2124 <1 RK_PB3 3 &pcfg_pull_none>; 2125 }; 2126 2127 pdm_m0_sdi1: pdm-m0-sdi1 { 2128 rockchip,pins = 2129 <1 RK_PB2 3 &pcfg_pull_none>; 2130 }; 2131 2132 pdm_m0_sdi2: pdm-m0-sdi2 { 2133 rockchip,pins = 2134 <1 RK_PB1 3 &pcfg_pull_none>; 2135 }; 2136 2137 pdm_m0_sdi3: pdm-m0-sdi3 { 2138 rockchip,pins = 2139 <1 RK_PB0 3 &pcfg_pull_none>; 2140 }; 2141 }; 2142 2143 pdm_m1 { 2144 pdm_m1_clk: pdm-m1-clk { 2145 rockchip,pins = 2146 <1 RK_PB6 4 &pcfg_pull_none>; 2147 }; 2148 2149 pdm_m1_sdi0: pdm-m1-sdi0 { 2150 rockchip,pins = 2151 <1 RK_PC5 4 &pcfg_pull_none>; 2152 }; 2153 2154 pdm_m1_sdi1: pdm-m1-sdi1 { 2155 rockchip,pins = 2156 <1 RK_PC4 4 &pcfg_pull_none>; 2157 }; 2158 2159 pdm_m1_sdi2: pdm-m1-sdi2 { 2160 rockchip,pins = 2161 <1 RK_PC3 4 &pcfg_pull_none>; 2162 }; 2163 2164 pdm_m1_sdi3: pdm-m1-sdi3 { 2165 rockchip,pins = 2166 <1 RK_PC2 4 &pcfg_pull_none>; 2167 }; 2168 }; 2169 2170 pdm_m2 { 2171 pdm_m2_clkm: pdm-m2-clkm { 2172 rockchip,pins = 2173 <2 RK_PA4 3 &pcfg_pull_none>; 2174 }; 2175 2176 pdm_m2_clk: pdm-m2-clk { 2177 rockchip,pins = 2178 <2 RK_PA6 2 &pcfg_pull_none>; 2179 }; 2180 2181 pdm_m2_sdi0: pdm-m2-sdi0 { 2182 rockchip,pins = 2183 <2 RK_PB5 2 &pcfg_pull_none>; 2184 }; 2185 2186 pdm_m2_sdi1: pdm-m2-sdi1 { 2187 rockchip,pins = 2188 <2 RK_PB6 2 &pcfg_pull_none>; 2189 }; 2190 2191 pdm_m2_sdi2: pdm-m2-sdi2 { 2192 rockchip,pins = 2193 <2 RK_PB7 2 &pcfg_pull_none>; 2194 }; 2195 2196 pdm_m2_sdi3: pdm-m2-sdi3 { 2197 rockchip,pins = 2198 <2 RK_PC0 2 &pcfg_pull_none>; 2199 }; 2200 }; 2201 2202 pwm0 { 2203 pwm0_pin: pwm0-pin { 2204 rockchip,pins = 2205 <0 RK_PB5 1 &pcfg_pull_none>; 2206 }; 2207 2208 pwm0_pin_pull_down: pwm0-pin-pull-down { 2209 rockchip,pins = 2210 <0 RK_PB5 1 &pcfg_pull_down>; 2211 }; 2212 }; 2213 2214 pwm1 { 2215 pwm1_pin: pwm1-pin { 2216 rockchip,pins = 2217 <0 RK_PB6 1 &pcfg_pull_none>; 2218 }; 2219 2220 pwm1_pin_pull_down: pwm1-pin-pull-down { 2221 rockchip,pins = 2222 <0 RK_PB6 1 &pcfg_pull_down>; 2223 }; 2224 }; 2225 2226 pwm2 { 2227 pwm2_pin: pwm2-pin { 2228 rockchip,pins = 2229 <0 RK_PB7 1 &pcfg_pull_none>; 2230 }; 2231 2232 pwm2_pin_pull_down: pwm2-pin-pull-down { 2233 rockchip,pins = 2234 <0 RK_PB7 1 &pcfg_pull_down>; 2235 }; 2236 }; 2237 2238 pwm3 { 2239 pwm3_pin: pwm3-pin { 2240 rockchip,pins = 2241 <0 RK_PC0 1 &pcfg_pull_none>; 2242 }; 2243 2244 pwm3_pin_pull_down: pwm3-pin-pull-down { 2245 rockchip,pins = 2246 <0 RK_PC0 1 &pcfg_pull_down>; 2247 }; 2248 }; 2249 2250 pwm4 { 2251 pwm4_pin: pwm4-pin { 2252 rockchip,pins = 2253 <0 RK_PA1 2 &pcfg_pull_none>; 2254 }; 2255 2256 pwm4_pin_pull_down: pwm4-pin-pull-down { 2257 rockchip,pins = 2258 <0 RK_PA1 2 &pcfg_pull_down>; 2259 }; 2260 }; 2261 2262 pwm5 { 2263 pwm5_pin: pwm5-pin { 2264 rockchip,pins = 2265 <0 RK_PC1 2 &pcfg_pull_none>; 2266 }; 2267 2268 pwm5_pin_pull_down: pwm5-pin-pull-down { 2269 rockchip,pins = 2270 <0 RK_PC1 2 &pcfg_pull_down>; 2271 }; 2272 }; 2273 2274 pwm6 { 2275 pwm6_pin: pwm6-pin { 2276 rockchip,pins = 2277 <0 RK_PC2 2 &pcfg_pull_none>; 2278 }; 2279 2280 pwm6_pin_pull_down: pwm6-pin-pull-down { 2281 rockchip,pins = 2282 <0 RK_PC2 2 &pcfg_pull_down>; 2283 }; 2284 }; 2285 2286 pwm7 { 2287 pwm7_pin: pwm7-pin { 2288 rockchip,pins = 2289 <2 RK_PB0 2 &pcfg_pull_none>; 2290 }; 2291 2292 pwm7_pin_pull_down: pwm7-pin-pull-down { 2293 rockchip,pins = 2294 <2 RK_PB0 2 &pcfg_pull_down>; 2295 }; 2296 }; 2297 2298 pwm8 { 2299 pwm8_pin: pwm8-pin { 2300 rockchip,pins = 2301 <2 RK_PB2 2 &pcfg_pull_none>; 2302 }; 2303 2304 pwm8_pin_pull_down: pwm8-pin-pull-down { 2305 rockchip,pins = 2306 <2 RK_PB2 2 &pcfg_pull_down>; 2307 }; 2308 }; 2309 2310 pwm9 { 2311 pwm9_pin: pwm9-pin { 2312 rockchip,pins = 2313 <2 RK_PB3 2 &pcfg_pull_none>; 2314 }; 2315 2316 pwm9_pin_pull_down: pwm9-pin-pull-down { 2317 rockchip,pins = 2318 <2 RK_PB3 2 &pcfg_pull_down>; 2319 }; 2320 }; 2321 2322 pwm10 { 2323 pwm10_pin: pwm10-pin { 2324 rockchip,pins = 2325 <2 RK_PB4 2 &pcfg_pull_none>; 2326 }; 2327 2328 pwm10_pin_pull_down: pwm10-pin-pull-down { 2329 rockchip,pins = 2330 <2 RK_PB4 2 &pcfg_pull_down>; 2331 }; 2332 }; 2333 2334 pwm11 { 2335 pwm11_pin: pwm11-pin { 2336 rockchip,pins = 2337 <2 RK_PC0 4 &pcfg_pull_none>; 2338 }; 2339 2340 pwm11_pin_pull_down: pwm11-pin-pull-down { 2341 rockchip,pins = 2342 <2 RK_PC0 4 &pcfg_pull_down>; 2343 }; 2344 }; 2345 2346 rtc { 2347 rtc_32k: rtc-32k { 2348 rockchip,pins = 2349 <0 RK_PC3 1 &pcfg_pull_none>; 2350 }; 2351 }; 2352 2353 sdmmc { 2354 sdmmc_clk: sdmmc-clk { 2355 rockchip,pins = 2356 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 2357 }; 2358 2359 sdmmc_cmd: sdmmc-cmd { 2360 rockchip,pins = 2361 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 2362 }; 2363 2364 sdmmc_det: sdmmc-det { 2365 rockchip,pins = 2366 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 2367 }; 2368 2369 sdmmc_pwren: sdmmc-pwren { 2370 rockchip,pins = 2371 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 2372 }; 2373 2374 sdmmc_bus1: sdmmc-bus1 { 2375 rockchip,pins = 2376 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 2377 }; 2378 2379 sdmmc_bus4: sdmmc-bus4 { 2380 rockchip,pins = 2381 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 2382 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 2383 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 2384 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 2385 }; 2386 2387 sdmmc_gpio: sdmmc-gpio { 2388 rockchip,pins = 2389 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2390 <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2391 <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2392 <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2393 <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2394 <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2395 <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 2396 }; 2397 }; 2398 2399 sdio { 2400 sdio_clk: sdio-clk { 2401 rockchip,pins = 2402 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 2403 }; 2404 2405 sdio_cmd: sdio-cmd { 2406 rockchip,pins = 2407 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 2408 }; 2409 2410 sdio_pwren: sdio-pwren { 2411 rockchip,pins = 2412 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 2413 }; 2414 2415 sdio_wrpt: sdio-wrpt { 2416 rockchip,pins = 2417 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 2418 }; 2419 2420 sdio_intn: sdio-intn { 2421 rockchip,pins = 2422 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 2423 }; 2424 2425 sdio_bus1: sdio-bus1 { 2426 rockchip,pins = 2427 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 2428 }; 2429 2430 sdio_bus4: sdio-bus4 { 2431 rockchip,pins = 2432 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 2433 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 2434 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 2435 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 2436 }; 2437 2438 sdio_gpio: sdio-gpio { 2439 rockchip,pins = 2440 <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2441 <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2442 <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2443 <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2444 <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 2445 <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 2446 }; 2447 }; 2448 2449 spdif_in { 2450 spdif_in: spdif-in { 2451 rockchip,pins = 2452 <0 RK_PC2 1 &pcfg_pull_none>; 2453 }; 2454 }; 2455 2456 spdif_out { 2457 spdif_out: spdif-out { 2458 rockchip,pins = 2459 <0 RK_PC1 1 &pcfg_pull_none>; 2460 }; 2461 }; 2462 2463 spi0 { 2464 spi0_clk: spi0-clk { 2465 rockchip,pins = 2466 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 2467 }; 2468 2469 spi0_csn0: spi0-csn0 { 2470 rockchip,pins = 2471 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 2472 }; 2473 2474 spi0_miso: spi0-miso { 2475 rockchip,pins = 2476 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 2477 }; 2478 2479 spi0_mosi: spi0-mosi { 2480 rockchip,pins = 2481 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 2482 }; 2483 2484 spi0_clk_hs: spi0-clk-hs { 2485 rockchip,pins = 2486 <2 RK_PA2 2 &pcfg_pull_up_8ma>; 2487 }; 2488 2489 spi0_miso_hs: spi0-miso-hs { 2490 rockchip,pins = 2491 <2 RK_PA0 2 &pcfg_pull_up_8ma>; 2492 }; 2493 2494 spi0_mosi_hs: spi0-mosi-hs { 2495 rockchip,pins = 2496 <2 RK_PA1 2 &pcfg_pull_up_8ma>; 2497 }; 2498 2499 }; 2500 2501 spi1 { 2502 spi1_clk: spi1-clk { 2503 rockchip,pins = 2504 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 2505 }; 2506 2507 spi1_csn0: spi1-csn0 { 2508 rockchip,pins = 2509 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 2510 }; 2511 2512 spi1_miso: spi1-miso { 2513 rockchip,pins = 2514 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 2515 }; 2516 2517 spi1_mosi: spi1-mosi { 2518 rockchip,pins = 2519 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 2520 }; 2521 2522 spi1_clk_hs: spi1-clk-hs { 2523 rockchip,pins = 2524 <3 RK_PB3 3 &pcfg_pull_up_8ma>; 2525 }; 2526 2527 spi1_miso_hs: spi1-miso-hs { 2528 rockchip,pins = 2529 <3 RK_PB2 3 &pcfg_pull_up_8ma>; 2530 }; 2531 2532 spi1_mosi_hs: spi1-mosi-hs { 2533 rockchip,pins = 2534 <3 RK_PB4 3 &pcfg_pull_up_8ma>; 2535 }; 2536 }; 2537 2538 spi1-m1 { 2539 spi1m1_miso: spi1m1-miso { 2540 rockchip,pins = 2541 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 2542 }; 2543 2544 spi1m1_mosi: spi1m1-mosi { 2545 rockchip,pins = 2546 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 2547 }; 2548 2549 spi1m1_clk: spi1m1-clk { 2550 rockchip,pins = 2551 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 2552 }; 2553 2554 spi1m1_csn0: spi1m1-csn0 { 2555 rockchip,pins = 2556 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 2557 }; 2558 2559 spi1m1_miso_hs: spi1m1-miso-hs { 2560 rockchip,pins = 2561 <2 RK_PA4 2 &pcfg_pull_up_8ma>; 2562 }; 2563 2564 spi1m1_mosi_hs: spi1m1-mosi-hs { 2565 rockchip,pins = 2566 <2 RK_PA5 2 &pcfg_pull_up_8ma>; 2567 }; 2568 2569 spi1m1_clk_hs: spi1m1-clk-hs { 2570 rockchip,pins = 2571 <2 RK_PA7 2 &pcfg_pull_up_8ma>; 2572 }; 2573 2574 spi1m1_csn0_hs: spi1m1-csn0-hs { 2575 rockchip,pins = 2576 <2 RK_PB1 2 &pcfg_pull_up_8ma>; 2577 }; 2578 }; 2579 2580 spi2 { 2581 spi2_clk: spi2-clk { 2582 rockchip,pins = 2583 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 2584 }; 2585 2586 spi2_csn0: spi2-csn0 { 2587 rockchip,pins = 2588 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 2589 }; 2590 2591 spi2_miso: spi2-miso { 2592 rockchip,pins = 2593 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 2594 }; 2595 2596 spi2_mosi: spi2-mosi { 2597 rockchip,pins = 2598 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 2599 }; 2600 2601 spi2_clk_hs: spi2-clk-hs { 2602 rockchip,pins = 2603 <1 RK_PD0 3 &pcfg_pull_up_8ma>; 2604 }; 2605 2606 spi2_miso_hs: spi2-miso-hs { 2607 rockchip,pins = 2608 <1 RK_PC6 3 &pcfg_pull_up_8ma>; 2609 }; 2610 2611 spi2_mosi_hs: spi2-mosi-hs { 2612 rockchip,pins = 2613 <1 RK_PC7 3 &pcfg_pull_up_8ma>; 2614 }; 2615 }; 2616 2617 tsadc { 2618 tsadc_otp_pin: tsadc-otp-pin { 2619 rockchip,pins = 2620 <0 RK_PB2 0 &pcfg_pull_none>; 2621 }; 2622 2623 tsadc_otp_out: tsadc-otp-out { 2624 rockchip,pins = 2625 <0 RK_PB2 1 &pcfg_pull_none>; 2626 }; 2627 }; 2628 2629 uart0 { 2630 uart0_xfer: uart0-xfer { 2631 rockchip,pins = 2632 <2 RK_PA1 1 &pcfg_pull_up>, 2633 <2 RK_PA0 1 &pcfg_pull_up>; 2634 }; 2635 2636 uart0_cts: uart0-cts { 2637 rockchip,pins = 2638 <2 RK_PA2 1 &pcfg_pull_none>; 2639 }; 2640 2641 uart0_rts: uart0-rts { 2642 rockchip,pins = 2643 <2 RK_PA3 1 &pcfg_pull_none>; 2644 }; 2645 2646 uart0_rts_pin: uart0-rts-pin { 2647 rockchip,pins = 2648 <2 RK_PA3 0 &pcfg_pull_none>; 2649 }; 2650 }; 2651 2652 uart1 { 2653 uart1_xfer: uart1-xfer { 2654 rockchip,pins = 2655 <1 RK_PD1 1 &pcfg_pull_up>, 2656 <1 RK_PD0 1 &pcfg_pull_up>; 2657 }; 2658 2659 uart1_cts: uart1-cts { 2660 rockchip,pins = 2661 <1 RK_PC6 1 &pcfg_pull_none>; 2662 }; 2663 2664 uart1_rts: uart1-rts { 2665 rockchip,pins = 2666 <1 RK_PC7 1 &pcfg_pull_none>; 2667 }; 2668 }; 2669 2670 uart2-m0 { 2671 uart2m0_xfer: uart2m0-xfer { 2672 rockchip,pins = 2673 <1 RK_PC7 2 &pcfg_pull_up>, 2674 <1 RK_PC6 2 &pcfg_pull_up>; 2675 }; 2676 }; 2677 2678 uart2-m1 { 2679 uart2m1_xfer: uart2m1-xfer { 2680 rockchip,pins = 2681 <4 RK_PD3 2 &pcfg_pull_up>, 2682 <4 RK_PD2 2 &pcfg_pull_up>; 2683 }; 2684 }; 2685 2686 uart3 { 2687 uart3_xfer: uart3-xfer { 2688 rockchip,pins = 2689 <3 RK_PB5 4 &pcfg_pull_up>, 2690 <3 RK_PB4 4 &pcfg_pull_up>; 2691 }; 2692 }; 2693 2694 uart3-m1 { 2695 uart3m1_xfer: uart3m1-xfer { 2696 rockchip,pins = 2697 <0 RK_PC2 3 &pcfg_pull_up>, 2698 <0 RK_PC1 3 &pcfg_pull_up>; 2699 }; 2700 }; 2701 2702 uart4 { 2703 uart4_xfer: uart4-xfer { 2704 rockchip,pins = 2705 <4 RK_PB1 1 &pcfg_pull_up>, 2706 <4 RK_PB0 1 &pcfg_pull_up>; 2707 }; 2708 2709 uart4_cts: uart4-cts { 2710 rockchip,pins = 2711 <4 RK_PA6 1 &pcfg_pull_none>; 2712 }; 2713 2714 uart4_rts: uart4-rts { 2715 rockchip,pins = 2716 <4 RK_PA7 1 &pcfg_pull_none>; 2717 }; 2718 2719 uart4_rts_pin: uart4-rts-pin { 2720 rockchip,pins = 2721 <4 RK_PA7 0 &pcfg_pull_none>; 2722 }; 2723 }; 2724 }; 2725}; 2726#include "rk3308bs-pinctrl.dtsi" 2727
