1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 dmc: dmc { 73 compatible = "rockchip,px30-dmc", "syscon"; 74 reg = <0x0 0xff2a0000 0x0 0x1000>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vopb_out>, <&vopl_out>; 80 status = "disabled"; 81 }; 82 83 firmware { 84 optee { 85 compatible = "linaro,optee-tz"; 86 method = "smc"; 87 }; 88 }; 89 90 gmac_clkin: external-gmac-clock { 91 compatible = "fixed-clock"; 92 clock-frequency = <50000000>; 93 clock-output-names = "gmac_clkin"; 94 #clock-cells = <0>; 95 }; 96 97 psci: psci { 98 compatible = "arm,psci-1.0"; 99 method = "smc"; 100 }; 101 102 timer { 103 compatible = "arm,armv8-timer"; 104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 108 }; 109 110 xin24m: xin24m { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <24000000>; 114 clock-output-names = "xin24m"; 115 }; 116 117 pmu: power-management@ff000000 { 118 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 119 reg = <0x0 0xff000000 0x0 0x1000>; 120 121 power: power-controller { 122 compatible = "rockchip,px30-power-controller"; 123 #power-domain-cells = <1>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* These power domains are grouped by VD_LOGIC */ 129 pd_usb@PX30_PD_USB { 130 reg = <PX30_PD_USB>; 131 clocks = <&cru HCLK_HOST>, 132 <&cru HCLK_OTG>, 133 <&cru SCLK_OTG_ADP>; 134 }; 135 pd_sdcard@PX30_PD_SDCARD { 136 reg = <PX30_PD_SDCARD>; 137 clocks = <&cru HCLK_SDMMC>, 138 <&cru SCLK_SDMMC>; 139 }; 140 pd_gmac@PX30_PD_GMAC { 141 reg = <PX30_PD_GMAC>; 142 clocks = <&cru ACLK_GMAC>, 143 <&cru PCLK_GMAC>, 144 <&cru SCLK_MAC_REF>, 145 <&cru SCLK_GMAC_RX_TX>; 146 }; 147 pd_mmc_nand@PX30_PD_MMC_NAND { 148 reg = <PX30_PD_MMC_NAND>; 149 clocks = <&cru HCLK_NANDC>, 150 <&cru HCLK_EMMC>, 151 <&cru HCLK_SDIO>, 152 <&cru HCLK_SFC>, 153 <&cru SCLK_EMMC>, 154 <&cru SCLK_NANDC>, 155 <&cru SCLK_SDIO>, 156 <&cru SCLK_SFC>; 157 }; 158 pd_vpu@PX30_PD_VPU { 159 reg = <PX30_PD_VPU>; 160 clocks = <&cru ACLK_VPU>, 161 <&cru HCLK_VPU>, 162 <&cru SCLK_CORE_VPU>; 163 }; 164 pd_vo@PX30_PD_VO { 165 reg = <PX30_PD_VO>; 166 clocks = <&cru ACLK_RGA>, 167 <&cru ACLK_VOPB>, 168 <&cru ACLK_VOPL>, 169 <&cru DCLK_VOPB>, 170 <&cru DCLK_VOPL>, 171 <&cru HCLK_RGA>, 172 <&cru HCLK_VOPB>, 173 <&cru HCLK_VOPL>, 174 <&cru PCLK_MIPI_DSI>, 175 <&cru SCLK_RGA_CORE>, 176 <&cru SCLK_VOPB_PWM>; 177 }; 178 pd_vi@PX30_PD_VI { 179 reg = <PX30_PD_VI>; 180 clocks = <&cru ACLK_CIF>, 181 <&cru ACLK_ISP>, 182 <&cru HCLK_CIF>, 183 <&cru HCLK_ISP>, 184 <&cru SCLK_ISP>; 185 }; 186 pd_gpu@PX30_PD_GPU { 187 reg = <PX30_PD_GPU>; 188 clocks = <&cru ACLK_GPU>; 189 }; 190 }; 191 }; 192 193 pmugrf: syscon@ff010000 { 194 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 195 reg = <0x0 0xff010000 0x0 0x1000>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 199 pmu_io_domains: io-domains { 200 compatible = "rockchip,px30-pmu-io-voltage-domain"; 201 status = "disabled"; 202 }; 203 204 reboot-mode { 205 compatible = "syscon-reboot-mode"; 206 offset = <0x200>; 207 mode-bootloader = <BOOT_BL_DOWNLOAD>; 208 mode-charge = <BOOT_CHARGING>; 209 mode-fastboot = <BOOT_FASTBOOT>; 210 mode-loader = <BOOT_BL_DOWNLOAD>; 211 mode-normal = <BOOT_NORMAL>; 212 mode-recovery = <BOOT_RECOVERY>; 213 mode-ums = <BOOT_UMS>; 214 }; 215 216 pmu_pvtm: pmu-pvtm { 217 compatible = "rockchip,px30-pmu-pvtm"; 218 clocks = <&pmucru SCLK_PVTM_PMU>; 219 clock-names = "pmu"; 220 status = "disabled"; 221 }; 222 }; 223 224 uart0: serial@ff030000 { 225 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 226 reg = <0x0 0xff030000 0x0 0x100>; 227 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 229 clock-names = "baudclk", "apb_pclk"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 dmas = <&dmac 0>, <&dmac 1>; 233 #dma-cells = <2>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 236 status = "disabled"; 237 }; 238 239 i2s0_8ch: i2s@ff060000 { 240 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 241 reg = <0x0 0xff060000 0x0 0x1000>; 242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 244 clock-names = "i2s_clk", "i2s_hclk"; 245 dmas = <&dmac 16>, <&dmac 17>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 i2s1_2ch: i2s@ff070000 { 251 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 252 reg = <0x0 0xff070000 0x0 0x1000>; 253 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 255 clock-names = "i2s_clk", "i2s_hclk"; 256 dmas = <&dmac 18>, <&dmac 19>; 257 dma-names = "tx", "rx"; 258 status = "disabled"; 259 }; 260 261 i2s2_2ch: i2s@ff080000 { 262 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 263 reg = <0x0 0xff080000 0x0 0x1000>; 264 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 266 clock-names = "i2s_clk", "i2s_hclk"; 267 dmas = <&dmac 20>, <&dmac 21>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 pdm: pdm@ff0a0000 { 273 compatible = "rockchip,pdm"; 274 reg = <0x0 0xff0a0000 0x0 0x1000>; 275 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 276 clock-names = "pdm_clk", "pdm_hclk"; 277 dmas = <&dmac 24>; 278 dma-names = "rx"; 279 status = "disabled"; 280 }; 281 282 crypto: crypto@ff0b0000 { 283 compatible = "rockchip,px30-crypto"; 284 reg = <0x0 0xff0b0000 0x0 0x4000>; 285 clock-names = "sclk_crypto", "apkclk_crypto"; 286 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 287 clock-frequency = <200000000>, <300000000>; 288 status = "disabled"; 289 }; 290 291 gic: interrupt-controller@ff131000 { 292 compatible = "arm,gic-400"; 293 #interrupt-cells = <3>; 294 #address-cells = <0>; 295 interrupt-controller; 296 reg = <0x0 0xff131000 0 0x1000>, 297 <0x0 0xff132000 0 0x2000>, 298 <0x0 0xff134000 0 0x2000>, 299 <0x0 0xff136000 0 0x2000>; 300 interrupts = <GIC_PPI 9 301 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 302 }; 303 304 grf: syscon@ff140000 { 305 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 306 reg = <0x0 0xff140000 0x0 0x1000>; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 310 io_domains: io-domains { 311 compatible = "rockchip,px30-io-voltage-domain"; 312 status = "disabled"; 313 }; 314 315 lvds: lvds { 316 compatible = "rockchip,px30-lvds"; 317 phys = <&video_phy>; 318 phy-names = "phy"; 319 status = "disabled"; 320 321 ports { 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 port@0 { 326 reg = <0>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 330 lvds_in_vopb: endpoint@0 { 331 reg = <0>; 332 remote-endpoint = <&vopb_out_lvds>; 333 }; 334 335 lvds_in_vopl: endpoint@1 { 336 reg = <1>; 337 remote-endpoint = <&vopl_out_lvds>; 338 }; 339 }; 340 }; 341 }; 342 343 rgb: rgb { 344 compatible = "rockchip,px30-rgb"; 345 pinctrl-names = "default", "sleep"; 346 pinctrl-0 = <&lcdc_m0_rgb_pins>; 347 pinctrl-1 = <&lcdc_m0_sleep_pins>; 348 status = "disabled"; 349 350 ports { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 354 port@0 { 355 reg = <0>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 359 rgb_in_vopb: endpoint@0 { 360 reg = <0>; 361 remote-endpoint = <&vopb_out_rgb>; 362 }; 363 364 rgb_in_vopl: endpoint@1 { 365 reg = <1>; 366 remote-endpoint = <&vopl_out_rgb>; 367 }; 368 }; 369 }; 370 }; 371 }; 372 373 core_grf: syscon@ff148000 { 374 compatible = "syscon", "simple-mfd"; 375 reg = <0x0 0xff148000 0x0 0x1000>; 376 #address-cells = <1>; 377 #size-cells = <1>; 378 379 pvtm: pvtm { 380 compatible = "rockchip,px30-pvtm"; 381 clocks = <&cru SCLK_PVTM>; 382 clock-names = "core"; 383 status = "disabled"; 384 }; 385 }; 386 387 uart1: serial@ff158000 { 388 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 389 reg = <0x0 0xff158000 0x0 0x100>; 390 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 392 clock-names = "sclk_uart", "pclk_uart"; 393 reg-shift = <2>; 394 reg-io-width = <4>; 395 dmas = <&dmac 2>, <&dmac 3>; 396 #dma-cells = <2>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 399 status = "disabled"; 400 }; 401 402 uart2: serial@ff160000 { 403 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 404 reg = <0x0 0xff160000 0x0 0x100>; 405 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 407 clock-names = "baudclk", "apb_pclk"; 408 reg-shift = <2>; 409 reg-io-width = <4>; 410 dmas = <&dmac 4>, <&dmac 5>; 411 #dma-cells = <2>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&uart2m0_xfer>; 414 status = "disabled"; 415 }; 416 417 uart3: serial@ff168000 { 418 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 419 reg = <0x0 0xff168000 0x0 0x100>; 420 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 422 clock-names = "baudclk", "apb_pclk"; 423 reg-shift = <2>; 424 reg-io-width = <4>; 425 dmas = <&dmac 6>, <&dmac 7>; 426 #dma-cells = <2>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 429 status = "disabled"; 430 }; 431 432 uart4: serial@ff170000 { 433 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 434 reg = <0x0 0xff170000 0x0 0x100>; 435 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 437 clock-names = "baudclk", "apb_pclk"; 438 reg-shift = <2>; 439 reg-io-width = <4>; 440 dmas = <&dmac 8>, <&dmac 9>; 441 #dma-cells = <2>; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 444 status = "disabled"; 445 }; 446 447 uart5: serial@ff178000 { 448 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 449 reg = <0x0 0xff178000 0x0 0x100>; 450 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 452 clock-names = "baudclk", "apb_pclk"; 453 reg-shift = <2>; 454 reg-io-width = <4>; 455 dmas = <&dmac 10>, <&dmac 11>; 456 #dma-cells = <2>; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 459 status = "disabled"; 460 }; 461 462 i2c0: i2c@ff180000 { 463 compatible = "rockchip,rk3399-i2c"; 464 reg = <0x0 0xff180000 0x0 0x1000>; 465 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 466 clock-names = "i2c", "pclk"; 467 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&i2c0_xfer>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 i2c1: i2c@ff190000 { 476 compatible = "rockchip,rk3399-i2c"; 477 reg = <0x0 0xff190000 0x0 0x1000>; 478 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 479 clock-names = "i2c", "pclk"; 480 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&i2c1_xfer>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 status = "disabled"; 486 }; 487 488 i2c2: i2c@ff1a0000 { 489 compatible = "rockchip,rk3399-i2c"; 490 reg = <0x0 0xff1a0000 0x0 0x1000>; 491 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 492 clock-names = "i2c", "pclk"; 493 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&i2c2_xfer>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 i2c3: i2c@ff1b0000 { 502 compatible = "rockchip,rk3399-i2c"; 503 reg = <0x0 0xff1b0000 0x0 0x1000>; 504 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 505 clock-names = "i2c", "pclk"; 506 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&i2c3_xfer>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 status = "disabled"; 512 }; 513 514 spi0: spi@ff1d0000 { 515 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 516 reg = <0x0 0xff1d0000 0x0 0x1000>; 517 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 521 clock-names = "spiclk", "apb_pclk"; 522 dmas = <&dmac 12>, <&dmac 13>; 523 #dma-cells = <2>; 524 dma-names = "tx", "rx"; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 527 status = "disabled"; 528 }; 529 530 spi1: spi@ff1d8000 { 531 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 532 reg = <0x0 0xff1d8000 0x0 0x1000>; 533 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 537 clock-names = "spiclk", "apb_pclk"; 538 dmas = <&dmac 14>, <&dmac 15>; 539 #dma-cells = <2>; 540 dma-names = "tx", "rx"; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 543 status = "disabled"; 544 }; 545 546 wdt: watchdog@ff1e0000 { 547 compatible = "snps,dw-wdt"; 548 reg = <0x0 0xff1e0000 0x0 0x100>; 549 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 550 status = "disabled"; 551 }; 552 553 pwm0: pwm@ff200000 { 554 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 555 reg = <0x0 0xff200000 0x0 0x10>; 556 #pwm-cells = <3>; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pwm0_pin>; 559 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 560 clock-names = "pwm", "pclk"; 561 status = "disabled"; 562 }; 563 564 pwm1: pwm@ff200010 { 565 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 566 reg = <0x0 0xff200010 0x0 0x10>; 567 #pwm-cells = <3>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pwm1_pin>; 570 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 571 clock-names = "pwm", "pclk"; 572 status = "disabled"; 573 }; 574 575 pwm2: pwm@ff200020 { 576 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 577 reg = <0x0 0xff200020 0x0 0x10>; 578 #pwm-cells = <3>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pwm2_pin>; 581 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 582 clock-names = "pwm", "pclk"; 583 status = "disabled"; 584 }; 585 586 pwm3: pwm@ff200030 { 587 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 588 reg = <0x0 0xff200030 0x0 0x10>; 589 #pwm-cells = <3>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&pwm3_pin>; 592 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 593 clock-names = "pwm", "pclk"; 594 status = "disabled"; 595 }; 596 597 pwm4: pwm@ff208000 { 598 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 599 reg = <0x0 0xff208000 0x0 0x10>; 600 #pwm-cells = <3>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pwm4_pin>; 603 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 604 clock-names = "pwm", "pclk"; 605 status = "disabled"; 606 }; 607 608 pwm5: pwm@ff208010 { 609 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 610 reg = <0x0 0xff208010 0x0 0x10>; 611 #pwm-cells = <3>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pwm5_pin>; 614 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 615 clock-names = "pwm", "pclk"; 616 status = "disabled"; 617 }; 618 619 pwm6: pwm@ff208020 { 620 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 621 reg = <0x0 0xff208020 0x0 0x10>; 622 #pwm-cells = <3>; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pwm6_pin>; 625 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 626 clock-names = "pwm", "pclk"; 627 status = "disabled"; 628 }; 629 630 pwm7: pwm@ff208030 { 631 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 632 reg = <0x0 0xff208030 0x0 0x10>; 633 #pwm-cells = <3>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pwm7_pin>; 636 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 637 clock-names = "pwm", "pclk"; 638 status = "disabled"; 639 }; 640 641 amba { 642 compatible = "simple-bus"; 643 #address-cells = <2>; 644 #size-cells = <2>; 645 ranges; 646 647 dmac: dmac@ff240000 { 648 compatible = "arm,pl330", "arm,primecell"; 649 reg = <0x0 0xff240000 0x0 0x4000>; 650 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cru ACLK_DMAC>; 653 clock-names = "apb_pclk"; 654 #dma-cells = <1>; 655 peripherals-req-type-burst; 656 }; 657 }; 658 659 tsadc: tsadc@ff280000 { 660 compatible = "rockchip,px30-tsadc"; 661 reg = <0x0 0xff280000 0x0 0x100>; 662 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 663 rockchip,grf = <&grf>; 664 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 665 clock-names = "tsadc", "apb_pclk"; 666 assigned-clocks = <&cru SCLK_TSADC>; 667 assigned-clock-rates = <50000>; 668 resets = <&cru SRST_TSADC_P>; 669 reset-names = "tsadc-apb"; 670 pinctrl-names = "init", "default", "sleep"; 671 pinctrl-0 = <&tsadc_otp_gpio>; 672 pinctrl-1 = <&tsadc_otp_out>; 673 pinctrl-2 = <&tsadc_otp_gpio>; 674 #thermal-sensor-cells = <1>; 675 rockchip,hw-tshut-temp = <100000>; 676 status = "disabled"; 677 }; 678 679 saradc: saradc@ff288000 { 680 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 681 reg = <0x0 0xff288000 0x0 0x100>; 682 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 683 #io-channel-cells = <1>; 684 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 685 clock-names = "saradc", "apb_pclk"; 686 resets = <&cru SRST_SARADC_P>; 687 reset-names = "saradc-apb"; 688 status = "disabled"; 689 }; 690 691 cru: clock-controller@ff2b0000 { 692 compatible = "rockchip,px30-cru"; 693 reg = <0x0 0xff2b0000 0x0 0x9000>; 694 rockchip,grf = <&grf>; 695 #clock-cells = <1>; 696 #reset-cells = <1>; 697 698 assigned-clocks = 699 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 700 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 701 <&cru ARMCLK>; 702 assigned-clock-rates = 703 <1608000000>, <1416000000>, 704 <1188000000>, <1188000000>, 705 <816000000>; 706 }; 707 708 pmucru: pmu-clock-controller@ff2bc000 { 709 compatible = "rockchip,px30-pmucru"; 710 reg = <0x0 0xff2bc000 0x0 0x1000>; 711 rockchip,grf = <&grf>; 712 #clock-cells = <1>; 713 #reset-cells = <1>; 714 715 assigned-clocks = 716 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 717 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 718 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 719 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 720 assigned-clock-rates = 721 <1200000000>, <100000000>, 722 <26000000>, <300000000>, 723 <300000000>, <150000000>, 724 <150000000>, <75000000>; 725 }; 726 727 usb2phy_grf: syscon@ff2c0000 { 728 compatible = "rockchip,px30-usb2phy-grf", "syscon", 729 "simple-mfd"; 730 reg = <0x0 0xff2c0000 0x0 0x10000>; 731 #address-cells = <1>; 732 #size-cells = <1>; 733 734 u2phy: usb2-phy@100 { 735 compatible = "rockchip,px30-usb2phy", 736 "rockchip,rk3328-usb2phy"; 737 reg = <0x100 0x10>; 738 clocks = <&pmucru SCLK_USBPHY_REF>; 739 clock-names = "phyclk"; 740 #clock-cells = <0>; 741 assigned-clocks = <&cru USB480M>; 742 assigned-clock-parents = <&u2phy>; 743 clock-output-names = "usb480m_phy"; 744 status = "disabled"; 745 746 u2phy_host: host-port { 747 #phy-cells = <0>; 748 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 749 interrupt-names = "linestate"; 750 status = "disabled"; 751 }; 752 753 u2phy_otg: otg-port { 754 #phy-cells = <0>; 755 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 758 interrupt-names = "otg-bvalid", "otg-id", 759 "linestate"; 760 status = "disabled"; 761 }; 762 }; 763 }; 764 765 video_phy: video-phy@ff2e0000 { 766 compatible = "rockchip,px30-video-phy"; 767 reg = <0x0 0xff2e0000 0x0 0x10000>, 768 <0x0 0xff450000 0x0 0x10000>; 769 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, 770 <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 771 clock-names = "ref", "pclk_phy", "pclk_host"; 772 #clock-cells = <0>; 773 resets = <&cru SRST_MIPIDSIPHY_P>; 774 reset-names = "rst"; 775 power-domains = <&power PX30_PD_VO>; 776 #phy-cells = <0>; 777 status = "disabled"; 778 }; 779 780 usb20_otg: usb@ff300000 { 781 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 782 "snps,dwc2"; 783 reg = <0x0 0xff300000 0x0 0x40000>; 784 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&cru HCLK_OTG>; 786 clock-names = "otg"; 787 dr_mode = "otg"; 788 g-np-tx-fifo-size = <16>; 789 g-rx-fifo-size = <275>; 790 g-tx-fifo-size = <256 128 128 64 64 32>; 791 g-use-dma; 792 phys = <&u2phy_otg>; 793 phy-names = "usb2-phy"; 794 status = "disabled"; 795 }; 796 797 usb_host0_ehci: usb@ff340000 { 798 compatible = "generic-ehci"; 799 reg = <0x0 0xff340000 0x0 0x10000>; 800 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 802 <&u2phy>; 803 clock-names = "usbhost", "arbiter", "utmi"; 804 phys = <&u2phy_host>; 805 phy-names = "usb"; 806 status = "disabled"; 807 }; 808 809 usb_host0_ohci: usb@ff350000 { 810 compatible = "generic-ohci"; 811 reg = <0x0 0xff350000 0x0 0x10000>; 812 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 814 <&u2phy>; 815 clock-names = "usbhost", "arbiter", "utmi"; 816 phys = <&u2phy_host>; 817 phy-names = "usb"; 818 }; 819 820 gmac: ethernet@ff360000 { 821 compatible = "rockchip,px30-gmac"; 822 reg = <0x0 0xff360000 0x0 0x10000>; 823 rockchip,grf = <&grf>; 824 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-names = "macirq"; 826 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 827 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 828 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 829 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 830 clock-names = "stmmaceth", "mac_clk_rx", 831 "mac_clk_tx", "clk_mac_ref", 832 "clk_mac_refout", "aclk_mac", 833 "pclk_mac", "clk_mac_speed"; 834 phy-mode = "rmii"; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 837 resets = <&cru SRST_GMAC_A>; 838 reset-names = "stmmaceth"; 839 power-domains = <&power PX30_PD_GMAC>; 840 status = "disabled"; 841 }; 842 843 sdmmc: dwmmc@ff370000 { 844 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 845 reg = <0x0 0xff370000 0x0 0x4000>; 846 max-frequency = <150000000>; 847 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 848 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 849 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 850 fifo-depth = <0x100>; 851 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 852 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 855 status = "disabled"; 856 }; 857 858 sdio: dwmmc@ff380000 { 859 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 860 reg = <0x0 0xff380000 0x0 0x4000>; 861 max-frequency = <150000000>; 862 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 863 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 864 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 865 fifo-depth = <0x100>; 866 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 867 status = "disabled"; 868 }; 869 870 emmc: dwmmc@ff390000 { 871 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 872 reg = <0x0 0xff390000 0x0 0x4000>; 873 max-frequency = <150000000>; 874 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 875 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 876 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 877 fifo-depth = <0x100>; 878 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 879 status = "disabled"; 880 }; 881 882 sfc: sfc@ff3a0000 { 883 compatible = "rockchip,rksfc","rockchip,sfc"; 884 reg = <0x0 0xff3a0000 0x0 0x4000>; 885 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 887 clock-names = "clk_sfc", "hclk_sfc"; 888 status = "disabled"; 889 }; 890 891 nandc0: nandc@ff3b0000 { 892 compatible = "rockchip,rk-nandc"; 893 reg = <0x0 0xff3b0000 0x0 0x4000>; 894 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 895 nandc_id = <0>; 896 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 897 clock-names = "clk_nandc", "hclk_nandc"; 898 status = "disabled"; 899 }; 900 901 gpu: gpu@ff400000 { 902 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 903 reg = <0x0 0xff400000 0x0 0x4000>; 904 905 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "GPU", "MMU", "JOB"; 909 910 clocks = <&cru ACLK_GPU>; 911 clock-names = "clk_mali"; 912 913 status = "disabled"; 914 }; 915 916 hevc: hevc_service@ff440000 { 917 compatible = "rockchip,hevc_sub"; 918 iommu_enabled = <1>; 919 reg = <0x0 0xff440000 0x0 0x400>; 920 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 921 interrupt-names = "irq_dec"; 922 dev_mode = <1>; 923 iommus = <&hevc_mmu>; 924 name = "hevc_service"; 925 allocator = <1>; 926 }; 927 928 vpu: vpu_service@ff442000 { 929 compatible = "rockchip,vpu_sub"; 930 iommu_enabled = <1>; 931 reg = <0x0 0xff442000 0x0 0x800>; 932 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-names = "irq_enc", "irq_dec"; 935 dev_mode = <0>; 936 iommus = <&vpu_mmu>; 937 name = "vpu_service"; 938 allocator = <1>; 939 }; 940 941 vpu_combo: vpu_combo { 942 compatible = "rockchip,vpu_combo"; 943 subcnt = <2>; 944 rockchip,grf = <&grf>; 945 rockchip,sub = <&vpu>, <&hevc>; 946 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 947 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 948 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 949 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 950 <&cru SRST_VPU_CORE>; 951 reset-names = "video_a", "video_h", "niu_a", "niu_h", 952 "video_core"; 953 mode_bit = <15>; 954 mode_ctrl = <0x410>; 955 name = "vpu_combo"; 956 status = "disabled"; 957 }; 958 959 hevc_mmu: iommu@ff440440 { 960 compatible = "rockchip,iommu"; 961 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 962 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 963 interrupt-names = "hevc_mmu"; 964 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 965 clock-names = "aclk", "hclk"; 966 #iommu-cells = <0>; 967 }; 968 969 vpu_mmu: iommu@ff442800 { 970 compatible = "rockchip,iommu"; 971 reg = <0x0 0xff442800 0x0 0x100>; 972 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 973 interrupt-names = "vpu_mmu"; 974 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 975 clock-names = "aclk", "hclk"; 976 #iommu-cells = <0>; 977 }; 978 979 dsi: dsi@ff450000 { 980 compatible = "rockchip,px30-mipi-dsi"; 981 reg = <0x0 0xff450000 0x0 0x10000>; 982 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cru PCLK_MIPI_DSI>, <&video_phy>; 984 clock-names = "pclk", "hs_clk"; 985 resets = <&cru SRST_MIPIDSI_HOST_P>; 986 reset-names = "apb"; 987 phys = <&video_phy>; 988 phy-names = "mipi_dphy"; 989 power-domains = <&power PX30_PD_VO>; 990 rockchip,grf = <&grf>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 status = "disabled"; 994 995 ports { 996 #address-cells = <1>; 997 #size-cells = <0>; 998 999 port@0 { 1000 reg = <0>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 1004 dsi_in_vopl: endpoint@0 { 1005 reg = <0>; 1006 remote-endpoint = <&vopl_out_dsi>; 1007 }; 1008 1009 dsi_in_vopb: endpoint@1 { 1010 reg = <1>; 1011 remote-endpoint = <&vopb_out_dsi>; 1012 }; 1013 }; 1014 }; 1015 }; 1016 1017 vopb: vop@ff460000 { 1018 compatible = "rockchip,px30-vop-big"; 1019 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 1020 reg-names = "regs", "gamma_lut"; 1021 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1023 <&cru HCLK_VOPB>; 1024 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1025 iommus = <&vopb_mmu>; 1026 status = "disabled"; 1027 1028 vopb_out: port { 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 1032 vopb_out_lvds: endpoint@0 { 1033 reg = <0>; 1034 remote-endpoint = <&lvds_in_vopb>; 1035 }; 1036 1037 vopb_out_dsi: endpoint@1 { 1038 reg = <1>; 1039 remote-endpoint = <&dsi_in_vopb>; 1040 }; 1041 1042 vopb_out_rgb: endpoint@2 { 1043 reg = <2>; 1044 remote-endpoint = <&rgb_in_vopb>; 1045 }; 1046 }; 1047 }; 1048 1049 vopb_mmu: iommu@ff460f00 { 1050 compatible = "rockchip,iommu"; 1051 reg = <0x0 0xff460f00 0x0 0x100>; 1052 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1053 interrupt-names = "vopb_mmu"; 1054 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1055 clock-names = "aclk", "hclk"; 1056 #iommu-cells = <0>; 1057 status = "disabled"; 1058 }; 1059 1060 vopl: vop@ff470000 { 1061 compatible = "rockchip,px30-vop-lit"; 1062 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 1063 reg-names = "regs", "gamma_lut"; 1064 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1066 <&cru HCLK_VOPL>; 1067 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1068 iommus = <&vopl_mmu>; 1069 status = "disabled"; 1070 1071 vopl_out: port { 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 1075 vopl_out_lvds: endpoint@0 { 1076 reg = <0>; 1077 remote-endpoint = <&lvds_in_vopl>; 1078 }; 1079 1080 vopl_out_dsi: endpoint@1 { 1081 reg = <1>; 1082 remote-endpoint = <&dsi_in_vopl>; 1083 }; 1084 1085 vopl_out_rgb: endpoint@2 { 1086 reg = <2>; 1087 remote-endpoint = <&rgb_in_vopl>; 1088 }; 1089 }; 1090 }; 1091 1092 vopl_mmu: iommu@ff470f00 { 1093 compatible = "rockchip,iommu"; 1094 reg = <0x0 0xff470f00 0x0 0x100>; 1095 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1096 interrupt-names = "vopl_mmu"; 1097 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1098 clock-names = "aclk", "hclk"; 1099 #iommu-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 rk_rga: rk_rga@ff480000 { 1104 compatible = "rockchip,rga2"; 1105 //dev_mode = <1>; 1106 reg = <0x0 0xff480000 0x0 0x1000>; 1107 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1109 clock-names = "aclk_rga", "hclk_rga"; 1110 dma-coherent; 1111 status = "disabled"; 1112 }; 1113 1114 cif: cif@ff490000 { 1115 compatible = "rockchip,cif"; 1116 reg = <0x0 0xff490000 0x0 0x200>; 1117 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1119 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1120 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1121 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1122 pinctrl-names = "cif_pin_all"; 1123 pinctrl-0 = <&dvp_d2d9_m0>; 1124 status = "disabled"; 1125 }; 1126 1127 vip_mmu: iommu@ff490800{ 1128 compatible = "rockchip,iommu"; 1129 reg = <0x0 0xff490800 0x0 0x100>; 1130 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1131 interrupt-names = "vip_mmu"; 1132 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1133 clock-names = "aclk", "hclk"; 1134 rk_iommu,disable_reset_quirk; 1135 #iommu-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 rk_isp: rk_isp@ff4a0000 { 1140 compatible = "rockchip,px30-isp", "rockchip,isp"; 1141 reg = <0x0 0xff4a0000 0x0 0x4000>; 1142 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1144 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1145 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1146 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1147 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1148 reset-names = "rst_isp", "rst_mipicsiphy"; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&cif_clkout_m0>; 1151 rockchip,isp,mipiphy = <0>; 1152 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1153 rockchip,grf = <&grf>; 1154 rockchip,cru = <&cru>; 1155 rockchip,isp,iommu-enable = <1>; 1156 iommus = <&isp_mmu>; 1157 status = "disabled"; 1158 }; 1159 1160 isp_mmu: iommu@ff4a8000 { 1161 compatible = "rockchip,iommu"; 1162 reg = <0x0 0xff4a8000 0x0 0x100>; 1163 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1164 interrupt-names = "isp_mmu"; 1165 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1166 clock-names = "aclk", "hclk"; 1167 rk_iommu,disable_reset_quirk; 1168 #iommu-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 qos_gmac: qos@ff518000 { 1173 compatible = "syscon"; 1174 reg = <0x0 0xff518000 0x0 0x20>; 1175 }; 1176 1177 qos_gpu: qos@ff520000 { 1178 compatible = "syscon"; 1179 reg = <0x0 0xff520000 0x0 0x20>; 1180 }; 1181 1182 qos_sdmmc: qos@ff52c000 { 1183 compatible = "syscon"; 1184 reg = <0x0 0xff52c000 0x0 0x20>; 1185 }; 1186 1187 qos_emmc: qos@ff538000 { 1188 compatible = "syscon"; 1189 reg = <0x0 0xff538000 0x0 0x20>; 1190 }; 1191 1192 qos_nand: qos@ff538080 { 1193 compatible = "syscon"; 1194 reg = <0x0 0xff538080 0x0 0x20>; 1195 }; 1196 1197 qos_sdio: qos@ff538100 { 1198 compatible = "syscon"; 1199 reg = <0x0 0xff538100 0x0 0x20>; 1200 }; 1201 1202 qos_sfc: qos@ff538180 { 1203 compatible = "syscon"; 1204 reg = <0x0 0xff538180 0x0 0x20>; 1205 }; 1206 1207 qos_usb_host: qos@ff540000 { 1208 compatible = "syscon"; 1209 reg = <0x0 0xff540000 0x0 0x20>; 1210 }; 1211 1212 qos_usb_otg: qos@ff540080 { 1213 compatible = "syscon"; 1214 reg = <0x0 0xff540080 0x0 0x20>; 1215 }; 1216 1217 qos_isp_128: qos@ff548000 { 1218 compatible = "syscon"; 1219 reg = <0x0 0xff548000 0x0 0x20>; 1220 }; 1221 1222 qos_isp_rd: qos@ff548080 { 1223 compatible = "syscon"; 1224 reg = <0x0 0xff548080 0x0 0x20>; 1225 }; 1226 1227 qos_isp_wr: qos@ff548100 { 1228 compatible = "syscon"; 1229 reg = <0x0 0xff548100 0x0 0x20>; 1230 }; 1231 1232 qos_isp_m1: qos@ff548180 { 1233 compatible = "syscon"; 1234 reg = <0x0 0xff548180 0x0 0x20>; 1235 }; 1236 1237 qos_vip: qos@ff548200 { 1238 compatible = "syscon"; 1239 reg = <0x0 0xff548200 0x0 0x20>; 1240 }; 1241 1242 qos_rga_rd: qos@ff550000 { 1243 compatible = "syscon"; 1244 reg = <0x0 0xff550000 0x0 0x20>; 1245 }; 1246 1247 qos_rga_wr: qos@ff550080 { 1248 compatible = "syscon"; 1249 reg = <0x0 0xff550080 0x0 0x20>; 1250 }; 1251 1252 qos_vop_m0: qos@ff550100 { 1253 compatible = "syscon"; 1254 reg = <0x0 0xff550100 0x0 0x20>; 1255 }; 1256 1257 qos_vop_m1: qos@ff550180 { 1258 compatible = "syscon"; 1259 reg = <0x0 0xff550180 0x0 0x20>; 1260 }; 1261 1262 qos_vpu: qos@ff558000 { 1263 compatible = "syscon"; 1264 reg = <0x0 0xff558000 0x0 0x20>; 1265 }; 1266 1267 qos_vpu_r128: qos@ff558080 { 1268 compatible = "syscon"; 1269 reg = <0x0 0xff558080 0x0 0x20>; 1270 }; 1271 1272 pinctrl: pinctrl { 1273 compatible = "rockchip,px30-pinctrl"; 1274 rockchip,grf = <&grf>; 1275 rockchip,pmu = <&pmugrf>; 1276 #address-cells = <2>; 1277 #size-cells = <2>; 1278 ranges; 1279 1280 gpio0: gpio0@ff040000 { 1281 compatible = "rockchip,gpio-bank"; 1282 reg = <0x0 0xff040000 0x0 0x100>; 1283 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&cru PCLK_GPIO0_PMU>; 1285 gpio-controller; 1286 #gpio-cells = <2>; 1287 1288 interrupt-controller; 1289 #interrupt-cells = <2>; 1290 }; 1291 1292 gpio1: gpio1@ff250000 { 1293 compatible = "rockchip,gpio-bank"; 1294 reg = <0x0 0xff250000 0x0 0x100>; 1295 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1296 clocks = <&cru PCLK_GPIO1>; 1297 gpio-controller; 1298 #gpio-cells = <2>; 1299 1300 interrupt-controller; 1301 #interrupt-cells = <2>; 1302 }; 1303 1304 gpio2: gpio2@ff260000 { 1305 compatible = "rockchip,gpio-bank"; 1306 reg = <0x0 0xff260000 0x0 0x100>; 1307 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&cru PCLK_GPIO2>; 1309 gpio-controller; 1310 #gpio-cells = <2>; 1311 1312 interrupt-controller; 1313 #interrupt-cells = <2>; 1314 }; 1315 1316 gpio3: gpio3@ff270000 { 1317 compatible = "rockchip,gpio-bank"; 1318 reg = <0x0 0xff270000 0x0 0x100>; 1319 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1320 clocks = <&cru PCLK_GPIO3>; 1321 gpio-controller; 1322 #gpio-cells = <2>; 1323 1324 interrupt-controller; 1325 #interrupt-cells = <2>; 1326 }; 1327 1328 pcfg_pull_up: pcfg-pull-up { 1329 bias-pull-up; 1330 }; 1331 1332 pcfg_pull_down: pcfg-pull-down { 1333 bias-pull-down; 1334 }; 1335 1336 pcfg_pull_none: pcfg-pull-none { 1337 bias-disable; 1338 }; 1339 1340 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1341 bias-disable; 1342 drive-strength = <2>; 1343 }; 1344 1345 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1346 bias-pull-up; 1347 drive-strength = <2>; 1348 }; 1349 1350 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1351 bias-pull-up; 1352 drive-strength = <4>; 1353 }; 1354 1355 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1356 bias-disable; 1357 drive-strength = <4>; 1358 }; 1359 1360 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1361 bias-pull-down; 1362 drive-strength = <4>; 1363 }; 1364 1365 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1366 bias-disable; 1367 drive-strength = <8>; 1368 }; 1369 1370 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1371 bias-pull-up; 1372 drive-strength = <8>; 1373 }; 1374 1375 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1376 bias-disable; 1377 drive-strength = <12>; 1378 }; 1379 1380 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1381 bias-pull-up; 1382 drive-strength = <12>; 1383 }; 1384 1385 pcfg_pull_none_smt: pcfg-pull-none-smt { 1386 bias-disable; 1387 input-schmitt-enable; 1388 }; 1389 1390 pcfg_output_high: pcfg-output-high { 1391 output-high; 1392 }; 1393 1394 pcfg_output_low: pcfg-output-low { 1395 output-low; 1396 }; 1397 1398 pcfg_input_high: pcfg-input-high { 1399 bias-pull-up; 1400 input-enable; 1401 }; 1402 1403 pcfg_input: pcfg-input { 1404 input-enable; 1405 }; 1406 1407 i2c0 { 1408 i2c0_xfer: i2c0-xfer { 1409 rockchip,pins = 1410 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1411 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1412 }; 1413 }; 1414 1415 i2c1 { 1416 i2c1_xfer: i2c1-xfer { 1417 rockchip,pins = 1418 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1419 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1420 }; 1421 }; 1422 1423 i2c2 { 1424 i2c2_xfer: i2c2-xfer { 1425 rockchip,pins = 1426 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1427 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1428 }; 1429 }; 1430 1431 i2c3 { 1432 i2c3_xfer: i2c3-xfer { 1433 rockchip,pins = 1434 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1435 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1436 }; 1437 }; 1438 1439 tsadc { 1440 tsadc_otp_gpio: tsadc-otp-gpio { 1441 rockchip,pins = 1442 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1443 }; 1444 1445 tsadc_otp_out: tsadc-otp-out { 1446 rockchip,pins = 1447 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1448 }; 1449 }; 1450 1451 uart0 { 1452 uart0_xfer: uart0-xfer { 1453 rockchip,pins = 1454 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1455 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1456 }; 1457 1458 uart0_cts: uart0-cts { 1459 rockchip,pins = 1460 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1461 }; 1462 1463 uart0_rts: uart0-rts { 1464 rockchip,pins = 1465 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1466 }; 1467 1468 uart0_rts_gpio: uart0-rts-gpio { 1469 rockchip,pins = 1470 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1471 }; 1472 }; 1473 1474 uart1 { 1475 uart1_xfer: uart1-xfer { 1476 rockchip,pins = 1477 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1478 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1479 }; 1480 1481 uart1_cts: uart1-cts { 1482 rockchip,pins = 1483 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1484 }; 1485 1486 uart1_rts: uart1-rts { 1487 rockchip,pins = 1488 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1489 }; 1490 1491 uart1_rts_gpio: uart1-rts-gpio { 1492 rockchip,pins = 1493 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1494 }; 1495 }; 1496 1497 uart2-m0 { 1498 uart2m0_xfer: uart2m0-xfer { 1499 rockchip,pins = 1500 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1501 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1502 }; 1503 }; 1504 1505 uart2-m1 { 1506 uart2m1_xfer: uart2m1-xfer { 1507 rockchip,pins = 1508 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1509 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1510 }; 1511 }; 1512 1513 uart3-m0 { 1514 uart3m0_xfer: uart3m0-xfer { 1515 rockchip,pins = 1516 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1517 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1518 }; 1519 1520 uart3m0_cts: uart3m0-cts { 1521 rockchip,pins = 1522 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1523 }; 1524 1525 uart3m0_rts: uart3m0-rts { 1526 rockchip,pins = 1527 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1528 }; 1529 1530 uart3m0_rts_gpio: uart3m0-rts-gpio { 1531 rockchip,pins = 1532 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1533 }; 1534 }; 1535 1536 uart3-m1 { 1537 uart3m1_xfer: uart3m1-xfer { 1538 rockchip,pins = 1539 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1540 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1541 }; 1542 1543 uart3m1_cts: uart3m1-cts { 1544 rockchip,pins = 1545 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1546 }; 1547 1548 uart3m1_rts: uart3m1-rts { 1549 rockchip,pins = 1550 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1551 }; 1552 1553 uart3m1_rts_gpio: uart3m1-rts-gpio { 1554 rockchip,pins = 1555 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1556 }; 1557 }; 1558 1559 uart4 { 1560 1561 uart4_xfer: uart4-xfer { 1562 rockchip,pins = 1563 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1564 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1565 }; 1566 1567 uart4_cts: uart4-cts { 1568 rockchip,pins = 1569 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1570 1571 }; 1572 1573 uart4_rts: uart4-rts { 1574 rockchip,pins = 1575 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1576 }; 1577 }; 1578 1579 uart5 { 1580 1581 uart5_xfer: uart5-xfer { 1582 rockchip,pins = 1583 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1584 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1585 }; 1586 1587 uart5_cts: uart5-cts { 1588 rockchip,pins = 1589 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1590 1591 }; 1592 1593 uart5_rts: uart5-rts { 1594 rockchip,pins = 1595 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1596 }; 1597 }; 1598 1599 spi0 { 1600 spi0_clk: spi0-clk { 1601 rockchip,pins = 1602 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1603 }; 1604 1605 spi0_csn: spi0-csn { 1606 rockchip,pins = 1607 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1608 }; 1609 1610 spi0_miso: spi0-miso { 1611 rockchip,pins = 1612 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1613 }; 1614 1615 spi0_mosi: spi0-mosi { 1616 rockchip,pins = 1617 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1618 }; 1619 }; 1620 1621 spi1 { 1622 spi1_clk: spi1-clk { 1623 rockchip,pins = 1624 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1625 }; 1626 1627 spi1_csn: spi1-csn { 1628 rockchip,pins = 1629 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1630 }; 1631 1632 spi1_miso: spi1-miso { 1633 rockchip,pins = 1634 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1635 }; 1636 1637 spi1_mosi: spi1-mosi { 1638 rockchip,pins = 1639 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1640 }; 1641 }; 1642 1643 pdm { 1644 pdm_clk0m0: pdm-clk0m0 { 1645 rockchip,pins = 1646 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1647 }; 1648 1649 pdm_clk0m1: pdm-clk0m1 { 1650 rockchip,pins = 1651 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1652 }; 1653 1654 pdm_clk1: pdm-clk1 { 1655 rockchip,pins = 1656 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1657 }; 1658 1659 pdm_sdi0m0: pdm-sdi0m0 { 1660 rockchip,pins = 1661 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1662 }; 1663 1664 pdm_sdi0m1: pdm-sdi0m1 { 1665 rockchip,pins = 1666 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1667 }; 1668 1669 pdm_sdi1: pdm-sdi1 { 1670 rockchip,pins = 1671 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1672 }; 1673 1674 pdm_sdi2: pdm-sdi2 { 1675 rockchip,pins = 1676 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1677 }; 1678 1679 pdm_sdi3: pdm-sdi3 { 1680 rockchip,pins = 1681 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1682 }; 1683 1684 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1685 rockchip,pins = 1686 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1687 }; 1688 1689 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1690 rockchip,pins = 1691 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1692 }; 1693 1694 pdm_clk1_sleep: pdm-clk1-sleep { 1695 rockchip,pins = 1696 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1697 }; 1698 1699 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1700 rockchip,pins = 1701 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1702 }; 1703 1704 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1705 rockchip,pins = 1706 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1707 }; 1708 1709 pdm_sdi1_sleep: pdm-sdi1-sleep { 1710 rockchip,pins = 1711 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1712 }; 1713 1714 pdm_sdi2_sleep: pdm-sdi2-sleep { 1715 rockchip,pins = 1716 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1717 }; 1718 1719 pdm_sdi3_sleep: pdm-sdi3-sleep { 1720 rockchip,pins = 1721 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1722 }; 1723 }; 1724 1725 i2s0 { 1726 i2s0_8ch_mclk: i2s0-8ch-mclk { 1727 rockchip,pins = 1728 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1729 }; 1730 1731 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1732 rockchip,pins = 1733 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1734 }; 1735 1736 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1737 rockchip,pins = 1738 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1739 }; 1740 1741 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1742 rockchip,pins = 1743 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1744 }; 1745 1746 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1747 rockchip,pins = 1748 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1749 }; 1750 1751 i2s0_8ch_sdo: i2s0-8ch-sdo { 1752 rockchip,pins = 1753 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1754 }; 1755 1756 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1757 rockchip,pins = 1758 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1759 }; 1760 1761 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1762 rockchip,pins = 1763 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1764 }; 1765 1766 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1767 rockchip,pins = 1768 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1769 }; 1770 1771 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1772 rockchip,pins = 1773 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1774 }; 1775 1776 i2s0_8ch_sdi: i2s0-8ch-sdi { 1777 rockchip,pins = 1778 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1779 }; 1780 1781 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1782 rockchip,pins = 1783 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1784 }; 1785 1786 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1787 rockchip,pins = 1788 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1789 }; 1790 1791 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1792 rockchip,pins = 1793 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1794 }; 1795 1796 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1797 rockchip,pins = 1798 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1799 }; 1800 }; 1801 1802 i2s1 { 1803 i2s1_2ch_mclk: i2s1-2ch-mclk { 1804 rockchip,pins = 1805 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1806 }; 1807 1808 i2s1_2ch_sclk: i2s1-2ch-sclk { 1809 rockchip,pins = 1810 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1811 }; 1812 1813 i2s1_2ch_lrck: i2s1-2ch-lrck { 1814 rockchip,pins = 1815 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1816 }; 1817 1818 i2s1_2ch_sdi: i2s1-2ch-sdi { 1819 rockchip,pins = 1820 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1821 }; 1822 1823 i2s1_2ch_sdo: i2s1-2ch-sdo { 1824 rockchip,pins = 1825 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1826 }; 1827 }; 1828 1829 i2s2 { 1830 i2s2_2ch_mclk: i2s2-2ch-mclk { 1831 rockchip,pins = 1832 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1833 }; 1834 1835 i2s2_2ch_sclk: i2s2-2ch-sclk { 1836 rockchip,pins = 1837 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1838 }; 1839 1840 i2s2_2ch_lrck: i2s2-2ch-lrck { 1841 rockchip,pins = 1842 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1843 }; 1844 1845 i2s2_2ch_sdi: i2s2-2ch-sdi { 1846 rockchip,pins = 1847 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1848 }; 1849 1850 i2s2_2ch_sdo: i2s2-2ch-sdo { 1851 rockchip,pins = 1852 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1853 }; 1854 }; 1855 1856 sdmmc { 1857 sdmmc_clk: sdmmc-clk { 1858 rockchip,pins = 1859 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_8ma>; 1860 }; 1861 1862 sdmmc_cmd: sdmmc-cmd { 1863 rockchip,pins = 1864 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_8ma>; 1865 }; 1866 1867 sdmmc_det: sdmmc-det { 1868 rockchip,pins = 1869 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>; 1870 }; 1871 1872 sdmmc_bus1: sdmmc-bus1 { 1873 rockchip,pins = 1874 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>; 1875 }; 1876 1877 sdmmc_bus4: sdmmc-bus4 { 1878 rockchip,pins = 1879 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>, 1880 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_8ma>, 1881 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_8ma>, 1882 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_8ma>; 1883 }; 1884 1885 sdmmc_gpio: sdmmc-gpio { 1886 rockchip,pins = 1887 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1888 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1889 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1890 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1891 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1892 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1893 }; 1894 }; 1895 1896 sdio { 1897 sdio_clk: sdio-clk { 1898 rockchip,pins = 1899 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1900 }; 1901 1902 sdio_cmd: sdio-cmd { 1903 rockchip,pins = 1904 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1905 }; 1906 1907 sdio_bus4: sdio-bus4 { 1908 rockchip,pins = 1909 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1910 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>, 1911 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>, 1912 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>; 1913 }; 1914 1915 sdio_gpio: sdio-gpio { 1916 rockchip,pins = 1917 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 1918 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, 1919 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, 1920 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, 1921 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, 1922 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 1923 }; 1924 }; 1925 1926 emmc { 1927 emmc_clk: emmc-clk { 1928 rockchip,pins = 1929 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1930 }; 1931 1932 emmc_cmd: emmc-cmd { 1933 rockchip,pins = 1934 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1935 }; 1936 1937 emmc_pwren: emmc-pwren { 1938 rockchip,pins = 1939 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1940 }; 1941 1942 emmc_rstnout: emmc-rstnout { 1943 rockchip,pins = 1944 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1945 }; 1946 1947 emmc_bus1: emmc-bus1 { 1948 rockchip,pins = 1949 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1950 }; 1951 1952 emmc_bus4: emmc-bus4 { 1953 rockchip,pins = 1954 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1955 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1956 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1957 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1958 }; 1959 1960 emmc_bus8: emmc-bus8 { 1961 rockchip,pins = 1962 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1963 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1964 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1965 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1966 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1967 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1968 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1969 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1970 }; 1971 }; 1972 1973 flash { 1974 flash_cs0: flash-cs0 { 1975 rockchip,pins = 1976 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1977 }; 1978 1979 flash_rdy: flash-rdy { 1980 rockchip,pins = 1981 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1982 }; 1983 1984 flash_dqs: flash-dqs { 1985 rockchip,pins = 1986 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1987 }; 1988 1989 flash_ale: flash-ale { 1990 rockchip,pins = 1991 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1992 }; 1993 1994 flash_cle: flash-cle { 1995 rockchip,pins = 1996 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1997 }; 1998 1999 flash_wrn: flash-wrn { 2000 rockchip,pins = 2001 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2002 }; 2003 2004 flash_csl: flash-csl { 2005 rockchip,pins = 2006 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2007 }; 2008 2009 flash_rdn: flash-rdn { 2010 rockchip,pins = 2011 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2012 }; 2013 2014 flash_bus8: flash-bus8 { 2015 rockchip,pins = 2016 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 2017 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 2018 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 2019 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 2020 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 2021 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 2022 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 2023 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 2024 }; 2025 }; 2026 2027 lcdc { 2028 lcdc_m0_rgb_pins: lcdc-m0-rgb-pins { 2029 rockchip,pins = 2030 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 2031 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_HSYNC */ 2032 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_VSYNC */ 2033 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DEN */ 2034 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 2035 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D1 */ 2036 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 2037 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D3 */ 2038 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D4 */ 2039 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D5 */ 2040 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 2041 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 2042 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D8 */ 2043 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 2044 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D10 */ 2045 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D11 */ 2046 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 2047 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 2048 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 2049 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 2050 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 2051 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 2052 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 2053 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 2054 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 2055 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 2056 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 2057 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ 2058 }; 2059 2060 lcdc_m0_sleep_pins: lcdc-m0-sleep-pins { 2061 rockchip,pins = 2062 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 2063 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ 2064 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ 2065 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ 2066 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 2067 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D1 */ 2068 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 2069 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D3 */ 2070 <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D4 */ 2071 <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D5 */ 2072 <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 2073 <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 2074 <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D8 */ 2075 <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 2076 <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ 2077 <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ 2078 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 2079 <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 2080 <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 2081 <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 2082 <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 2083 <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 2084 <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 2085 <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 2086 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 2087 <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 2088 <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 2089 <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ 2090 }; 2091 }; 2092 2093 pwm0 { 2094 pwm0_pin: pwm0-pin { 2095 rockchip,pins = 2096 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2097 }; 2098 }; 2099 2100 pwm1 { 2101 pwm1_pin: pwm1-pin { 2102 rockchip,pins = 2103 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2104 }; 2105 }; 2106 2107 pwm2 { 2108 pwm2_pin: pwm2-pin { 2109 rockchip,pins = 2110 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2111 }; 2112 }; 2113 2114 pwm3 { 2115 pwm3_pin: pwm3-pin { 2116 rockchip,pins = 2117 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2118 }; 2119 }; 2120 2121 pwm4 { 2122 pwm4_pin: pwm4-pin { 2123 rockchip,pins = 2124 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2125 }; 2126 }; 2127 2128 pwm5 { 2129 pwm5_pin: pwm5-pin { 2130 rockchip,pins = 2131 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2132 }; 2133 }; 2134 2135 pwm6 { 2136 pwm6_pin: pwm6-pin { 2137 rockchip,pins = 2138 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2139 }; 2140 }; 2141 2142 pwm7 { 2143 pwm7_pin: pwm7-pin { 2144 rockchip,pins = 2145 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2146 }; 2147 }; 2148 2149 gmac { 2150 rmii_pins: rmii-pins { 2151 rockchip,pins = 2152 /* mac_txen */ 2153 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2154 /* mac_txd1 */ 2155 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2156 /* mac_txd0 */ 2157 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2158 /* mac_rxd0 */ 2159 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2160 /* mac_rxd1 */ 2161 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2162 /* mac_rxer */ 2163 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2164 /* mac_rxdv */ 2165 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2166 /* mac_mdio */ 2167 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2168 /* mac_mdc */ 2169 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2170 }; 2171 2172 mac_refclk_12ma: mac-refclk-12ma { 2173 rockchip,pins = 2174 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none_12ma>; 2175 }; 2176 2177 mac_refclk: mac-refclk { 2178 rockchip,pins = 2179 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2180 }; 2181 }; 2182 2183 cif-m0 { 2184 cif_clkout_m0: cif-clkout-m0 { 2185 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2186 }; 2187 2188 dvp_d2d9_m0: dvp-d2d9-m0 { 2189 rockchip,pins = 2190 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2191 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2192 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2193 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2194 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2195 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2196 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2197 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2198 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2199 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2200 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2201 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2202 }; 2203 2204 dvp_d0d1_m0: dvp-d0d1-m0 { 2205 rockchip,pins = 2206 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2207 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2208 }; 2209 2210 dvp_d10d11_m0:d10-d11-m0 { 2211 rockchip,pins = 2212 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2213 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2214 }; 2215 }; 2216 2217 cif-m1 { 2218 cif_clkout_m1: cif-clkout-m1 { 2219 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2220 }; 2221 2222 dvp_d2d9_m1: dvp-d2d9-m1 { 2223 rockchip,pins = 2224 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2225 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2226 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2227 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2228 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2229 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2230 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2231 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2232 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2233 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2234 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2235 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2236 }; 2237 2238 dvp_d0d1_m1: dvp-d0d1-m1 { 2239 rockchip,pins = 2240 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2241 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2242 }; 2243 2244 dvp_d10d11_m1:d10-d11-m1 { 2245 rockchip,pins = 2246 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2247 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2248 }; 2249 }; 2250 2251 isp { 2252 isp_prelight: isp-prelight { 2253 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2254 }; 2255 }; 2256 }; 2257}; 2258