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Searched refs:SCLK_PWM0 (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Dpx30-cru.h49 #define SCLK_PWM0 34 macro
H A Drk1808-cru.h85 #define SCLK_PWM0 84 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dpx30-cru.h36 #define SCLK_PWM0 34 macro
H A Drk3308-cru.h30 #define SCLK_PWM0 26 macro
H A Drk1808-cru.h85 #define SCLK_PWM0 84 macro
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk1808.c327 case SCLK_PWM0: in rk1808_pwm_get_clk()
357 case SCLK_PWM0: in rk1808_pwm_set_clk()
950 case SCLK_PWM0: in rk1808_clk_get_rate()
1054 case SCLK_PWM0: in rk1808_clk_set_rate()
H A Dclk_px30.c656 case SCLK_PWM0: in px30_pwm_get_clk()
681 case SCLK_PWM0: in px30_pwm_set_clk()
1339 case SCLK_PWM0: in px30_clk_get_rate()
1425 case SCLK_PWM0: in px30_clk_set_rate()
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk1808.dtsi348 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
359 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
370 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
381 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
H A Dpx30.dtsi559 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
570 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
581 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
592 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi805 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
817 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
829 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
841 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
H A Drk1808.dtsi812 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
823 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
834 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
845 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
H A Dpx30.dtsi1048 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1059 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1070 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1081 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3308.c397 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
H A Dclk-px30.c728 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
H A Dclk-rk1808.c961 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,