| /OK3568_Linux_fs/kernel/sound/soc/codecs/ |
| H A D | ak4642.c | 115 #define PLL1 (1 << 5) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
|
| /OK3568_Linux_fs/u-boot/board/Barix/ipam390/ |
| H A D | ipam390-ais-uart.cfg | 32 ; This section allows setting up the PLL1. Usually this will
57 ; This section can be used to configure the PLL1 and the EMIF3a registers
155 ; This section allows setting up the PLL1. Usually this will
165 ; This section can be used to configure the PLL1 and the EMIF3a registers
182 ; This section can be used to configure the PLL1 and the EMIF3a registers
|
| /OK3568_Linux_fs/kernel/Documentation/arm/sunxi/ |
| H A D | clocks.rst | 20 PLL1
31 PLL1 |
|
| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 126 #define PLL1 117 macro
|
| H A D | stm32mp1-clks.h | 183 #define PLL1 176 macro
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | ti,cdce925.txt | 30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
|
| H A D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/st/ |
| H A D | st,flexgen.txt | 31 | | |PLL1 | | | | | | | | | |
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ti/davinci/ |
| H A D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
|
| /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/ |
| H A D | zl10039.c | 40 PLL1, enumerator
|
| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
|
| /OK3568_Linux_fs/u-boot/doc/ |
| H A D | README.Heterogeneous-SoCs | 54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
|
| /OK3568_Linux_fs/u-boot/drivers/video/tegra124/ |
| H A D | sor.c | 564 DUMP_REG(PLL1); in dump_sor_reg()
723 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | in tegra_dc_sor_enable_dp()
|
| H A D | sor.h | 252 #define PLL1 0x18 macro
|
| /OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/ |
| H A D | gcw0.dts | 447 * Put high-speed peripherals under PLL1, such that we can change the
|
| /OK3568_Linux_fs/kernel/drivers/clk/nxp/ |
| H A D | clk-lpc18xx-cgu.c | 523 LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
|
| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | Kconfig | 187 Y2 and Y3 derive from PLL1
|
| H A D | clk-stm32mp1.c | 1686 PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
|
| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | sun8i-a23-a33.dtsi | 145 * PLL1 is listed twice here.
|
| H A D | sun6i-a31.dtsi | 217 * PLL1 is listed twice here.
|