xref: /OK3568_Linux_fs/kernel/drivers/clk/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun
3*4882a593Smuzhiyunconfig HAVE_CLK
4*4882a593Smuzhiyun	bool
5*4882a593Smuzhiyun	help
6*4882a593Smuzhiyun	  The <linux/clk.h> calls support software clock gating and
7*4882a593Smuzhiyun	  thus are a key power management tool on many systems.
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunconfig CLKDEV_LOOKUP
10*4882a593Smuzhiyun	bool
11*4882a593Smuzhiyun	select HAVE_CLK
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunconfig HAVE_CLK_PREPARE
14*4882a593Smuzhiyun	bool
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunconfig HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated
17*4882a593Smuzhiyun	bool
18*4882a593Smuzhiyun	select HAVE_CLK
19*4882a593Smuzhiyun	help
20*4882a593Smuzhiyun	  Select this option when the clock API in <linux/clk.h> is implemented
21*4882a593Smuzhiyun	  by platform/architecture code. This method is deprecated. Modern
22*4882a593Smuzhiyun	  code should select COMMON_CLK instead and not define a custom
23*4882a593Smuzhiyun	  'struct clk'.
24*4882a593Smuzhiyun
25*4882a593Smuzhiyunmenuconfig COMMON_CLK
26*4882a593Smuzhiyun	bool "Common Clock Framework"
27*4882a593Smuzhiyun	depends on !HAVE_LEGACY_CLK
28*4882a593Smuzhiyun	select HAVE_CLK_PREPARE
29*4882a593Smuzhiyun	select CLKDEV_LOOKUP
30*4882a593Smuzhiyun	select SRCU
31*4882a593Smuzhiyun	select RATIONAL
32*4882a593Smuzhiyun	help
33*4882a593Smuzhiyun	  The common clock framework is a single definition of struct
34*4882a593Smuzhiyun	  clk, useful across many platforms, as well as an
35*4882a593Smuzhiyun	  implementation of the clock API in include/linux/clk.h.
36*4882a593Smuzhiyun	  Architectures utilizing the common struct clk should select
37*4882a593Smuzhiyun	  this option.
38*4882a593Smuzhiyun
39*4882a593Smuzhiyunif COMMON_CLK
40*4882a593Smuzhiyun
41*4882a593Smuzhiyunconfig COMMON_CLK_PROCFS
42*4882a593Smuzhiyun	bool "Common Clock PROCFS interface"
43*4882a593Smuzhiyun	depends on COMMON_CLK && PROC_FS && ARCH_ROCKCHIP
44*4882a593Smuzhiyun	default n
45*4882a593Smuzhiyun	help
46*4882a593Smuzhiyun	  Turns on the PROCFS interface for clock.
47*4882a593Smuzhiyun
48*4882a593Smuzhiyunconfig COMMON_CLK_WM831X
49*4882a593Smuzhiyun	tristate "Clock driver for WM831x/2x PMICs"
50*4882a593Smuzhiyun	depends on MFD_WM831X
51*4882a593Smuzhiyun	help
52*4882a593Smuzhiyun	  Supports the clocking subsystem of the WM831x/2x series of
53*4882a593Smuzhiyun	  PMICs from Wolfson Microelectronics.
54*4882a593Smuzhiyun
55*4882a593Smuzhiyunsource "drivers/clk/versatile/Kconfig"
56*4882a593Smuzhiyun
57*4882a593Smuzhiyunconfig CLK_HSDK
58*4882a593Smuzhiyun	bool "PLL Driver for HSDK platform"
59*4882a593Smuzhiyun	depends on ARC_SOC_HSDK || COMPILE_TEST
60*4882a593Smuzhiyun	depends on HAS_IOMEM
61*4882a593Smuzhiyun	help
62*4882a593Smuzhiyun	  This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
63*4882a593Smuzhiyun	  control.
64*4882a593Smuzhiyun
65*4882a593Smuzhiyunconfig COMMON_CLK_MAX77686
66*4882a593Smuzhiyun	tristate "Clock driver for Maxim 77620/77686/77802 MFD"
67*4882a593Smuzhiyun	depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
68*4882a593Smuzhiyun	help
69*4882a593Smuzhiyun	  This driver supports Maxim 77620/77686/77802 crystal oscillator
70*4882a593Smuzhiyun	  clock.
71*4882a593Smuzhiyun
72*4882a593Smuzhiyunconfig COMMON_CLK_MAX9485
73*4882a593Smuzhiyun	tristate "Maxim 9485 Programmable Clock Generator"
74*4882a593Smuzhiyun	depends on I2C
75*4882a593Smuzhiyun	help
76*4882a593Smuzhiyun	  This driver supports Maxim 9485 Programmable Audio Clock Generator
77*4882a593Smuzhiyun
78*4882a593Smuzhiyunconfig COMMON_CLK_RK808
79*4882a593Smuzhiyun	tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
80*4882a593Smuzhiyun	depends on MFD_RK808
81*4882a593Smuzhiyun	help
82*4882a593Smuzhiyun	  This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
83*4882a593Smuzhiyun	  These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
84*4882a593Smuzhiyun	  Clkout1 is always on, Clkout2 can off by control register.
85*4882a593Smuzhiyun
86*4882a593Smuzhiyunconfig COMMON_CLK_HI655X
87*4882a593Smuzhiyun	tristate "Clock driver for Hi655x" if EXPERT
88*4882a593Smuzhiyun	depends on (MFD_HI655X_PMIC || COMPILE_TEST)
89*4882a593Smuzhiyun	depends on REGMAP
90*4882a593Smuzhiyun	default MFD_HI655X_PMIC
91*4882a593Smuzhiyun	help
92*4882a593Smuzhiyun	  This driver supports the hi655x PMIC clock. This
93*4882a593Smuzhiyun	  multi-function device has one fixed-rate oscillator, clocked
94*4882a593Smuzhiyun	  at 32KHz.
95*4882a593Smuzhiyun
96*4882a593Smuzhiyunconfig COMMON_CLK_SCMI
97*4882a593Smuzhiyun	tristate "Clock driver controlled via SCMI interface"
98*4882a593Smuzhiyun	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
99*4882a593Smuzhiyun	help
100*4882a593Smuzhiyun	  This driver provides support for clocks that are controlled
101*4882a593Smuzhiyun	  by firmware that implements the SCMI interface.
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	  This driver uses SCMI Message Protocol to interact with the
104*4882a593Smuzhiyun	  firmware providing all the clock controls.
105*4882a593Smuzhiyun
106*4882a593Smuzhiyunconfig COMMON_CLK_SCPI
107*4882a593Smuzhiyun	tristate "Clock driver controlled via SCPI interface"
108*4882a593Smuzhiyun	depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
109*4882a593Smuzhiyun	help
110*4882a593Smuzhiyun	  This driver provides support for clocks that are controlled
111*4882a593Smuzhiyun	  by firmware that implements the SCPI interface.
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun	  This driver uses SCPI Message Protocol to interact with the
114*4882a593Smuzhiyun	  firmware providing all the clock controls.
115*4882a593Smuzhiyun
116*4882a593Smuzhiyunconfig COMMON_CLK_SI5341
117*4882a593Smuzhiyun	tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
118*4882a593Smuzhiyun	depends on I2C
119*4882a593Smuzhiyun	select REGMAP_I2C
120*4882a593Smuzhiyun	help
121*4882a593Smuzhiyun	  This driver supports Silicon Labs Si5341 and Si5340 programmable clock
122*4882a593Smuzhiyun	  generators. Not all features of these chips are currently supported
123*4882a593Smuzhiyun	  by the driver, in particular it only supports XTAL input. The chip can
124*4882a593Smuzhiyun	  be pre-programmed to support other configurations and features not yet
125*4882a593Smuzhiyun	  implemented in the driver.
126*4882a593Smuzhiyun
127*4882a593Smuzhiyunconfig COMMON_CLK_SI5351
128*4882a593Smuzhiyun	tristate "Clock driver for SiLabs 5351A/B/C"
129*4882a593Smuzhiyun	depends on I2C
130*4882a593Smuzhiyun	select REGMAP_I2C
131*4882a593Smuzhiyun	help
132*4882a593Smuzhiyun	  This driver supports Silicon Labs 5351A/B/C programmable clock
133*4882a593Smuzhiyun	  generators.
134*4882a593Smuzhiyun
135*4882a593Smuzhiyunconfig COMMON_CLK_SI514
136*4882a593Smuzhiyun	tristate "Clock driver for SiLabs 514 devices"
137*4882a593Smuzhiyun	depends on I2C
138*4882a593Smuzhiyun	depends on OF
139*4882a593Smuzhiyun	select REGMAP_I2C
140*4882a593Smuzhiyun	help
141*4882a593Smuzhiyun	  This driver supports the Silicon Labs 514 programmable clock
142*4882a593Smuzhiyun	  generator.
143*4882a593Smuzhiyun
144*4882a593Smuzhiyunconfig COMMON_CLK_SI544
145*4882a593Smuzhiyun	tristate "Clock driver for SiLabs 544 devices"
146*4882a593Smuzhiyun	depends on I2C
147*4882a593Smuzhiyun	select REGMAP_I2C
148*4882a593Smuzhiyun	help
149*4882a593Smuzhiyun	  This driver supports the Silicon Labs 544 programmable clock
150*4882a593Smuzhiyun	  generator.
151*4882a593Smuzhiyun
152*4882a593Smuzhiyunconfig COMMON_CLK_SI570
153*4882a593Smuzhiyun	tristate "Clock driver for SiLabs 570 and compatible devices"
154*4882a593Smuzhiyun	depends on I2C
155*4882a593Smuzhiyun	depends on OF
156*4882a593Smuzhiyun	select REGMAP_I2C
157*4882a593Smuzhiyun	help
158*4882a593Smuzhiyun	  This driver supports Silicon Labs 570/571/598/599 programmable
159*4882a593Smuzhiyun	  clock generators.
160*4882a593Smuzhiyun
161*4882a593Smuzhiyunconfig COMMON_CLK_BM1880
162*4882a593Smuzhiyun	bool "Clock driver for Bitmain BM1880 SoC"
163*4882a593Smuzhiyun	depends on ARCH_BITMAIN || COMPILE_TEST
164*4882a593Smuzhiyun	default ARCH_BITMAIN
165*4882a593Smuzhiyun	help
166*4882a593Smuzhiyun	  This driver supports the clocks on Bitmain BM1880 SoC.
167*4882a593Smuzhiyun
168*4882a593Smuzhiyunconfig COMMON_CLK_CDCE706
169*4882a593Smuzhiyun	tristate "Clock driver for TI CDCE706 clock synthesizer"
170*4882a593Smuzhiyun	depends on I2C
171*4882a593Smuzhiyun	select REGMAP_I2C
172*4882a593Smuzhiyun	help
173*4882a593Smuzhiyun	  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
174*4882a593Smuzhiyun
175*4882a593Smuzhiyunconfig COMMON_CLK_CDCE925
176*4882a593Smuzhiyun	tristate "Clock driver for TI CDCE913/925/937/949 devices"
177*4882a593Smuzhiyun	depends on I2C
178*4882a593Smuzhiyun	depends on OF
179*4882a593Smuzhiyun	select REGMAP_I2C
180*4882a593Smuzhiyun	help
181*4882a593Smuzhiyun	  This driver supports the TI CDCE913/925/937/949 programmable clock
182*4882a593Smuzhiyun	  synthesizer. Each chip has different number of PLLs and outputs.
183*4882a593Smuzhiyun	  For example, the CDCE925 contains two PLLs with spread-spectrum
184*4882a593Smuzhiyun	  clocking support and five output dividers. The driver only supports
185*4882a593Smuzhiyun	  the following setup, and uses a fixed setting for the output muxes.
186*4882a593Smuzhiyun	  Y1 is derived from the input clock
187*4882a593Smuzhiyun	  Y2 and Y3 derive from PLL1
188*4882a593Smuzhiyun	  Y4 and Y5 derive from PLL2
189*4882a593Smuzhiyun	  Given a target output frequency, the driver will set the PLL and
190*4882a593Smuzhiyun	  divider to best approximate the desired output.
191*4882a593Smuzhiyun
192*4882a593Smuzhiyunconfig COMMON_CLK_CS2000_CP
193*4882a593Smuzhiyun	tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
194*4882a593Smuzhiyun	depends on I2C
195*4882a593Smuzhiyun	help
196*4882a593Smuzhiyun	  If you say yes here you get support for the CS2000 clock multiplier.
197*4882a593Smuzhiyun
198*4882a593Smuzhiyunconfig COMMON_CLK_FSL_SAI
199*4882a593Smuzhiyun	bool "Clock driver for BCLK of Freescale SAI cores"
200*4882a593Smuzhiyun	depends on ARCH_LAYERSCAPE || COMPILE_TEST
201*4882a593Smuzhiyun	help
202*4882a593Smuzhiyun	  This driver supports the Freescale SAI (Synchronous Audio Interface)
203*4882a593Smuzhiyun	  to be used as a generic clock output. Some SoCs have restrictions
204*4882a593Smuzhiyun	  regarding the possible pin multiplexer settings. Eg. on some SoCs
205*4882a593Smuzhiyun	  two SAI interfaces can only be enabled together. If just one is
206*4882a593Smuzhiyun	  needed, the BCLK pin of the second one can be used as general
207*4882a593Smuzhiyun	  purpose clock output. Ideally, it can be used to drive an audio
208*4882a593Smuzhiyun	  codec (sometimes known as MCLK).
209*4882a593Smuzhiyun
210*4882a593Smuzhiyunconfig COMMON_CLK_GEMINI
211*4882a593Smuzhiyun	bool "Clock driver for Cortina Systems Gemini SoC"
212*4882a593Smuzhiyun	depends on ARCH_GEMINI || COMPILE_TEST
213*4882a593Smuzhiyun	select MFD_SYSCON
214*4882a593Smuzhiyun	select RESET_CONTROLLER
215*4882a593Smuzhiyun	help
216*4882a593Smuzhiyun	  This driver supports the SoC clocks on the Cortina Systems Gemini
217*4882a593Smuzhiyun	  platform, also known as SL3516 or CS3516.
218*4882a593Smuzhiyun
219*4882a593Smuzhiyunconfig COMMON_CLK_ASPEED
220*4882a593Smuzhiyun	bool "Clock driver for Aspeed BMC SoCs"
221*4882a593Smuzhiyun	depends on ARCH_ASPEED || COMPILE_TEST
222*4882a593Smuzhiyun	default ARCH_ASPEED
223*4882a593Smuzhiyun	select MFD_SYSCON
224*4882a593Smuzhiyun	select RESET_CONTROLLER
225*4882a593Smuzhiyun	help
226*4882a593Smuzhiyun	  This driver supports the SoC clocks on the Aspeed BMC platforms.
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun	  The G4 and G5 series, including the ast2400 and ast2500, are supported
229*4882a593Smuzhiyun	  by this driver.
230*4882a593Smuzhiyun
231*4882a593Smuzhiyunconfig COMMON_CLK_S2MPS11
232*4882a593Smuzhiyun	tristate "Clock driver for S2MPS1X/S5M8767 MFD"
233*4882a593Smuzhiyun	depends on MFD_SEC_CORE || COMPILE_TEST
234*4882a593Smuzhiyun	help
235*4882a593Smuzhiyun	  This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
236*4882a593Smuzhiyun	  clock. These multi-function devices have two (S2MPS14) or three
237*4882a593Smuzhiyun	  (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
238*4882a593Smuzhiyun
239*4882a593Smuzhiyunconfig CLK_TWL6040
240*4882a593Smuzhiyun	tristate "External McPDM functional clock from twl6040"
241*4882a593Smuzhiyun	depends on TWL6040_CORE
242*4882a593Smuzhiyun	help
243*4882a593Smuzhiyun	  Enable the external functional clock support on OMAP4+ platforms for
244*4882a593Smuzhiyun	  McPDM. McPDM module is using the external bit clock on the McPDM bus
245*4882a593Smuzhiyun	  as functional clock.
246*4882a593Smuzhiyun
247*4882a593Smuzhiyunconfig COMMON_CLK_AXI_CLKGEN
248*4882a593Smuzhiyun	tristate "AXI clkgen driver"
249*4882a593Smuzhiyun	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
250*4882a593Smuzhiyun	help
251*4882a593Smuzhiyun	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
252*4882a593Smuzhiyun	  FPGAs. It is commonly used in Analog Devices' reference designs.
253*4882a593Smuzhiyun
254*4882a593Smuzhiyunconfig CLK_QORIQ
255*4882a593Smuzhiyun	bool "Clock driver for Freescale QorIQ platforms"
256*4882a593Smuzhiyun	depends on (PPC_E500MC || ARM || ARM64 || COMPILE_TEST) && OF
257*4882a593Smuzhiyun	help
258*4882a593Smuzhiyun	  This adds the clock driver support for Freescale QorIQ platforms
259*4882a593Smuzhiyun	  using common clock framework.
260*4882a593Smuzhiyun
261*4882a593Smuzhiyunconfig CLK_LS1028A_PLLDIG
262*4882a593Smuzhiyun        tristate "Clock driver for LS1028A Display output"
263*4882a593Smuzhiyun        depends on ARCH_LAYERSCAPE || COMPILE_TEST
264*4882a593Smuzhiyun        default ARCH_LAYERSCAPE
265*4882a593Smuzhiyun        help
266*4882a593Smuzhiyun          This driver support the Display output interfaces(LCD, DPHY) pixel clocks
267*4882a593Smuzhiyun          of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
268*4882a593Smuzhiyun          features of the PLL are currently supported by the driver. By default,
269*4882a593Smuzhiyun          configured bypass mode with this PLL.
270*4882a593Smuzhiyun
271*4882a593Smuzhiyunconfig COMMON_CLK_XGENE
272*4882a593Smuzhiyun	bool "Clock driver for APM XGene SoC"
273*4882a593Smuzhiyun	default ARCH_XGENE
274*4882a593Smuzhiyun	depends on ARM64 || COMPILE_TEST
275*4882a593Smuzhiyun	help
276*4882a593Smuzhiyun	  Support for the APM X-Gene SoC reference, PLL, and device clocks.
277*4882a593Smuzhiyun
278*4882a593Smuzhiyunconfig COMMON_CLK_LOCHNAGAR
279*4882a593Smuzhiyun	tristate "Cirrus Logic Lochnagar clock driver"
280*4882a593Smuzhiyun	depends on MFD_LOCHNAGAR
281*4882a593Smuzhiyun	help
282*4882a593Smuzhiyun	  This driver supports the clocking features of the Cirrus Logic
283*4882a593Smuzhiyun	  Lochnagar audio development board.
284*4882a593Smuzhiyun
285*4882a593Smuzhiyunconfig COMMON_CLK_NXP
286*4882a593Smuzhiyun	def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
287*4882a593Smuzhiyun	select REGMAP_MMIO if ARCH_LPC32XX
288*4882a593Smuzhiyun	select MFD_SYSCON if ARCH_LPC18XX
289*4882a593Smuzhiyun	help
290*4882a593Smuzhiyun	  Support for clock providers on NXP platforms.
291*4882a593Smuzhiyun
292*4882a593Smuzhiyunconfig COMMON_CLK_PALMAS
293*4882a593Smuzhiyun	tristate "Clock driver for TI Palmas devices"
294*4882a593Smuzhiyun	depends on MFD_PALMAS
295*4882a593Smuzhiyun	help
296*4882a593Smuzhiyun	  This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
297*4882a593Smuzhiyun	  using common clock framework.
298*4882a593Smuzhiyun
299*4882a593Smuzhiyunconfig COMMON_CLK_PWM
300*4882a593Smuzhiyun	tristate "Clock driver for PWMs used as clock outputs"
301*4882a593Smuzhiyun	depends on PWM
302*4882a593Smuzhiyun	help
303*4882a593Smuzhiyun	  Adapter driver so that any PWM output can be (mis)used as clock signal
304*4882a593Smuzhiyun	  at 50% duty cycle.
305*4882a593Smuzhiyun
306*4882a593Smuzhiyunconfig COMMON_CLK_PXA
307*4882a593Smuzhiyun	def_bool COMMON_CLK && ARCH_PXA
308*4882a593Smuzhiyun	help
309*4882a593Smuzhiyun	  Support for the Marvell PXA SoC.
310*4882a593Smuzhiyun
311*4882a593Smuzhiyunconfig COMMON_CLK_PIC32
312*4882a593Smuzhiyun	def_bool COMMON_CLK && MACH_PIC32
313*4882a593Smuzhiyun
314*4882a593Smuzhiyunconfig COMMON_CLK_OXNAS
315*4882a593Smuzhiyun	bool "Clock driver for the OXNAS SoC Family"
316*4882a593Smuzhiyun	depends on ARCH_OXNAS || COMPILE_TEST
317*4882a593Smuzhiyun	select MFD_SYSCON
318*4882a593Smuzhiyun	help
319*4882a593Smuzhiyun	  Support for the OXNAS SoC Family clocks.
320*4882a593Smuzhiyun
321*4882a593Smuzhiyunconfig COMMON_CLK_VC5
322*4882a593Smuzhiyun	tristate "Clock driver for IDT VersaClock 5,6 devices"
323*4882a593Smuzhiyun	depends on I2C
324*4882a593Smuzhiyun	depends on OF
325*4882a593Smuzhiyun	select REGMAP_I2C
326*4882a593Smuzhiyun	help
327*4882a593Smuzhiyun	  This driver supports the IDT VersaClock 5 and VersaClock 6
328*4882a593Smuzhiyun	  programmable clock generators.
329*4882a593Smuzhiyun
330*4882a593Smuzhiyunconfig COMMON_CLK_STM32MP157
331*4882a593Smuzhiyun	def_bool COMMON_CLK && MACH_STM32MP157
332*4882a593Smuzhiyun	help
333*4882a593Smuzhiyun	  Support for stm32mp157 SoC family clocks
334*4882a593Smuzhiyun
335*4882a593Smuzhiyunconfig COMMON_CLK_STM32F
336*4882a593Smuzhiyun	def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
337*4882a593Smuzhiyun	help
338*4882a593Smuzhiyun	  Support for stm32f4 and stm32f7 SoC families clocks
339*4882a593Smuzhiyun
340*4882a593Smuzhiyunconfig COMMON_CLK_STM32H7
341*4882a593Smuzhiyun	def_bool COMMON_CLK && MACH_STM32H743
342*4882a593Smuzhiyun	help
343*4882a593Smuzhiyun	  Support for stm32h7 SoC family clocks
344*4882a593Smuzhiyun
345*4882a593Smuzhiyunconfig COMMON_CLK_MMP2
346*4882a593Smuzhiyun	def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
347*4882a593Smuzhiyun	help
348*4882a593Smuzhiyun	  Support for Marvell MMP2 and MMP3 SoC clocks
349*4882a593Smuzhiyun
350*4882a593Smuzhiyunconfig COMMON_CLK_MMP2_AUDIO
351*4882a593Smuzhiyun        tristate "Clock driver for MMP2 Audio subsystem"
352*4882a593Smuzhiyun        depends on COMMON_CLK_MMP2 || COMPILE_TEST
353*4882a593Smuzhiyun        help
354*4882a593Smuzhiyun          This driver supports clocks for Audio subsystem on MMP2 SoC.
355*4882a593Smuzhiyun
356*4882a593Smuzhiyunconfig COMMON_CLK_BD718XX
357*4882a593Smuzhiyun	tristate "Clock driver for 32K clk gates on ROHM PMICs"
358*4882a593Smuzhiyun	depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828
359*4882a593Smuzhiyun	help
360*4882a593Smuzhiyun	  This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and
361*4882a593Smuzhiyun	  ROHM BD70528 PMICs clock gates.
362*4882a593Smuzhiyun
363*4882a593Smuzhiyunconfig COMMON_CLK_FIXED_MMIO
364*4882a593Smuzhiyun	bool "Clock driver for Memory Mapped Fixed values"
365*4882a593Smuzhiyun	depends on COMMON_CLK && OF
366*4882a593Smuzhiyun	help
367*4882a593Smuzhiyun	  Support for Memory Mapped IO Fixed clocks
368*4882a593Smuzhiyun
369*4882a593Smuzhiyunsource "drivers/clk/actions/Kconfig"
370*4882a593Smuzhiyunsource "drivers/clk/analogbits/Kconfig"
371*4882a593Smuzhiyunsource "drivers/clk/baikal-t1/Kconfig"
372*4882a593Smuzhiyunsource "drivers/clk/bcm/Kconfig"
373*4882a593Smuzhiyunsource "drivers/clk/hisilicon/Kconfig"
374*4882a593Smuzhiyunsource "drivers/clk/imgtec/Kconfig"
375*4882a593Smuzhiyunsource "drivers/clk/imx/Kconfig"
376*4882a593Smuzhiyunsource "drivers/clk/ingenic/Kconfig"
377*4882a593Smuzhiyunsource "drivers/clk/keystone/Kconfig"
378*4882a593Smuzhiyunsource "drivers/clk/mediatek/Kconfig"
379*4882a593Smuzhiyunsource "drivers/clk/meson/Kconfig"
380*4882a593Smuzhiyunsource "drivers/clk/mvebu/Kconfig"
381*4882a593Smuzhiyunsource "drivers/clk/qcom/Kconfig"
382*4882a593Smuzhiyunsource "drivers/clk/renesas/Kconfig"
383*4882a593Smuzhiyunsource "drivers/clk/rockchip/Kconfig"
384*4882a593Smuzhiyunsource "drivers/clk/samsung/Kconfig"
385*4882a593Smuzhiyunsource "drivers/clk/sifive/Kconfig"
386*4882a593Smuzhiyunsource "drivers/clk/sprd/Kconfig"
387*4882a593Smuzhiyunsource "drivers/clk/sunxi/Kconfig"
388*4882a593Smuzhiyunsource "drivers/clk/sunxi-ng/Kconfig"
389*4882a593Smuzhiyunsource "drivers/clk/tegra/Kconfig"
390*4882a593Smuzhiyunsource "drivers/clk/ti/Kconfig"
391*4882a593Smuzhiyunsource "drivers/clk/uniphier/Kconfig"
392*4882a593Smuzhiyunsource "drivers/clk/x86/Kconfig"
393*4882a593Smuzhiyunsource "drivers/clk/zynqmp/Kconfig"
394*4882a593Smuzhiyun
395*4882a593Smuzhiyunendif
396