1*4882a593SmuzhiyunBinding for TI DaVinci PLL Controllers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe PLL provides clocks to most of the components on the SoC. In addition 4*4882a593Smuzhiyunto the PLL itself, this controller also contains bypasses, gates, dividers, 5*4882a593Smuzhiyunan multiplexers for various clock signals. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: shall be one of: 9*4882a593Smuzhiyun - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX 10*4882a593Smuzhiyun - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX 11*4882a593Smuzhiyun- reg: physical base address and size of the controller's register area. 12*4882a593Smuzhiyun- clocks: phandles corresponding to the clock names 13*4882a593Smuzhiyun- clock-names: names of the clock sources - depends on compatible string 14*4882a593Smuzhiyun - for "ti,da850-pll0", shall be "clksrc", "extclksrc" 15*4882a593Smuzhiyun - for "ti,da850-pll1", shall be "clksrc" 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun- ti,clkmode-square-wave: Indicates that the the board is supplying a square 19*4882a593Smuzhiyun wave input on the OSCIN pin instead of using a crystal oscillator. 20*4882a593Smuzhiyun This property is only valid when compatible = "ti,da850-pll0". 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional child nodes: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunpllout 26*4882a593Smuzhiyun Describes the main PLL clock output (before POSTDIV). The node name must 27*4882a593Smuzhiyun be "pllout". 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun Required properties: 30*4882a593Smuzhiyun - #clock-cells: shall be 0 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunsysclk 33*4882a593Smuzhiyun Describes the PLLDIVn divider clocks that provide the SYSCLKn clock 34*4882a593Smuzhiyun domains. The node name must be "sysclk". Consumers of this node should 35*4882a593Smuzhiyun use "n" in "SYSCLKn" as the index parameter for the clock cell. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun Required properties: 38*4882a593Smuzhiyun - #clock-cells: shall be 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunauxclk 41*4882a593Smuzhiyun Describes the AUXCLK output of the PLL. The node name must be "auxclk". 42*4882a593Smuzhiyun This child node is only valid when compatible = "ti,da850-pll0". 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun Required properties: 45*4882a593Smuzhiyun - #clock-cells: shall be 0 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunobsclk 48*4882a593Smuzhiyun Describes the OBSCLK output of the PLL. The node name must be "obsclk". 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun Required properties: 51*4882a593Smuzhiyun - #clock-cells: shall be 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunExamples: 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun pll0: clock-controller@11000 { 57*4882a593Smuzhiyun compatible = "ti,da850-pll0"; 58*4882a593Smuzhiyun reg = <0x11000 0x1000>; 59*4882a593Smuzhiyun clocks = <&ref_clk>, <&pll1_sysclk 3>; 60*4882a593Smuzhiyun clock-names = "clksrc", "extclksrc"; 61*4882a593Smuzhiyun ti,clkmode-square-wave; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun pll0_pllout: pllout { 64*4882a593Smuzhiyun #clock-cells = <0>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun pll0_sysclk: sysclk { 68*4882a593Smuzhiyun #clock-cells = <1>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun pll0_auxclk: auxclk { 72*4882a593Smuzhiyun #clock-cells = <0>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun pll0_obsclk: obsclk { 76*4882a593Smuzhiyun #clock-cells = <0>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun pll1: clock-controller@21a000 { 81*4882a593Smuzhiyun compatible = "ti,da850-pll1"; 82*4882a593Smuzhiyun reg = <0x21a000 0x1000>; 83*4882a593Smuzhiyun clocks = <&ref_clk>; 84*4882a593Smuzhiyun clock-names = "clksrc"; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun pll0_sysclk: sysclk { 87*4882a593Smuzhiyun #clock-cells = <1>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun pll0_obsclk: obsclk { 91*4882a593Smuzhiyun #clock-cells = <0>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593SmuzhiyunAlso see: 96*4882a593Smuzhiyun- Documentation/devicetree/bindings/clock/clock-bindings.txt 97