1*4882a593SmuzhiyunBinding for TI CDCE913/925/937/949 programmable I2C clock synthesizers. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunReference 4*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 7*4882a593Smuzhiyun[2] https://www.ti.com/product/cdce913 8*4882a593Smuzhiyun[3] https://www.ti.com/product/cdce925 9*4882a593Smuzhiyun[4] https://www.ti.com/product/cdce937 10*4882a593Smuzhiyun[5] https://www.ti.com/product/cdce949 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunThe driver provides clock sources for each output Y1 through Y5. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties: 15*4882a593Smuzhiyun - compatible: Shall be one of the following: 16*4882a593Smuzhiyun - "ti,cdce913": 1-PLL, 3 Outputs 17*4882a593Smuzhiyun - "ti,cdce925": 2-PLL, 5 Outputs 18*4882a593Smuzhiyun - "ti,cdce937": 3-PLL, 7 Outputs 19*4882a593Smuzhiyun - "ti,cdce949": 4-PLL, 9 Outputs 20*4882a593Smuzhiyun - reg: I2C device address. 21*4882a593Smuzhiyun - clocks: Points to a fixed parent clock that provides the input frequency. 22*4882a593Smuzhiyun - #clock-cells: From common clock bindings: Shall be 1. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional properties: 25*4882a593Smuzhiyun - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a 26*4882a593Smuzhiyun board, or to compensate for external influences. 27*4882a593Smuzhiyun- vdd-supply: A regulator node for Vdd 28*4882a593Smuzhiyun- vddout-supply: A regulator node for Vddout 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunFor all PLL1, PLL2, ... an optional child node can be used to specify spread 31*4882a593Smuzhiyunspectrum clocking parameters for a board. 32*4882a593Smuzhiyun - spread-spectrum: SSC mode as defined in the data sheet. 33*4882a593Smuzhiyun - spread-spectrum-center: Use "centered" mode instead of "max" mode. When 34*4882a593Smuzhiyun present, the clock runs at the requested frequency on average. Otherwise 35*4882a593Smuzhiyun the requested frequency is the maximum value of the SCC range. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunExample: 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun clockgen: cdce925pw@64 { 41*4882a593Smuzhiyun compatible = "cdce925"; 42*4882a593Smuzhiyun reg = <0x64>; 43*4882a593Smuzhiyun clocks = <&xtal_27Mhz>; 44*4882a593Smuzhiyun #clock-cells = <1>; 45*4882a593Smuzhiyun xtal-load-pf = <5>; 46*4882a593Smuzhiyun vdd-supply = <&1v8-reg>; 47*4882a593Smuzhiyun vddout-supply = <&3v3-reg>; 48*4882a593Smuzhiyun /* PLL options to get SSC 1% centered */ 49*4882a593Smuzhiyun PLL2 { 50*4882a593Smuzhiyun spread-spectrum = <4>; 51*4882a593Smuzhiyun spread-spectrum-center; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54