1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 4*4882a593Smuzhiyun * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ 8*4882a593Smuzhiyun #define _DT_BINDINGS_STM32MP1_CLKS_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* OSCILLATOR clocks */ 11*4882a593Smuzhiyun #define CK_HSE 0 12*4882a593Smuzhiyun #define CK_CSI 1 13*4882a593Smuzhiyun #define CK_LSI 2 14*4882a593Smuzhiyun #define CK_LSE 3 15*4882a593Smuzhiyun #define CK_HSI 4 16*4882a593Smuzhiyun #define CK_HSE_DIV2 5 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Bus clocks */ 19*4882a593Smuzhiyun #define TIM2 6 20*4882a593Smuzhiyun #define TIM3 7 21*4882a593Smuzhiyun #define TIM4 8 22*4882a593Smuzhiyun #define TIM5 9 23*4882a593Smuzhiyun #define TIM6 10 24*4882a593Smuzhiyun #define TIM7 11 25*4882a593Smuzhiyun #define TIM12 12 26*4882a593Smuzhiyun #define TIM13 13 27*4882a593Smuzhiyun #define TIM14 14 28*4882a593Smuzhiyun #define LPTIM1 15 29*4882a593Smuzhiyun #define SPI2 16 30*4882a593Smuzhiyun #define SPI3 17 31*4882a593Smuzhiyun #define USART2 18 32*4882a593Smuzhiyun #define USART3 19 33*4882a593Smuzhiyun #define UART4 20 34*4882a593Smuzhiyun #define UART5 21 35*4882a593Smuzhiyun #define UART7 22 36*4882a593Smuzhiyun #define UART8 23 37*4882a593Smuzhiyun #define I2C1 24 38*4882a593Smuzhiyun #define I2C2 25 39*4882a593Smuzhiyun #define I2C3 26 40*4882a593Smuzhiyun #define I2C5 27 41*4882a593Smuzhiyun #define SPDIF 28 42*4882a593Smuzhiyun #define CEC 29 43*4882a593Smuzhiyun #define DAC12 30 44*4882a593Smuzhiyun #define MDIO 31 45*4882a593Smuzhiyun #define TIM1 32 46*4882a593Smuzhiyun #define TIM8 33 47*4882a593Smuzhiyun #define TIM15 34 48*4882a593Smuzhiyun #define TIM16 35 49*4882a593Smuzhiyun #define TIM17 36 50*4882a593Smuzhiyun #define SPI1 37 51*4882a593Smuzhiyun #define SPI4 38 52*4882a593Smuzhiyun #define SPI5 39 53*4882a593Smuzhiyun #define USART6 40 54*4882a593Smuzhiyun #define SAI1 41 55*4882a593Smuzhiyun #define SAI2 42 56*4882a593Smuzhiyun #define SAI3 43 57*4882a593Smuzhiyun #define DFSDM 44 58*4882a593Smuzhiyun #define FDCAN 45 59*4882a593Smuzhiyun #define LPTIM2 46 60*4882a593Smuzhiyun #define LPTIM3 47 61*4882a593Smuzhiyun #define LPTIM4 48 62*4882a593Smuzhiyun #define LPTIM5 49 63*4882a593Smuzhiyun #define SAI4 50 64*4882a593Smuzhiyun #define SYSCFG 51 65*4882a593Smuzhiyun #define VREF 52 66*4882a593Smuzhiyun #define TMPSENS 53 67*4882a593Smuzhiyun #define PMBCTRL 54 68*4882a593Smuzhiyun #define HDP 55 69*4882a593Smuzhiyun #define LTDC 56 70*4882a593Smuzhiyun #define DSI 57 71*4882a593Smuzhiyun #define IWDG2 58 72*4882a593Smuzhiyun #define USBPHY 59 73*4882a593Smuzhiyun #define STGENRO 60 74*4882a593Smuzhiyun #define SPI6 61 75*4882a593Smuzhiyun #define I2C4 62 76*4882a593Smuzhiyun #define I2C6 63 77*4882a593Smuzhiyun #define USART1 64 78*4882a593Smuzhiyun #define RTCAPB 65 79*4882a593Smuzhiyun #define TZC1 66 80*4882a593Smuzhiyun #define TZPC 67 81*4882a593Smuzhiyun #define IWDG1 68 82*4882a593Smuzhiyun #define BSEC 69 83*4882a593Smuzhiyun #define STGEN 70 84*4882a593Smuzhiyun #define DMA1 71 85*4882a593Smuzhiyun #define DMA2 72 86*4882a593Smuzhiyun #define DMAMUX 73 87*4882a593Smuzhiyun #define ADC12 74 88*4882a593Smuzhiyun #define USBO 75 89*4882a593Smuzhiyun #define SDMMC3 76 90*4882a593Smuzhiyun #define DCMI 77 91*4882a593Smuzhiyun #define CRYP2 78 92*4882a593Smuzhiyun #define HASH2 79 93*4882a593Smuzhiyun #define RNG2 80 94*4882a593Smuzhiyun #define CRC2 81 95*4882a593Smuzhiyun #define HSEM 82 96*4882a593Smuzhiyun #define IPCC 83 97*4882a593Smuzhiyun #define GPIOA 84 98*4882a593Smuzhiyun #define GPIOB 85 99*4882a593Smuzhiyun #define GPIOC 86 100*4882a593Smuzhiyun #define GPIOD 87 101*4882a593Smuzhiyun #define GPIOE 88 102*4882a593Smuzhiyun #define GPIOF 89 103*4882a593Smuzhiyun #define GPIOG 90 104*4882a593Smuzhiyun #define GPIOH 91 105*4882a593Smuzhiyun #define GPIOI 92 106*4882a593Smuzhiyun #define GPIOJ 93 107*4882a593Smuzhiyun #define GPIOK 94 108*4882a593Smuzhiyun #define GPIOZ 95 109*4882a593Smuzhiyun #define CRYP1 96 110*4882a593Smuzhiyun #define HASH1 97 111*4882a593Smuzhiyun #define RNG1 98 112*4882a593Smuzhiyun #define BKPSRAM 99 113*4882a593Smuzhiyun #define MDMA 100 114*4882a593Smuzhiyun #define GPU 101 115*4882a593Smuzhiyun #define ETHCK 102 116*4882a593Smuzhiyun #define ETHTX 103 117*4882a593Smuzhiyun #define ETHRX 104 118*4882a593Smuzhiyun #define ETHMAC 105 119*4882a593Smuzhiyun #define FMC 106 120*4882a593Smuzhiyun #define QSPI 107 121*4882a593Smuzhiyun #define SDMMC1 108 122*4882a593Smuzhiyun #define SDMMC2 109 123*4882a593Smuzhiyun #define CRC1 110 124*4882a593Smuzhiyun #define USBH 111 125*4882a593Smuzhiyun #define ETHSTP 112 126*4882a593Smuzhiyun #define TZC2 113 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* Kernel clocks */ 129*4882a593Smuzhiyun #define SDMMC1_K 118 130*4882a593Smuzhiyun #define SDMMC2_K 119 131*4882a593Smuzhiyun #define SDMMC3_K 120 132*4882a593Smuzhiyun #define FMC_K 121 133*4882a593Smuzhiyun #define QSPI_K 122 134*4882a593Smuzhiyun #define ETHCK_K 123 135*4882a593Smuzhiyun #define RNG1_K 124 136*4882a593Smuzhiyun #define RNG2_K 125 137*4882a593Smuzhiyun #define GPU_K 126 138*4882a593Smuzhiyun #define USBPHY_K 127 139*4882a593Smuzhiyun #define STGEN_K 128 140*4882a593Smuzhiyun #define SPDIF_K 129 141*4882a593Smuzhiyun #define SPI1_K 130 142*4882a593Smuzhiyun #define SPI2_K 131 143*4882a593Smuzhiyun #define SPI3_K 132 144*4882a593Smuzhiyun #define SPI4_K 133 145*4882a593Smuzhiyun #define SPI5_K 134 146*4882a593Smuzhiyun #define SPI6_K 135 147*4882a593Smuzhiyun #define CEC_K 136 148*4882a593Smuzhiyun #define I2C1_K 137 149*4882a593Smuzhiyun #define I2C2_K 138 150*4882a593Smuzhiyun #define I2C3_K 139 151*4882a593Smuzhiyun #define I2C4_K 140 152*4882a593Smuzhiyun #define I2C5_K 141 153*4882a593Smuzhiyun #define I2C6_K 142 154*4882a593Smuzhiyun #define LPTIM1_K 143 155*4882a593Smuzhiyun #define LPTIM2_K 144 156*4882a593Smuzhiyun #define LPTIM3_K 145 157*4882a593Smuzhiyun #define LPTIM4_K 146 158*4882a593Smuzhiyun #define LPTIM5_K 147 159*4882a593Smuzhiyun #define USART1_K 148 160*4882a593Smuzhiyun #define USART2_K 149 161*4882a593Smuzhiyun #define USART3_K 150 162*4882a593Smuzhiyun #define UART4_K 151 163*4882a593Smuzhiyun #define UART5_K 152 164*4882a593Smuzhiyun #define USART6_K 153 165*4882a593Smuzhiyun #define UART7_K 154 166*4882a593Smuzhiyun #define UART8_K 155 167*4882a593Smuzhiyun #define DFSDM_K 156 168*4882a593Smuzhiyun #define FDCAN_K 157 169*4882a593Smuzhiyun #define SAI1_K 158 170*4882a593Smuzhiyun #define SAI2_K 159 171*4882a593Smuzhiyun #define SAI3_K 160 172*4882a593Smuzhiyun #define SAI4_K 161 173*4882a593Smuzhiyun #define ADC12_K 162 174*4882a593Smuzhiyun #define DSI_K 163 175*4882a593Smuzhiyun #define DSI_PX 164 176*4882a593Smuzhiyun #define ADFSDM_K 165 177*4882a593Smuzhiyun #define USBO_K 166 178*4882a593Smuzhiyun #define LTDC_PX 167 179*4882a593Smuzhiyun #define DAC12_K 168 180*4882a593Smuzhiyun #define ETHPTP_K 169 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* PLL */ 183*4882a593Smuzhiyun #define PLL1 176 184*4882a593Smuzhiyun #define PLL2 177 185*4882a593Smuzhiyun #define PLL3 178 186*4882a593Smuzhiyun #define PLL4 179 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* ODF */ 189*4882a593Smuzhiyun #define PLL1_P 180 190*4882a593Smuzhiyun #define PLL1_Q 181 191*4882a593Smuzhiyun #define PLL1_R 182 192*4882a593Smuzhiyun #define PLL2_P 183 193*4882a593Smuzhiyun #define PLL2_Q 184 194*4882a593Smuzhiyun #define PLL2_R 185 195*4882a593Smuzhiyun #define PLL3_P 186 196*4882a593Smuzhiyun #define PLL3_Q 187 197*4882a593Smuzhiyun #define PLL3_R 188 198*4882a593Smuzhiyun #define PLL4_P 189 199*4882a593Smuzhiyun #define PLL4_Q 190 200*4882a593Smuzhiyun #define PLL4_R 191 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* AUX */ 203*4882a593Smuzhiyun #define RTC 192 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* MCLK */ 206*4882a593Smuzhiyun #define CK_PER 193 207*4882a593Smuzhiyun #define CK_MPU 194 208*4882a593Smuzhiyun #define CK_AXI 195 209*4882a593Smuzhiyun #define CK_MCU 196 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* Time base */ 212*4882a593Smuzhiyun #define TIM2_K 197 213*4882a593Smuzhiyun #define TIM3_K 198 214*4882a593Smuzhiyun #define TIM4_K 199 215*4882a593Smuzhiyun #define TIM5_K 200 216*4882a593Smuzhiyun #define TIM6_K 201 217*4882a593Smuzhiyun #define TIM7_K 202 218*4882a593Smuzhiyun #define TIM12_K 203 219*4882a593Smuzhiyun #define TIM13_K 204 220*4882a593Smuzhiyun #define TIM14_K 205 221*4882a593Smuzhiyun #define TIM1_K 206 222*4882a593Smuzhiyun #define TIM8_K 207 223*4882a593Smuzhiyun #define TIM15_K 208 224*4882a593Smuzhiyun #define TIM16_K 209 225*4882a593Smuzhiyun #define TIM17_K 210 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun /* MCO clocks */ 228*4882a593Smuzhiyun #define CK_MCO1 211 229*4882a593Smuzhiyun #define CK_MCO2 212 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* TRACE & DEBUG clocks */ 232*4882a593Smuzhiyun #define CK_DBG 214 233*4882a593Smuzhiyun #define CK_TRACE 215 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun /* DDR */ 236*4882a593Smuzhiyun #define DDRC1 220 237*4882a593Smuzhiyun #define DDRC1LP 221 238*4882a593Smuzhiyun #define DDRC2 222 239*4882a593Smuzhiyun #define DDRC2LP 223 240*4882a593Smuzhiyun #define DDRPHYC 224 241*4882a593Smuzhiyun #define DDRPHYCLP 225 242*4882a593Smuzhiyun #define DDRCAPB 226 243*4882a593Smuzhiyun #define DDRCAPBLP 227 244*4882a593Smuzhiyun #define AXIDCG 228 245*4882a593Smuzhiyun #define DDRPHYCAPB 229 246*4882a593Smuzhiyun #define DDRPHYCAPBLP 230 247*4882a593Smuzhiyun #define DDRPERFM 231 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define STM32MP1_LAST_CLK 232 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ 252