1*4882a593SmuzhiyunST Microelectronics Nomadik SRC System Reset and Control 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding: 4*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe Nomadik SRC controller is responsible of controlling chrystals, 7*4882a593SmuzhiyunPLLs and clock gates. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties for the SRC node: 10*4882a593Smuzhiyun- compatible: must be "stericsson,nomadik-src" 11*4882a593Smuzhiyun- reg: must contain the SRC register base and size 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOptional properties for the SRC node: 14*4882a593Smuzhiyun- disable-sxtalo: if present this will disable the SXTALO 15*4882a593Smuzhiyun i.e. the driver output for the slow 32kHz chrystal, if the 16*4882a593Smuzhiyun board has its own circuitry for providing this oscillator 17*4882a593Smuzhiyun- disable-mxtal: if present this will disable the MXTALO, 18*4882a593Smuzhiyun i.e. the driver output for the main (~19.2 MHz) chrystal, 19*4882a593Smuzhiyun if the board has its own circuitry for providing this 20*4882a593Smuzhiyun oscillator 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunPLL nodes: these nodes represent the two PLLs on the system, 24*4882a593Smuzhiyunwhich should both have the main chrystal, represented as a 25*4882a593Smuzhiyunfixed frequency clock, as parent. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunRequired properties for the two PLL nodes: 28*4882a593Smuzhiyun- compatible: must be "st,nomadik-pll-clock" 29*4882a593Smuzhiyun- clock-cells: must be 0 30*4882a593Smuzhiyun- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively 31*4882a593Smuzhiyun- clocks: this clock will have main chrystal as parent 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunHCLK nodes: these represent the clock gates on individual 35*4882a593Smuzhiyunlines from the HCLK clock tree and the gate for individual 36*4882a593Smuzhiyunlines from the PCLK clock tree. 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunRequires properties for the HCLK nodes: 39*4882a593Smuzhiyun- compatible: must be "st,nomadik-hclk-clock" 40*4882a593Smuzhiyun- clock-cells: must be 0 41*4882a593Smuzhiyun- clock-id: must be the clock ID from 0 to 63 according to 42*4882a593Smuzhiyun this table: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun 0: HCLKDMA0 45*4882a593Smuzhiyun 1: HCLKSMC 46*4882a593Smuzhiyun 2: HCLKSDRAM 47*4882a593Smuzhiyun 3: HCLKDMA1 48*4882a593Smuzhiyun 4: HCLKCLCD 49*4882a593Smuzhiyun 5: PCLKIRDA 50*4882a593Smuzhiyun 6: PCLKSSP 51*4882a593Smuzhiyun 7: PCLKUART0 52*4882a593Smuzhiyun 8: PCLKSDI 53*4882a593Smuzhiyun 9: PCLKI2C0 54*4882a593Smuzhiyun 10: PCLKI2C1 55*4882a593Smuzhiyun 11: PCLKUART1 56*4882a593Smuzhiyun 12: PCLMSP0 57*4882a593Smuzhiyun 13: HCLKUSB 58*4882a593Smuzhiyun 14: HCLKDIF 59*4882a593Smuzhiyun 15: HCLKSAA 60*4882a593Smuzhiyun 16: HCLKSVA 61*4882a593Smuzhiyun 17: PCLKHSI 62*4882a593Smuzhiyun 18: PCLKXTI 63*4882a593Smuzhiyun 19: PCLKUART2 64*4882a593Smuzhiyun 20: PCLKMSP1 65*4882a593Smuzhiyun 21: PCLKMSP2 66*4882a593Smuzhiyun 22: PCLKOWM 67*4882a593Smuzhiyun 23: HCLKHPI 68*4882a593Smuzhiyun 24: PCLKSKE 69*4882a593Smuzhiyun 25: PCLKHSEM 70*4882a593Smuzhiyun 26: HCLK3D 71*4882a593Smuzhiyun 27: HCLKHASH 72*4882a593Smuzhiyun 28: HCLKCRYP 73*4882a593Smuzhiyun 29: PCLKMSHC 74*4882a593Smuzhiyun 30: HCLKUSBM 75*4882a593Smuzhiyun 31: HCLKRNG 76*4882a593Smuzhiyun (32, 33, 34, 35 RESERVED) 77*4882a593Smuzhiyun 36: CLDCLK 78*4882a593Smuzhiyun 37: IRDACLK 79*4882a593Smuzhiyun 38: SSPICLK 80*4882a593Smuzhiyun 39: UART0CLK 81*4882a593Smuzhiyun 40: SDICLK 82*4882a593Smuzhiyun 41: I2C0CLK 83*4882a593Smuzhiyun 42: I2C1CLK 84*4882a593Smuzhiyun 43: UART1CLK 85*4882a593Smuzhiyun 44: MSPCLK0 86*4882a593Smuzhiyun 45: USBCLK 87*4882a593Smuzhiyun 46: DIFCLK 88*4882a593Smuzhiyun 47: IPI2CCLK 89*4882a593Smuzhiyun 48: IPBMCCLK 90*4882a593Smuzhiyun 49: HSICLKRX 91*4882a593Smuzhiyun 50: HSICLKTX 92*4882a593Smuzhiyun 51: UART2CLK 93*4882a593Smuzhiyun 52: MSPCLK1 94*4882a593Smuzhiyun 53: MSPCLK2 95*4882a593Smuzhiyun 54: OWMCLK 96*4882a593Smuzhiyun (55 RESERVED) 97*4882a593Smuzhiyun 56: SKECLK 98*4882a593Smuzhiyun (57 RESERVED) 99*4882a593Smuzhiyun 58: 3DCLK 100*4882a593Smuzhiyun 59: PCLKMSP3 101*4882a593Smuzhiyun 60: MSPCLK3 102*4882a593Smuzhiyun 61: MSHCCLK 103*4882a593Smuzhiyun 62: USBMCLK 104*4882a593Smuzhiyun 63: RNGCCLK 105