1*4882a593Smuzhiyun; General settings that can be overwritten in the host code 2*4882a593Smuzhiyun; that calls the AISGen library. 3*4882a593Smuzhiyun[General] 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun; Can be 8 or 16 - used in emifa 6*4882a593SmuzhiyunbusWidth=8 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW 9*4882a593SmuzhiyunBootMode=UART 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun; 8,16,24 - used for SPI,I2C 12*4882a593Smuzhiyun;AddrWidth=8 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun; NO_CRC,SECTION_CRC,SINGLE_CRC 15*4882a593SmuzhiyuncrcCheckType=NO_CRC 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun; This section allows setting the PLL0 system clock with a 18*4882a593Smuzhiyun; specified multiplier and divider as shown. The clock source 19*4882a593Smuzhiyun; can also be chosen for internal or external. 20*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 21*4882a593Smuzhiyun; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| 22*4882a593Smuzhiyun; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| 23*4882a593Smuzhiyun;[PLL0CONFIG] 24*4882a593Smuzhiyun;PLL0CFG0 = 0x00180001 25*4882a593Smuzhiyun;PLL0CFG1 = 0x00000205 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun[PLLANDCLOCKCONFIG] 28*4882a593SmuzhiyunPLL0CFG0 = 0x00180001 29*4882a593SmuzhiyunPLL0CFG1 = 0x00000205 30*4882a593SmuzhiyunPERIPHCLKCFG = 0x00000051 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun; This section allows setting up the PLL1. Usually this will 33*4882a593Smuzhiyun; take place as part of the EMIF3a DDR setup. The format of 34*4882a593Smuzhiyun; the input args is as follows: 35*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 36*4882a593Smuzhiyun; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| 37*4882a593Smuzhiyun; PLL1CFG1: | RSVD | PLLDIV3| 38*4882a593Smuzhiyun[PLL1CONFIG] 39*4882a593SmuzhiyunPLL1CFG0 = 0x18010001 40*4882a593SmuzhiyunPLL1CFG1 = 0x00000002 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun; This section lets us configure the peripheral interface 43*4882a593Smuzhiyun; of the current booting peripheral (I2C, SPI, or UART). 44*4882a593Smuzhiyun; Use with caution. The format of the PERIPHCLKCFG field 45*4882a593Smuzhiyun; is as follows: 46*4882a593Smuzhiyun; SPI: |------24|------16|-------8|-------0| 47*4882a593Smuzhiyun; | RSVD |PRESCALE| 48*4882a593Smuzhiyun; 49*4882a593Smuzhiyun; I2C: |------24|------16|-------8|-------0| 50*4882a593Smuzhiyun; | RSVD |PRESCALE| CLKL | CLKH | 51*4882a593Smuzhiyun; 52*4882a593Smuzhiyun; UART: |------24|------16|-------8|-------0| 53*4882a593Smuzhiyun; | RSVD | OSR | DLH | DLL | 54*4882a593Smuzhiyun[PERIPHCLKCFG] 55*4882a593SmuzhiyunPERIPHCLKCFG = 0x00000051 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun; This section can be used to configure the PLL1 and the EMIF3a registers 58*4882a593Smuzhiyun; for starting the DDR2 interface. 59*4882a593Smuzhiyun; See PLL1CONFIG section for the format of the PLL1CFG fields. 60*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 61*4882a593Smuzhiyun; PLL1CFG0: | PLL1CFG | 62*4882a593Smuzhiyun; PLL1CFG1: | PLL1CFG | 63*4882a593Smuzhiyun; DDRPHYC1R: | DDRPHYC1R | 64*4882a593Smuzhiyun; SDCR: | SDCR | 65*4882a593Smuzhiyun; SDTIMR: | SDTIMR | 66*4882a593Smuzhiyun; SDTIMR2: | SDTIMR2 | 67*4882a593Smuzhiyun; SDRCR: | SDRCR | 68*4882a593Smuzhiyun; CLK2XSRC: | CLK2XSRC | 69*4882a593Smuzhiyun[EMIF3DDR] 70*4882a593SmuzhiyunPLL1CFG0 = 0x18010001 71*4882a593SmuzhiyunPLL1CFG1 = 0x00000002 72*4882a593SmuzhiyunDDRPHYC1R = 0x000000C2 73*4882a593SmuzhiyunSDCR = 0x0017C432 74*4882a593SmuzhiyunSDTIMR = 0x26922A09 75*4882a593SmuzhiyunSDTIMR2 = 0x4414C722 76*4882a593SmuzhiyunSDRCR = 0x00000498 77*4882a593SmuzhiyunCLK2XSRC = 0x00000000 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun; This section can be used to configure the EMIFA to use 80*4882a593Smuzhiyun; CS0 as an SDRAM interface. The fields required to do this 81*4882a593Smuzhiyun; are given below. 82*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 83*4882a593Smuzhiyun; SDBCR: | SDBCR | 84*4882a593Smuzhiyun; SDTIMR: | SDTIMR | 85*4882a593Smuzhiyun; SDRSRPDEXIT: | SDRSRPDEXIT | 86*4882a593Smuzhiyun; SDRCR: | SDRCR | 87*4882a593Smuzhiyun; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | 88*4882a593Smuzhiyun;[EMIF25SDRAM] 89*4882a593Smuzhiyun;SDBCR = 0x00004421 90*4882a593Smuzhiyun;SDTIMR = 0x42215810 91*4882a593Smuzhiyun;SDRSRPDEXIT = 0x00000009 92*4882a593Smuzhiyun;SDRCR = 0x00000410 93*4882a593Smuzhiyun;DIV4p5_CLK_ENABLE = 0x00000001 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun; This section can be used to configure the async chip selects 96*4882a593Smuzhiyun; of the EMIFA (CS2-CS5). The fields required to do this 97*4882a593Smuzhiyun; are given below. 98*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 99*4882a593Smuzhiyun; A1CR: | A1CR | 100*4882a593Smuzhiyun; A2CR: | A2CR | 101*4882a593Smuzhiyun; A3CR: | A3CR | 102*4882a593Smuzhiyun; A4CR: | A4CR | 103*4882a593Smuzhiyun; NANDFCR: | NANDFCR | 104*4882a593Smuzhiyun;[EMIF25ASYNC] 105*4882a593Smuzhiyun;A1CR = 0x00000000 106*4882a593Smuzhiyun;A2CR = 0x00000000 107*4882a593Smuzhiyun;A3CR = 0x00000000 108*4882a593Smuzhiyun;A4CR = 0x00000000 109*4882a593Smuzhiyun;NANDFCR = 0x00000000 110*4882a593Smuzhiyun[EMIF25ASYNC] 111*4882a593SmuzhiyunA1CR = 0x00000000 112*4882a593SmuzhiyunA2CR = 0x04202110 113*4882a593SmuzhiyunA3CR = 0x00000000 114*4882a593SmuzhiyunA4CR = 0x00000000 115*4882a593SmuzhiyunNANDFCR = 0x00000012 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun; This section should be used in place of PLL0CONFIG when 118*4882a593Smuzhiyun; the I2C, SPI, or UART modes are being used. This ensures that 119*4882a593Smuzhiyun; the system PLL and the peripheral's clocks are changed together. 120*4882a593Smuzhiyun; See PLL0CONFIG section for the format of the PLL0CFG fields. 121*4882a593Smuzhiyun; See PERIPHCLKCFG section for the format of the CLKCFG field. 122*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 123*4882a593Smuzhiyun; PLL0CFG0: | PLL0CFG | 124*4882a593Smuzhiyun; PLL0CFG1: | PLL0CFG | 125*4882a593Smuzhiyun; PERIPHCLKCFG: | CLKCFG | 126*4882a593Smuzhiyun;[PLLANDCLOCKCONFIG] 127*4882a593Smuzhiyun;PLL0CFG0 = 0x00180001 128*4882a593Smuzhiyun;PLL0CFG1 = 0x00000205 129*4882a593Smuzhiyun;PERIPHCLKCFG = 0x00010032 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun; This section should be used to setup the power state of modules 132*4882a593Smuzhiyun; of the two PSCs. This section can be included multiple times to 133*4882a593Smuzhiyun; allow the configuration of any or all of the device modules. 134*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 135*4882a593Smuzhiyun; LPSCCFG: | PSCNUM | MODULE | PD | STATE | 136*4882a593Smuzhiyun;[PSCCONFIG] 137*4882a593Smuzhiyun;LPSCCFG= 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun; This section allows setting of a single PINMUX register. 140*4882a593Smuzhiyun; This section can be included multiple times to allow setting 141*4882a593Smuzhiyun; as many PINMUX registers as needed. 142*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 143*4882a593Smuzhiyun; REGNUM: | regNum | 144*4882a593Smuzhiyun; MASK: | mask | 145*4882a593Smuzhiyun; VALUE: | value | 146*4882a593Smuzhiyun;[PINMUX] 147*4882a593Smuzhiyun;REGNUM = 5 148*4882a593Smuzhiyun;MASK = 0x00FF0000 149*4882a593Smuzhiyun;VALUE = 0x00880000 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun; No Params required - simply include this section for the fast boot 152*4882a593Smuzhiyun; function to be called 153*4882a593Smuzhiyun;[FASTBOOT] 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun; This section allows setting up the PLL1. Usually this will 156*4882a593Smuzhiyun; take place as part of the EMIF3a DDR setup. The format of 157*4882a593Smuzhiyun; the input args is as follows: 158*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 159*4882a593Smuzhiyun; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| 160*4882a593Smuzhiyun; PLL1CFG1: | RSVD | PLLDIV3| 161*4882a593Smuzhiyun;[PLL1CONFIG] 162*4882a593Smuzhiyun;PLL1CFG0 = 0x15010001 163*4882a593Smuzhiyun;PLL1CFG1 = 0x00000002 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun; This section can be used to configure the PLL1 and the EMIF3a registers 166*4882a593Smuzhiyun; for starting the DDR2 interface on ARM-boot D800K002 devices. 167*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 168*4882a593Smuzhiyun; DDRPHYC1R: | DDRPHYC1R | 169*4882a593Smuzhiyun; SDCR: | SDCR | 170*4882a593Smuzhiyun; SDTIMR: | SDTIMR | 171*4882a593Smuzhiyun; SDTIMR2: | SDTIMR2 | 172*4882a593Smuzhiyun; SDRCR: | SDRCR | 173*4882a593Smuzhiyun; CLK2XSRC: | CLK2XSRC | 174*4882a593Smuzhiyun;[ARM_EMIF3DDR_PATCHFXN] 175*4882a593Smuzhiyun;DDRPHYC1R = 0x000000C2 176*4882a593Smuzhiyun;SDCR = 0x0017C432 177*4882a593Smuzhiyun;SDTIMR = 0x26922A09 178*4882a593Smuzhiyun;SDTIMR2 = 0x4414C722 179*4882a593Smuzhiyun;SDRCR = 0x00000498 180*4882a593Smuzhiyun;CLK2XSRC = 0x00000000 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun; This section can be used to configure the PLL1 and the EMIF3a registers 183*4882a593Smuzhiyun; for starting the DDR2 interface on DSP-boot D800K002 devices. 184*4882a593Smuzhiyun; |------24|------16|-------8|-------0| 185*4882a593Smuzhiyun; DDRPHYC1R: | DDRPHYC1R | 186*4882a593Smuzhiyun; SDCR: | SDCR | 187*4882a593Smuzhiyun; SDTIMR: | SDTIMR | 188*4882a593Smuzhiyun; SDTIMR2: | SDTIMR2 | 189*4882a593Smuzhiyun; SDRCR: | SDRCR | 190*4882a593Smuzhiyun; CLK2XSRC: | CLK2XSRC | 191*4882a593Smuzhiyun;[DSP_EMIF3DDR_PATCHFXN] 192*4882a593Smuzhiyun;DDRPHYC1R = 0x000000C4 193*4882a593Smuzhiyun;SDCR = 0x08134632 194*4882a593Smuzhiyun;SDTIMR = 0x26922A09 195*4882a593Smuzhiyun;SDTIMR2 = 0x0014C722 196*4882a593Smuzhiyun;SDRCR = 0x00000492 197*4882a593Smuzhiyun;CLK2XSRC = 0x00000000 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun;[INPUTFILE] 200*4882a593Smuzhiyun;FILENAME=u-boot.bin 201*4882a593Smuzhiyun;LOADADDRESS=0xC1080000 202*4882a593Smuzhiyun;ENTRYPOINTADDRESS=0xC1080000 203