1*4882a593SmuzhiyunDSP side awareness for Freescale heterogeneous multicore chips based on 2*4882a593SmuzhiyunStarCore and Power Architecture 3*4882a593Smuzhiyun=============================================================== 4*4882a593Smuzhiyunpowerpc/mpc85xx code ve APIs and function to get the number, 5*4882a593Smuzhiyunconfiguration and frequencies of all PowerPC cores and devices 6*4882a593Smuzhiyunconnected to them, but it didnt have the similar code ofr HEterogeneous 7*4882a593SmuzhiyunSC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunCode for DSP side awareness provides such functionality for Freescale 10*4882a593SmuzhiyunHeterogeneous SoCs which are chasis-2 compliant like B4860 and B4420 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunAs part of this feature, following changes have been made: 13*4882a593Smuzhiyun========================================================== 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun1. Changed files: 16*4882a593Smuzhiyun================= 17*4882a593Smuzhiyun- arch/powerpc/cpu/mpc85xx/cpu.c 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunCode added in this file to print the DSP cores and other device's(CPRI, 20*4882a593SmuzhiyunMAPLE etc) frequencies 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- arch/powerpc/cpu/mpc85xx/speed.c 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunAdded Defines and code to extract the frequncy information for all 25*4882a593Smuzhiyunrequired cores and devices from RCW and System frequency 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- arch/powerpc/cpu/mpc8xxx/cpu.c 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunAdded API to get the number of SC cores in running system and Their BIT 30*4882a593SmuzhiyunMASK, similar to the code written for PowerPC 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- arch/powerpc/include/asm/config_mpc85xx.h 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunAdded top level CONFIG to identify presence of HETEROGENUOUS clusters 35*4882a593Smuzhiyunin the system and CONFIGS for SC3900/DSP components 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun- arch/powerpc/include/asm/processor.h 38*4882a593Smuzhiyun- include/common.h 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunAdded newly added Functions Declaration 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- include/e500.h 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunGlobal structure updated for dsp cores and other components 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun2. CONFIGs ADDED 47*4882a593Smuzhiyun================ 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunCONFIG_HETROGENOUS_CLUSTERS - Define for checking the presence of 50*4882a593Smuzhiyun DSP/SC3900 core clusters 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunCONFIG_SYS_FSL_NUM_CC_PLLS - Define for number of PLLs 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunThough there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 - 55*4882a593SmuzhiyunPLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the 56*4882a593Smuzhiyunvalue as 5 not 4, to iterate over all PLLs while coding 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunCONFIG_SYS_MAPLE - Define for MAPLE Baseband Accelerator 59*4882a593SmuzhiyunCONFIG_SYS_CPRI - Define for CPRI Interface 60*4882a593SmuzhiyunCONFIG_PPC_CLUSTER_START - Start index of ppc clusters 61*4882a593SmuzhiyunCONFIG_DSP_CLUSTER_START - Start index of dsp clusters 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunFollowing are the defines for PLL's index that provide the Clocking to 64*4882a593SmuzhiyunCPRI, ULB and ETVE components 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunCONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock 67*4882a593SmuzhiyunCONFIG_SYS_ULB_CLK - Define PLL index for ULB clock 68*4882a593SmuzhiyunCONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun3. Changes in MPC85xx_SYS_INFO Global structure 71*4882a593Smuzhiyun=============================================== 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunDSP cores and other device's components have been added in this structure. 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunfreq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies 76*4882a593Smuzhiyunfreq_cpri - To store CPRI frequency 77*4882a593Smuzhiyunfreq_maple - To store MAPLE frequency 78*4882a593Smuzhiyunfreq_maple_ulb - To store MAPLE-ULB frequency 79*4882a593Smuzhiyunfreq_maple_etvpe - To store MAPLE-eTVPE frequency 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun4. U-BOOT LOGS 82*4882a593Smuzhiyun============== 83*4882a593Smuzhiyun4.1 B4860QDS board 84*4882a593Smuzhiyun Boot from NOR flash 85*4882a593Smuzhiyun 86*4882a593SmuzhiyunU-Boot 2014.07-00222-g70587a8-dirty (Aug 07 2014 - 13:15:47) 87*4882a593Smuzhiyun 88*4882a593SmuzhiyunCPU0: B4860E, Version: 2.0, (0x86880020) 89*4882a593SmuzhiyunCore: e6500, Version: 2.0, (0x80400020) Clock Configuration: 90*4882a593Smuzhiyun CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, 91*4882a593Smuzhiyun DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, 92*4882a593Smuzhiyun DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, 93*4882a593Smuzhiyun CCB:666.667 MHz, 94*4882a593Smuzhiyun DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz 95*4882a593Smuzhiyun CPRI:600 MHz 96*4882a593Smuzhiyun MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz 97*4882a593Smuzhiyun FMAN1: 666.667 MHz 98*4882a593Smuzhiyun QMAN: 333.333 MHz 99*4882a593Smuzhiyun 100*4882a593SmuzhiyunCPUn - PowerPC core 101*4882a593SmuzhiyunDSP CPUn - SC3900 core 102*4882a593Smuzhiyun 103*4882a593SmuzhiyunShaveta Leekha(shaveta@freescale.com) 104*4882a593SmuzhiyunCreated August 7, 2014 105*4882a593Smuzhiyun=========================================== 106