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Searched refs:HIWORD_UPDATE (Results 1 – 25 of 68) sorted by relevance

123

/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Drk618.h23 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
26 #define LVDS_CON_START_PHASE(x) HIWORD_UPDATE(x, 14, 14)
27 #define LVDS_DCLK_INV HIWORD_UPDATE(1, 13, 13)
28 #define LVDS_CON_CHADS_10PF HIWORD_UPDATE(3, 12, 11)
29 #define LVDS_CON_CHADS_5PF HIWORD_UPDATE(2, 12, 11)
30 #define LVDS_CON_CHADS_7PF HIWORD_UPDATE(1, 12, 11)
31 #define LVDS_CON_CHADS_3PF HIWORD_UPDATE(0, 12, 11)
32 #define LVDS_CON_CHA1TTL_ENABLE HIWORD_UPDATE(1, 10, 10)
33 #define LVDS_CON_CHA1TTL_DISABLE HIWORD_UPDATE(0, 10, 10)
34 #define LVDS_CON_CHA0TTL_ENABLE HIWORD_UPDATE(1, 9, 9)
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H A Drk630.h18 #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16)) macro
23 #define GPIO0A0_SEL(x) HIWORD_UPDATE(x, 1, 0)
25 #define GPIO0A1_SEL(x) HIWORD_UPDATE(x, 3, 2)
27 #define GPIO0A2_SEL(x) HIWORD_UPDATE(x, 5, 4)
29 #define GPIO0A3_SEL(x) HIWORD_UPDATE(x, 7, 6)
31 #define GPIO0A4_SEL(x) HIWORD_UPDATE(x, 9, 8)
33 #define GPIO0A5_SEL(x) HIWORD_UPDATE(x, 11, 10)
35 #define GPIO0A6_SEL(x) HIWORD_UPDATE(x, 13, 12)
37 #define GPIO0A7_SEL(x) HIWORD_UPDATE(x, 15, 14)
40 #define GPIO0B0_SEL(x) HIWORD_UPDATE(x, 1, 0)
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H A Drk628.h20 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
51 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
52 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
53 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
54 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
55 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
56 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
92 #define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8)
93 #define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4)
94 #define SW_Y2R_EN(x) HIWORD_UPDATE(x, 0, 0)
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/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drk618.h15 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
18 #define FRC_DEN_INV HIWORD_UPDATE(1, 6, 6)
19 #define FRC_SYNC_INV HIWORD_UPDATE(1, 5, 5)
20 #define FRC_DCLK_INV HIWORD_UPDATE(1, 4, 4)
21 #define FRC_OUT_ZERO HIWORD_UPDATE(1, 3, 3)
22 #define FRC_OUT_MODE_RGB666 HIWORD_UPDATE(1, 2, 2)
23 #define FRC_OUT_MODE_RGB888 HIWORD_UPDATE(0, 2, 2)
24 #define FRC_DITHER_MODE_HI_FRC HIWORD_UPDATE(1, 1, 1)
25 #define FRC_DITHER_MODE_FRC HIWORD_UPDATE(0, 1, 1)
26 #define FRC_DITHER_ENABLE HIWORD_UPDATE(1, 0, 0)
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H A Drockchip_lvds.c25 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
28 #define PX30_LVDS_SELECT(x) HIWORD_UPDATE(x, 14, 13)
29 #define PX30_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 12, 12)
30 #define PX30_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 11, 11)
31 #define PX30_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 6, 6)
32 #define PX30_LVDS_VOP_SEL(x) HIWORD_UPDATE(x, 1, 1)
35 #define RK3126_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 9, 9)
36 #define RK3126_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 6, 6)
37 #define RK3126_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 3, 3)
38 #define RK3126_LVDS_SELECT(x) HIWORD_UPDATE(x, 2, 1)
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H A Drockchip_dw_hdmi_qp.c28 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) macro
1105 val = HIWORD_UPDATE(0, RK3588_HDMI21_MASK); in rk3588_set_link_mode()
1111 val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); in rk3588_set_link_mode()
1120 val = HIWORD_UPDATE(RK3588_HDMI21_MASK, RK3588_HDMI21_MASK); in rk3588_set_link_mode()
1127 val = HIWORD_UPDATE(RK3588_COMPRESS_MODE_MASK | RK3588_COMPRESSED_DATA, in rk3588_set_link_mode()
1134 val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); in rk3588_set_link_mode()
1150 val = HIWORD_UPDATE(0, RK3588_COLOR_FORMAT_MASK); in rk3588_set_color_format()
1154 val = HIWORD_UPDATE(RK3588_YUV420, RK3588_COLOR_FORMAT_MASK); in rk3588_set_color_format()
1158 val = HIWORD_UPDATE(RK3588_YUV444, RK3588_COLOR_FORMAT_MASK); in rk3588_set_color_format()
1162 val = HIWORD_UPDATE(RK3588_YUV422, RK3588_COLOR_FORMAT_MASK); in rk3588_set_color_format()
[all …]
H A Drockchip_rgb.c25 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
28 #define PX30_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
29 #define PX30_RGB_VOP_SEL(v) HIWORD_UPDATE(v, 2, 2)
32 #define RK1808_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
35 #define RV1106_IO_BYPASS_SEL(v) HIWORD_UPDATE(v, 0, 1)
37 #define RV1106_VOP_PIPE_BYPASS(v) HIWORD_UPDATE(v, 0, 1)
40 #define RV1126_LCDC_IO_BYPASS(v) HIWORD_UPDATE(v, 0, 0)
43 #define RK3288_LVDS_LCDC_SEL(v) HIWORD_UPDATE(v, 3, 3)
45 #define RK3288_LVDS_PWRDWN(v) HIWORD_UPDATE(v, 15, 15)
46 #define RK3288_LVDS_CON_ENABLE_2(v) HIWORD_UPDATE(v, 12, 12)
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/OK3568_Linux_fs/kernel/sound/soc/rockchip/
H A Drockchip_i2s_tdm.h321 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
324 #define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12)
325 #define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12)
326 #define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)
327 #define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)
336 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
337 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
338 #define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0)
339 #define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0)
348 #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 10, 10)
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H A Drockchip_audio_pwm.h26 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
29 #define AUDPWM_XFER_LSTOP HIWORD_UPDATE(1, 1, 1)
30 #define AUDPWM_XFER_START HIWORD_UPDATE(1, 0, 0)
31 #define AUDPWM_XFER_STOP HIWORD_UPDATE(0, 0, 0)
34 #define AUDPWM_ALIGN_LEFT HIWORD_UPDATE(1, 5, 5)
35 #define AUDPWM_ALIGN_RIGHT HIWORD_UPDATE(0, 5, 5)
36 #define AUDPWM_SRC_WIDTH(x) HIWORD_UPDATE((x) - 1, 4, 0)
39 #define AUDPWM_SAMPLE_WIDTH(x) HIWORD_UPDATE((x) - 8, 9, 8)
40 #define AUDPWM_LINEAR_INTERP_EN HIWORD_UPDATE(1, 4, 4)
41 #define AUDPWM_INTERP_RATE(x) HIWORD_UPDATE((x), 3, 0)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628.h18 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
49 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
50 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
51 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
52 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
53 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
54 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
90 #define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8)
91 #define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4)
92 #define SW_Y2R_EN(x) HIWORD_UPDATE(x, 0, 0)
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H A Drk628_cru.h17 #define PLL_BYPASS(x) HIWORD_UPDATE(x, 15, 15)
20 #define PLL_POSTDIV1(x) HIWORD_UPDATE(x, 14, 12)
23 #define PLL_FBDIV(x) HIWORD_UPDATE(x, 11, 0)
27 #define PLL_PD(x) HIWORD_UPDATE(x, 13, 13)
29 #define PLL_DSMPD(x) HIWORD_UPDATE(x, 12, 12)
33 #define PLL_POSTDIV2(x) HIWORD_UPDATE(x, 8, 6)
36 #define PLL_REFDIV(x) HIWORD_UPDATE(x, 5, 0)
74 #define SCLK_UART_SEL(x) HIWORD_UPDATE(x, 15, 14)
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk618/
H A Drk618_dither.c12 #define FRC_DEN_INV HIWORD_UPDATE(1, 6, 6)
13 #define FRC_SYNC_INV HIWORD_UPDATE(1, 5, 5)
14 #define FRC_DCLK_INV HIWORD_UPDATE(1, 4, 4)
15 #define FRC_OUT_ZERO HIWORD_UPDATE(1, 3, 3)
16 #define FRC_OUT_MODE_RGB666 HIWORD_UPDATE(1, 2, 2)
17 #define FRC_OUT_MODE_RGB888 HIWORD_UPDATE(0, 2, 2)
18 #define FRC_DITHER_MODE_HI_FRC HIWORD_UPDATE(1, 1, 1)
19 #define FRC_DITHER_MODE_FRC HIWORD_UPDATE(0, 1, 1)
20 #define FRC_DITHER_ENABLE HIWORD_UPDATE(1, 0, 0)
21 #define FRC_DITHER_DISABLE HIWORD_UPDATE(0, 0, 0)
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_lvds.c27 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
30 #define PX30_LVDS_SELECT(x) HIWORD_UPDATE(x, 14, 13)
31 #define PX30_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 12, 12)
32 #define PX30_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 11, 11)
33 #define PX30_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 6, 6)
34 #define PX30_LVDS_VOP_SEL(x) HIWORD_UPDATE(x, 1, 1)
37 #define RK3126_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 9, 9)
38 #define RK3126_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 6, 6)
39 #define RK3126_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 3, 3)
40 #define RK3126_LVDS_SELECT(x) HIWORD_UPDATE(x, 2, 1)
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H A Drockchip_lvds.h109 #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) macro
112 #define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8)
113 #define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9)
114 #define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5)
117 #define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13)
118 #define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12)
119 #define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11)
120 #define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6)
121 #define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1)
H A Ddw_hdmi-rockchip.c31 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
1247 val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, in rockchip_hdmi_hardirq()
1250 val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, in rockchip_hdmi_hardirq()
1272 val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, in rockchip_hdmi_irq()
1279 val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, in rockchip_hdmi_irq()
1299 val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, in rockchip_hdmi_irq()
1301 HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); in rockchip_hdmi_irq()
1303 val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, in rockchip_hdmi_irq()
1305 HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK); in rockchip_hdmi_irq()
1326 val = HIWORD_UPDATE(RK3528_HDMI_SNKDET, RK3528_HDMI_SNKDET); in rockchip_hdmi_hpd_irq_handler()
[all …]
H A Ddw-mipi-dsi-rockchip.c198 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
1280 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1281 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1285 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1300 .lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
1315 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1316 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1325 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1326 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1339 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
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/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628.h23 #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | \ macro
55 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
56 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
57 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
58 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
59 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
60 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
96 #define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8)
97 #define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4)
98 #define SW_Y2R_EN(x) HIWORD_UPDATE(x, 0, 0)
[all …]
H A Drk628_cru.h17 #define PLL_BYPASS(x) HIWORD_UPDATE(x, 15, 15)
20 #define PLL_POSTDIV1(x) HIWORD_UPDATE(x, 14, 12)
23 #define PLL_FBDIV(x) HIWORD_UPDATE(x, 11, 0)
27 #define PLL_PD(x) HIWORD_UPDATE(x, 13, 13)
29 #define PLL_DSMPD(x) HIWORD_UPDATE(x, 12, 12)
33 #define PLL_POSTDIV2(x) HIWORD_UPDATE(x, 8, 6)
36 #define PLL_REFDIV(x) HIWORD_UPDATE(x, 5, 0)
73 #define CLK_BT1120DEC_DIV(x) HIWORD_UPDATE(x, 4, 0)
78 #define SCLK_UART_SEL(x) HIWORD_UPDATE(x, 15, 14)
/OK3568_Linux_fs/kernel/drivers/soc/rockchip/
H A Dgrf.c107 #define HIWORD_UPDATE(val, mask, shift) \ macro
143 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
154 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
165 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
177 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
178 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
189 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
201 { "uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10) },
202 { "uart2 auto switching", RK3308_GRF_SOC_CON13, HIWORD_UPDATE(0, 0x1, 12) },
213 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-pll.c590 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
592 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
596 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
598 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
600 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
653 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_enable()
670 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, in rockchip_rk3036_pll_disable()
837 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
841 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
843 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_params()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c23 #define HIWORD_UPDATE(val, mask, shift) \ macro
100 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, in rockchip_emmc_phy_power()
105 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, in rockchip_emmc_phy_power()
158 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, in rockchip_emmc_phy_power()
181 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, in rockchip_emmc_phy_power()
187 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, in rockchip_emmc_phy_power()
282 HIWORD_UPDATE(rk_phy->drive_impedance, in rockchip_emmc_phy_power_on()
289 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, in rockchip_emmc_phy_power_on()
296 HIWORD_UPDATE(4, in rockchip_emmc_phy_power_on()
H A Dphy-rockchip-pcie.c26 #define HIWORD_UPDATE(val, mask, shift) \ macro
104 HIWORD_UPDATE(data, in phy_wr_cfg()
107 HIWORD_UPDATE(addr, in phy_wr_cfg()
112 HIWORD_UPDATE(PHY_CFG_WR_ENABLE, in phy_wr_cfg()
117 HIWORD_UPDATE(PHY_CFG_WR_DISABLE, in phy_wr_cfg()
128 HIWORD_UPDATE(addr, in phy_rd_cfg()
147 HIWORD_UPDATE(PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
168 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
187 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_on()
201 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, in rockchip_pcie_phy_power_on()
[all …]
H A Dphy-rockchip-usb.c34 #define HIWORD_UPDATE(val, mask) \ macro
220 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_HOST, in otg_mode_store()
224 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL, in otg_mode_store()
228 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_OTG, in otg_mode_store()
259 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); in rockchip_usb_phy_power()
325 val = HIWORD_UPDATE(RK3288_UOC0_CON4_BVALID_IRQ_EN in rk3288_usb_phy_init()
567 val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL, in rk3288_chg_detect_work()
570 val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING, in rk3288_chg_detect_work()
575 val = HIWORD_UPDATE(RK3288_UOC0_CON2_DCDENB, in rk3288_chg_detect_work()
593 val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_DCDENB); in rk3288_chg_detect_work()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-pll.c19 #define PLL_BYPASS(x) HIWORD_UPDATE(x, 15, 15)
22 #define PLL_POSTDIV1(x) HIWORD_UPDATE(x, 14, 12)
25 #define PLL_FBDIV(x) HIWORD_UPDATE(x, 11, 0)
29 #define PLL_POSTDIV2(x) HIWORD_UPDATE(x, 8, 6)
32 #define PLL_REFDIV(x) HIWORD_UPDATE(x, 5, 0)
274 HIWORD_UPDATE(dsmpd, pll->dsmpd_shift, pll->dsmpd_shift) | in clk_regmap_pll_set_rate()
295 HIWORD_UPDATE(0, pll->pd_shift, pll->pd_shift)); in clk_regmap_pll_prepare()
311 HIWORD_UPDATE(1, pll->pd_shift, pll->pd_shift)); in clk_regmap_pll_unprepare()
/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpcie-rockchip.h21 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
22 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
34 #define PCIE_CLIENT_LINK_TRAIN_DISABLE HIWORD_UPDATE(0x0002, 0x0000)
36 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
38 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
39 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)

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