xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rockchip_lvds.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4*4882a593Smuzhiyun  * Author:
5*4882a593Smuzhiyun  *      Mark Yao <mark.yao@rock-chips.com>
6*4882a593Smuzhiyun  *      Sandy Huang <hjc@rock-chips.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/component.h>
10*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
11*4882a593Smuzhiyun #include <linux/of_graph.h>
12*4882a593Smuzhiyun #include <linux/phy/phy.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
16*4882a593Smuzhiyun #include <drm/drm_bridge.h>
17*4882a593Smuzhiyun #include <drm/drm_of.h>
18*4882a593Smuzhiyun #include <drm/drm_panel.h>
19*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
20*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <uapi/linux/videodev2.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include "rockchip_drm_drv.h"
25*4882a593Smuzhiyun #include "rockchip_drm_vop.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define HIWORD_UPDATE(v, h, l)  (((v) << (l)) | (GENMASK(h, l) << 16))
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define PX30_GRF_PD_VO_CON1		0x0438
30*4882a593Smuzhiyun #define PX30_LVDS_SELECT(x)		HIWORD_UPDATE(x, 14, 13)
31*4882a593Smuzhiyun #define PX30_LVDS_MODE_EN(x)		HIWORD_UPDATE(x, 12, 12)
32*4882a593Smuzhiyun #define PX30_LVDS_MSBSEL(x)		HIWORD_UPDATE(x, 11, 11)
33*4882a593Smuzhiyun #define PX30_LVDS_P2S_EN(x)		HIWORD_UPDATE(x,  6,  6)
34*4882a593Smuzhiyun #define PX30_LVDS_VOP_SEL(x)		HIWORD_UPDATE(x,  1,  1)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define RK3126_GRF_LVDS_CON0		0x0150
37*4882a593Smuzhiyun #define RK3126_LVDS_P2S_EN(x)		HIWORD_UPDATE(x,  9,  9)
38*4882a593Smuzhiyun #define RK3126_LVDS_MODE_EN(x)		HIWORD_UPDATE(x,  6,  6)
39*4882a593Smuzhiyun #define RK3126_LVDS_MSBSEL(x)		HIWORD_UPDATE(x,  3,  3)
40*4882a593Smuzhiyun #define RK3126_LVDS_SELECT(x)		HIWORD_UPDATE(x,  2,  1)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON6		0x025c
43*4882a593Smuzhiyun #define RK3288_LVDS_LCDC_SEL(x)		HIWORD_UPDATE(x,  3,  3)
44*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON7		0x0260
45*4882a593Smuzhiyun #define RK3288_LVDS_PWRDWN(x)		HIWORD_UPDATE(x, 15, 15)
46*4882a593Smuzhiyun #define RK3288_LVDS_CON_ENABLE_2(x)	HIWORD_UPDATE(x, 12, 12)
47*4882a593Smuzhiyun #define RK3288_LVDS_CON_ENABLE_1(x)	HIWORD_UPDATE(x, 11, 11)
48*4882a593Smuzhiyun #define RK3288_LVDS_CON_DEN_POL(x)	HIWORD_UPDATE(x, 10, 10)
49*4882a593Smuzhiyun #define RK3288_LVDS_CON_HS_POL(x)	HIWORD_UPDATE(x,  9,  9)
50*4882a593Smuzhiyun #define RK3288_LVDS_CON_CLKINV(x)	HIWORD_UPDATE(x,  8,  8)
51*4882a593Smuzhiyun #define RK3288_LVDS_CON_STARTPHASE(x)	HIWORD_UPDATE(x,  7,  7)
52*4882a593Smuzhiyun #define RK3288_LVDS_CON_TTL_EN(x)	HIWORD_UPDATE(x,  6,  6)
53*4882a593Smuzhiyun #define RK3288_LVDS_CON_STARTSEL(x)	HIWORD_UPDATE(x,  5,  5)
54*4882a593Smuzhiyun #define RK3288_LVDS_CON_CHASEL(x)	HIWORD_UPDATE(x,  4,  4)
55*4882a593Smuzhiyun #define RK3288_LVDS_CON_MSBSEL(x)	HIWORD_UPDATE(x,  3,  3)
56*4882a593Smuzhiyun #define RK3288_LVDS_CON_SELECT(x)	HIWORD_UPDATE(x,  2,  0)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define RK3368_GRF_SOC_CON7		0x041c
59*4882a593Smuzhiyun #define RK3368_LVDS_SELECT(x)		HIWORD_UPDATE(x, 14, 13)
60*4882a593Smuzhiyun #define RK3368_LVDS_MODE_EN(x)		HIWORD_UPDATE(x, 12, 12)
61*4882a593Smuzhiyun #define RK3368_LVDS_MSBSEL(x)		HIWORD_UPDATE(x, 11, 11)
62*4882a593Smuzhiyun #define RK3368_LVDS_P2S_EN(x)		HIWORD_UPDATE(x,  6,  6)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define RK3562_GRF_VO_CON0		0x05d0
65*4882a593Smuzhiyun #define RK3562_GRF_VO_CON1		0x05d4
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define RK3568_GRF_VO_CON0		0x0360
68*4882a593Smuzhiyun #define RK3568_LVDS1_SELECT(x)		HIWORD_UPDATE(x, 13, 12)
69*4882a593Smuzhiyun #define RK3568_LVDS1_MSBSEL(x)		HIWORD_UPDATE(x, 11, 11)
70*4882a593Smuzhiyun #define RK3568_LVDS0_SELECT(x)		HIWORD_UPDATE(x,  5,  4)
71*4882a593Smuzhiyun #define RK3568_LVDS0_MSBSEL(x)		HIWORD_UPDATE(x,  3,  3)
72*4882a593Smuzhiyun #define RK3568_GRF_VO_CON2		0x0368
73*4882a593Smuzhiyun #define RK3568_LVDS0_DCLK_INV_SEL(x)	HIWORD_UPDATE(x,  9,  9)
74*4882a593Smuzhiyun #define RK3568_LVDS0_DCLK_DIV2_SEL(x)	HIWORD_UPDATE(x,  8,  8)
75*4882a593Smuzhiyun #define RK3568_LVDS0_MODE_EN(x)		HIWORD_UPDATE(x,  1,  1)
76*4882a593Smuzhiyun #define RK3568_LVDS0_P2S_EN(x)		HIWORD_UPDATE(x,  0,  0)
77*4882a593Smuzhiyun #define RK3568_GRF_VO_CON3		0x036c
78*4882a593Smuzhiyun #define RK3568_LVDS1_DCLK_INV_SEL(x)	HIWORD_UPDATE(x,  9,  9)
79*4882a593Smuzhiyun #define RK3568_LVDS1_DCLK_DIV2_SEL(x)	HIWORD_UPDATE(x,  8,  8)
80*4882a593Smuzhiyun #define RK3568_LVDS1_MODE_EN(x)		HIWORD_UPDATE(x,  1,  1)
81*4882a593Smuzhiyun #define RK3568_LVDS1_P2S_EN(x)		HIWORD_UPDATE(x,  0,  0)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun enum lvds_format {
84*4882a593Smuzhiyun 	LVDS_8BIT_MODE_FORMAT_1,
85*4882a593Smuzhiyun 	LVDS_8BIT_MODE_FORMAT_2,
86*4882a593Smuzhiyun 	LVDS_6BIT_MODE_FORMAT_1,
87*4882a593Smuzhiyun 	LVDS_6BIT_MODE_FORMAT_2,
88*4882a593Smuzhiyun 	LVDS_10BIT_MODE_FORMAT_1,
89*4882a593Smuzhiyun 	LVDS_10BIT_MODE_FORMAT_2,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun struct rockchip_lvds;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun struct rockchip_lvds_funcs {
95*4882a593Smuzhiyun 	int (*probe)(struct rockchip_lvds *lvds);
96*4882a593Smuzhiyun 	void (*enable)(struct rockchip_lvds *lvds);
97*4882a593Smuzhiyun 	void (*disable)(struct rockchip_lvds *lvds);
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun struct rockchip_lvds {
101*4882a593Smuzhiyun 	int id;
102*4882a593Smuzhiyun 	struct device *dev;
103*4882a593Smuzhiyun 	struct phy *phy;
104*4882a593Smuzhiyun 	struct regmap *grf;
105*4882a593Smuzhiyun 	const struct rockchip_lvds_funcs *funcs;
106*4882a593Smuzhiyun 	enum lvds_format format;
107*4882a593Smuzhiyun 	bool data_swap;
108*4882a593Smuzhiyun 	bool dual_channel;
109*4882a593Smuzhiyun 	bool phy_enabled;
110*4882a593Smuzhiyun 	enum drm_lvds_dual_link_pixels pixel_order;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	struct rockchip_lvds *primary;
113*4882a593Smuzhiyun 	struct rockchip_lvds *secondary;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	struct drm_panel *panel;
116*4882a593Smuzhiyun 	struct drm_bridge *bridge;
117*4882a593Smuzhiyun 	struct drm_connector connector;
118*4882a593Smuzhiyun 	struct drm_encoder encoder;
119*4882a593Smuzhiyun 	struct drm_display_mode mode;
120*4882a593Smuzhiyun 	struct rockchip_drm_sub_dev sub_dev;
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun 
connector_to_lvds(struct drm_connector * c)123*4882a593Smuzhiyun static inline struct rockchip_lvds *connector_to_lvds(struct drm_connector *c)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	return container_of(c, struct rockchip_lvds, connector);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun 
encoder_to_lvds(struct drm_encoder * e)128*4882a593Smuzhiyun static inline struct rockchip_lvds *encoder_to_lvds(struct drm_encoder *e)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	return container_of(e, struct rockchip_lvds, encoder);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static int
rockchip_lvds_atomic_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)134*4882a593Smuzhiyun rockchip_lvds_atomic_connector_get_property(struct drm_connector *connector,
135*4882a593Smuzhiyun 					    const struct drm_connector_state *state,
136*4882a593Smuzhiyun 					    struct drm_property *property,
137*4882a593Smuzhiyun 					    uint64_t *val)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = connector_to_lvds(connector);
140*4882a593Smuzhiyun 	struct rockchip_drm_private *private = connector->dev->dev_private;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	if (property == private->connector_id_prop) {
143*4882a593Smuzhiyun 		*val = lvds->id;
144*4882a593Smuzhiyun 		return 0;
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	DRM_ERROR("failed to get rockchip LVDS property\n");
148*4882a593Smuzhiyun 	return -EINVAL;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun static const struct drm_connector_funcs rockchip_lvds_connector_funcs = {
152*4882a593Smuzhiyun 	.fill_modes = drm_helper_probe_single_connector_modes,
153*4882a593Smuzhiyun 	.destroy = drm_connector_cleanup,
154*4882a593Smuzhiyun 	.reset = drm_atomic_helper_connector_reset,
155*4882a593Smuzhiyun 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
156*4882a593Smuzhiyun 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
157*4882a593Smuzhiyun 	.atomic_get_property = rockchip_lvds_atomic_connector_get_property,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
rockchip_lvds_connector_get_modes(struct drm_connector * connector)160*4882a593Smuzhiyun static int rockchip_lvds_connector_get_modes(struct drm_connector *connector)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = connector_to_lvds(connector);
163*4882a593Smuzhiyun 	struct drm_panel *panel = lvds->panel;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	return drm_panel_get_modes(panel, connector);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun static const
169*4882a593Smuzhiyun struct drm_connector_helper_funcs rockchip_lvds_connector_helper_funcs = {
170*4882a593Smuzhiyun 	.get_modes = rockchip_lvds_connector_get_modes,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static void
rockchip_lvds_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)174*4882a593Smuzhiyun rockchip_lvds_encoder_atomic_mode_set(struct drm_encoder *encoder,
175*4882a593Smuzhiyun 				      struct drm_crtc_state *crtc_state,
176*4882a593Smuzhiyun 				      struct drm_connector_state *conn_state)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
179*4882a593Smuzhiyun 	struct drm_connector *connector = &lvds->connector;
180*4882a593Smuzhiyun 	struct drm_display_info *info = &connector->display_info;
181*4882a593Smuzhiyun 	u32 bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	if (info->num_bus_formats)
184*4882a593Smuzhiyun 		bus_format = info->bus_formats[0];
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	switch (bus_format) {
187*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:	/* jeida-24 */
188*4882a593Smuzhiyun 		lvds->format = LVDS_8BIT_MODE_FORMAT_2;
189*4882a593Smuzhiyun 		break;
190*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA: /* jeida-30 */
191*4882a593Smuzhiyun 		lvds->format = LVDS_10BIT_MODE_FORMAT_2;
192*4882a593Smuzhiyun 		break;
193*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:	/* jeida-18, compatible with the [JEIDA], [LDI] and [VESA] specifications */
194*4882a593Smuzhiyun 		lvds->format = LVDS_6BIT_MODE_FORMAT_1;
195*4882a593Smuzhiyun 		break;
196*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG: /* vesa-30 */
197*4882a593Smuzhiyun 		lvds->format = LVDS_10BIT_MODE_FORMAT_1;
198*4882a593Smuzhiyun 		break;
199*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:	/* vesa-24 */
200*4882a593Smuzhiyun 	default:
201*4882a593Smuzhiyun 		lvds->format = LVDS_8BIT_MODE_FORMAT_1;
202*4882a593Smuzhiyun 		break;
203*4882a593Smuzhiyun 	}
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	if (lvds->secondary)
206*4882a593Smuzhiyun 		lvds->secondary->format = lvds->format;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	drm_mode_copy(&lvds->mode, &crtc_state->adjusted_mode);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun static int
rockchip_lvds_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)212*4882a593Smuzhiyun rockchip_lvds_encoder_atomic_check(struct drm_encoder *encoder,
213*4882a593Smuzhiyun 				   struct drm_crtc_state *crtc_state,
214*4882a593Smuzhiyun 				   struct drm_connector_state *conn_state)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
217*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
218*4882a593Smuzhiyun 	struct drm_connector *connector = conn_state->connector;
219*4882a593Smuzhiyun 	struct drm_display_info *info = &connector->display_info;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	if (info->num_bus_formats)
222*4882a593Smuzhiyun 		s->bus_format = info->bus_formats[0];
223*4882a593Smuzhiyun 	else
224*4882a593Smuzhiyun 		s->bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	s->output_mode = ROCKCHIP_OUT_MODE_P888;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	if (s->bus_format == MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG ||
229*4882a593Smuzhiyun 	    s->bus_format == MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA)
230*4882a593Smuzhiyun 		s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	s->output_type = DRM_MODE_CONNECTOR_LVDS;
233*4882a593Smuzhiyun 	s->bus_flags = info->bus_flags;
234*4882a593Smuzhiyun 	s->tv_state = &conn_state->tv;
235*4882a593Smuzhiyun 	s->eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
236*4882a593Smuzhiyun 	s->color_space = V4L2_COLORSPACE_DEFAULT;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	switch (lvds->pixel_order) {
239*4882a593Smuzhiyun 	case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
240*4882a593Smuzhiyun 		s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE;
241*4882a593Smuzhiyun 		s->output_if |= VOP_OUTPUT_IF_LVDS1 | VOP_OUTPUT_IF_LVDS0;
242*4882a593Smuzhiyun 		break;
243*4882a593Smuzhiyun 	case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
244*4882a593Smuzhiyun 		s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE;
245*4882a593Smuzhiyun 		s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
246*4882a593Smuzhiyun 		s->output_if |= VOP_OUTPUT_IF_LVDS1 | VOP_OUTPUT_IF_LVDS0;
247*4882a593Smuzhiyun 		break;
248*4882a593Smuzhiyun /*
249*4882a593Smuzhiyun  * Fix me: To do it with a GKI compatible version.
250*4882a593Smuzhiyun  */
251*4882a593Smuzhiyun #if 0
252*4882a593Smuzhiyun 	case DRM_LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS:
253*4882a593Smuzhiyun 		s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
254*4882a593Smuzhiyun 		s->output_if |= VOP_OUTPUT_IF_LVDS1 | VOP_OUTPUT_IF_LVDS0;
255*4882a593Smuzhiyun 		break;
256*4882a593Smuzhiyun 	case DRM_LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS:
257*4882a593Smuzhiyun 		s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
258*4882a593Smuzhiyun 		s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
259*4882a593Smuzhiyun 		s->output_if |= VOP_OUTPUT_IF_LVDS1 | VOP_OUTPUT_IF_LVDS0;
260*4882a593Smuzhiyun 		break;
261*4882a593Smuzhiyun #endif
262*4882a593Smuzhiyun 	default:
263*4882a593Smuzhiyun 		if (lvds->id)
264*4882a593Smuzhiyun 			s->output_if |= VOP_OUTPUT_IF_LVDS1;
265*4882a593Smuzhiyun 		else
266*4882a593Smuzhiyun 			s->output_if |= VOP_OUTPUT_IF_LVDS0;
267*4882a593Smuzhiyun 		break;
268*4882a593Smuzhiyun 	}
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	return 0;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun 
rockchip_lvds_enable(struct rockchip_lvds * lvds)273*4882a593Smuzhiyun static void rockchip_lvds_enable(struct rockchip_lvds *lvds)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	int ret;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	if (lvds->funcs->enable)
278*4882a593Smuzhiyun 		lvds->funcs->enable(lvds);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	ret = phy_set_mode(lvds->phy, PHY_MODE_LVDS);
281*4882a593Smuzhiyun 	if (ret) {
282*4882a593Smuzhiyun 		DRM_DEV_ERROR(lvds->dev, "failed to set phy mode: %d\n", ret);
283*4882a593Smuzhiyun 		return;
284*4882a593Smuzhiyun 	}
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	if (lvds->phy && !lvds->phy_enabled) {
287*4882a593Smuzhiyun 		phy_power_on(lvds->phy);
288*4882a593Smuzhiyun 		lvds->phy_enabled = true;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	if (lvds->secondary)
292*4882a593Smuzhiyun 		rockchip_lvds_enable(lvds->secondary);
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun 
rockchip_lvds_disable(struct rockchip_lvds * lvds)295*4882a593Smuzhiyun static void rockchip_lvds_disable(struct rockchip_lvds *lvds)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun 	if (lvds->funcs->disable)
298*4882a593Smuzhiyun 		lvds->funcs->disable(lvds);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	if (lvds->phy && lvds->phy_enabled) {
301*4882a593Smuzhiyun 		phy_power_off(lvds->phy);
302*4882a593Smuzhiyun 		lvds->phy_enabled = false;
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	if (lvds->secondary)
306*4882a593Smuzhiyun 		rockchip_lvds_disable(lvds->secondary);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun 
rockchip_lvds_encoder_enable(struct drm_encoder * encoder)309*4882a593Smuzhiyun static void rockchip_lvds_encoder_enable(struct drm_encoder *encoder)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	if (lvds->panel)
314*4882a593Smuzhiyun 		drm_panel_prepare(lvds->panel);
315*4882a593Smuzhiyun 	rockchip_lvds_enable(lvds);
316*4882a593Smuzhiyun 	if (lvds->panel)
317*4882a593Smuzhiyun 		drm_panel_enable(lvds->panel);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
rockchip_lvds_encoder_disable(struct drm_encoder * encoder)320*4882a593Smuzhiyun static void rockchip_lvds_encoder_disable(struct drm_encoder *encoder)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	if (lvds->panel)
325*4882a593Smuzhiyun 		drm_panel_disable(lvds->panel);
326*4882a593Smuzhiyun 	rockchip_lvds_disable(lvds);
327*4882a593Smuzhiyun 	if (lvds->panel)
328*4882a593Smuzhiyun 		drm_panel_unprepare(lvds->panel);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
rockchip_lvds_encoder_loader_protect(struct drm_encoder * encoder,bool on)331*4882a593Smuzhiyun static int rockchip_lvds_encoder_loader_protect(struct drm_encoder *encoder,
332*4882a593Smuzhiyun 						bool on)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	if (lvds->panel)
337*4882a593Smuzhiyun 		panel_simple_loader_protect(lvds->panel);
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	if (on) {
341*4882a593Smuzhiyun 		phy_init(lvds->phy);
342*4882a593Smuzhiyun 		if (lvds->phy) {
343*4882a593Smuzhiyun 			lvds->phy->power_count++;
344*4882a593Smuzhiyun 			lvds->phy_enabled = true;
345*4882a593Smuzhiyun 		}
346*4882a593Smuzhiyun 	} else {
347*4882a593Smuzhiyun 		phy_exit(lvds->phy);
348*4882a593Smuzhiyun 		if (lvds->phy) {
349*4882a593Smuzhiyun 			lvds->phy->power_count--;
350*4882a593Smuzhiyun 			lvds->phy_enabled = false;
351*4882a593Smuzhiyun 		}
352*4882a593Smuzhiyun 	}
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	return 0;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun static const
358*4882a593Smuzhiyun struct drm_encoder_helper_funcs rockchip_lvds_encoder_helper_funcs = {
359*4882a593Smuzhiyun 	.enable = rockchip_lvds_encoder_enable,
360*4882a593Smuzhiyun 	.disable = rockchip_lvds_encoder_disable,
361*4882a593Smuzhiyun 	.atomic_check = rockchip_lvds_encoder_atomic_check,
362*4882a593Smuzhiyun 	.atomic_mode_set = rockchip_lvds_encoder_atomic_mode_set,
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun static const struct drm_encoder_funcs rockchip_lvds_encoder_funcs = {
366*4882a593Smuzhiyun 	.destroy = drm_encoder_cleanup,
367*4882a593Smuzhiyun };
368*4882a593Smuzhiyun 
rockchip_lvds_match_by_id(struct device * dev,const void * data)369*4882a593Smuzhiyun static int rockchip_lvds_match_by_id(struct device *dev, const void *data)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = dev_get_drvdata(dev);
372*4882a593Smuzhiyun 	unsigned int *id = (unsigned int *)data;
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	return lvds->id == *id;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun 
rockchip_lvds_find_by_id(struct device_driver * drv,unsigned int id)377*4882a593Smuzhiyun static struct rockchip_lvds *rockchip_lvds_find_by_id(struct device_driver *drv,
378*4882a593Smuzhiyun 						      unsigned int id)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun 	struct device *dev;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	dev = driver_find_device(drv, NULL, &id, rockchip_lvds_match_by_id);
383*4882a593Smuzhiyun 	if (!dev)
384*4882a593Smuzhiyun 		return NULL;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	return dev_get_drvdata(dev);
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun 
rockchip_lvds_bind(struct device * dev,struct device * master,void * data)389*4882a593Smuzhiyun static int rockchip_lvds_bind(struct device *dev, struct device *master,
390*4882a593Smuzhiyun 			      void *data)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = dev_get_drvdata(dev);
393*4882a593Smuzhiyun 	struct drm_device *drm_dev = data;
394*4882a593Smuzhiyun 	struct drm_encoder *encoder = &lvds->encoder;
395*4882a593Smuzhiyun 	struct drm_connector *connector = &lvds->connector;
396*4882a593Smuzhiyun 	int ret;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	/*
399*4882a593Smuzhiyun 	 * dual channel lvds mode only need to register one connector.
400*4882a593Smuzhiyun 	 */
401*4882a593Smuzhiyun 	if (lvds->primary)
402*4882a593Smuzhiyun 		return 0;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
405*4882a593Smuzhiyun 					  &lvds->panel, &lvds->bridge);
406*4882a593Smuzhiyun 	if (ret)
407*4882a593Smuzhiyun 		return ret;
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
410*4882a593Smuzhiyun 								      dev->of_node);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	ret = drm_encoder_init(drm_dev, encoder, &rockchip_lvds_encoder_funcs,
413*4882a593Smuzhiyun 			       DRM_MODE_ENCODER_LVDS, NULL);
414*4882a593Smuzhiyun 	if (ret < 0) {
415*4882a593Smuzhiyun 		DRM_DEV_ERROR(lvds->dev,
416*4882a593Smuzhiyun 			      "failed to initialize encoder: %d\n", ret);
417*4882a593Smuzhiyun 		return ret;
418*4882a593Smuzhiyun 	}
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	drm_encoder_helper_add(encoder, &rockchip_lvds_encoder_helper_funcs);
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	if (lvds->panel) {
423*4882a593Smuzhiyun 		struct rockchip_drm_private *private = drm_dev->dev_private;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 		ret = drm_connector_init(drm_dev, connector,
426*4882a593Smuzhiyun 					 &rockchip_lvds_connector_funcs,
427*4882a593Smuzhiyun 					 DRM_MODE_CONNECTOR_LVDS);
428*4882a593Smuzhiyun 		if (ret < 0) {
429*4882a593Smuzhiyun 			DRM_DEV_ERROR(drm_dev->dev,
430*4882a593Smuzhiyun 				      "failed to initialize connector: %d\n", ret);
431*4882a593Smuzhiyun 			goto err_free_encoder;
432*4882a593Smuzhiyun 		}
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 		drm_connector_helper_add(connector,
435*4882a593Smuzhiyun 					 &rockchip_lvds_connector_helper_funcs);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 		ret = drm_connector_attach_encoder(connector, encoder);
438*4882a593Smuzhiyun 		if (ret < 0) {
439*4882a593Smuzhiyun 			DRM_DEV_ERROR(lvds->dev,
440*4882a593Smuzhiyun 				      "failed to attach encoder: %d\n", ret);
441*4882a593Smuzhiyun 			goto err_free_connector;
442*4882a593Smuzhiyun 		}
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 		lvds->sub_dev.connector = &lvds->connector;
445*4882a593Smuzhiyun 		lvds->sub_dev.of_node = lvds->dev->of_node;
446*4882a593Smuzhiyun 		lvds->sub_dev.loader_protect = rockchip_lvds_encoder_loader_protect;
447*4882a593Smuzhiyun 		rockchip_drm_register_sub_dev(&lvds->sub_dev);
448*4882a593Smuzhiyun 		drm_object_attach_property(&connector->base, private->connector_id_prop, 0);
449*4882a593Smuzhiyun 	} else {
450*4882a593Smuzhiyun 		ret = drm_bridge_attach(encoder, lvds->bridge, NULL, 0);
451*4882a593Smuzhiyun 		if (ret) {
452*4882a593Smuzhiyun 			DRM_DEV_ERROR(lvds->dev,
453*4882a593Smuzhiyun 				      "failed to attach bridge: %d\n", ret);
454*4882a593Smuzhiyun 			goto err_free_encoder;
455*4882a593Smuzhiyun 		}
456*4882a593Smuzhiyun 	}
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	return 0;
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun err_free_connector:
461*4882a593Smuzhiyun 	drm_connector_cleanup(connector);
462*4882a593Smuzhiyun err_free_encoder:
463*4882a593Smuzhiyun 	drm_encoder_cleanup(encoder);
464*4882a593Smuzhiyun 	return ret;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun 
rockchip_lvds_unbind(struct device * dev,struct device * master,void * data)467*4882a593Smuzhiyun static void rockchip_lvds_unbind(struct device *dev, struct device *master,
468*4882a593Smuzhiyun 				void *data)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun 	struct rockchip_lvds *lvds = dev_get_drvdata(dev);
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	if (lvds->sub_dev.connector)
473*4882a593Smuzhiyun 		rockchip_drm_unregister_sub_dev(&lvds->sub_dev);
474*4882a593Smuzhiyun 	if (lvds->panel)
475*4882a593Smuzhiyun 		drm_connector_cleanup(&lvds->connector);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	if (lvds->encoder.dev)
478*4882a593Smuzhiyun 		drm_encoder_cleanup(&lvds->encoder);
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun static const struct component_ops rockchip_lvds_component_ops = {
482*4882a593Smuzhiyun 	.bind = rockchip_lvds_bind,
483*4882a593Smuzhiyun 	.unbind = rockchip_lvds_unbind,
484*4882a593Smuzhiyun };
485*4882a593Smuzhiyun 
rockchip_lvds_probe(struct platform_device * pdev)486*4882a593Smuzhiyun static int rockchip_lvds_probe(struct platform_device *pdev)
487*4882a593Smuzhiyun {
488*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
489*4882a593Smuzhiyun 	struct rockchip_lvds *lvds;
490*4882a593Smuzhiyun 	int ret;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	if (!dev->of_node)
493*4882a593Smuzhiyun 		return -ENODEV;
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	lvds = devm_kzalloc(dev, sizeof(*lvds), GFP_KERNEL);
496*4882a593Smuzhiyun 	if (!lvds)
497*4882a593Smuzhiyun 		return -ENOMEM;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	lvds->id = of_alias_get_id(dev->of_node, "lvds");
500*4882a593Smuzhiyun 	if (lvds->id < 0)
501*4882a593Smuzhiyun 		lvds->id = 0;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	lvds->dev = dev;
504*4882a593Smuzhiyun 	lvds->funcs = of_device_get_match_data(dev);
505*4882a593Smuzhiyun 	platform_set_drvdata(pdev, lvds);
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	lvds->dual_channel = of_property_read_bool(dev->of_node,
508*4882a593Smuzhiyun 						   "dual-channel");
509*4882a593Smuzhiyun 	lvds->data_swap = of_property_read_bool(dev->of_node,
510*4882a593Smuzhiyun 						"rockchip,data-swap");
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	lvds->phy = devm_phy_get(dev, "phy");
513*4882a593Smuzhiyun 	if (IS_ERR(lvds->phy)) {
514*4882a593Smuzhiyun 		ret = PTR_ERR(lvds->phy);
515*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to get phy: %d\n", ret);
516*4882a593Smuzhiyun 		return ret;
517*4882a593Smuzhiyun 	}
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	lvds->grf = syscon_node_to_regmap(dev->parent->of_node);
520*4882a593Smuzhiyun 	if (IS_ERR(lvds->grf)) {
521*4882a593Smuzhiyun 		ret = PTR_ERR(lvds->grf);
522*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "Unable to get grf: %d\n", ret);
523*4882a593Smuzhiyun 		return ret;
524*4882a593Smuzhiyun 	}
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	lvds->pixel_order = -1;
527*4882a593Smuzhiyun 	if (lvds->funcs->probe) {
528*4882a593Smuzhiyun 		ret = lvds->funcs->probe(lvds);
529*4882a593Smuzhiyun 		if (ret)
530*4882a593Smuzhiyun 			return ret;
531*4882a593Smuzhiyun 	}
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 	return component_add(dev, &rockchip_lvds_component_ops);
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun 
rockchip_lvds_remove(struct platform_device * pdev)536*4882a593Smuzhiyun static int rockchip_lvds_remove(struct platform_device *pdev)
537*4882a593Smuzhiyun {
538*4882a593Smuzhiyun 	component_del(&pdev->dev, &rockchip_lvds_component_ops);
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	return 0;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun 
px30_lvds_enable(struct rockchip_lvds * lvds)543*4882a593Smuzhiyun static void px30_lvds_enable(struct rockchip_lvds *lvds)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun 	int pipe = drm_of_encoder_active_endpoint_id(lvds->dev->of_node,
546*4882a593Smuzhiyun 						     &lvds->encoder);
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	regmap_write(lvds->grf, PX30_GRF_PD_VO_CON1,
549*4882a593Smuzhiyun 		     PX30_LVDS_SELECT(lvds->format) |
550*4882a593Smuzhiyun 		     PX30_LVDS_MODE_EN(1) | PX30_LVDS_MSBSEL(1) |
551*4882a593Smuzhiyun 		     PX30_LVDS_P2S_EN(1) | PX30_LVDS_VOP_SEL(pipe));
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun 
px30_lvds_disable(struct rockchip_lvds * lvds)554*4882a593Smuzhiyun static void px30_lvds_disable(struct rockchip_lvds *lvds)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun 	regmap_write(lvds->grf, PX30_GRF_PD_VO_CON1,
557*4882a593Smuzhiyun 		     PX30_LVDS_MODE_EN(0) | PX30_LVDS_P2S_EN(0));
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun static const struct rockchip_lvds_funcs px30_lvds_funcs = {
561*4882a593Smuzhiyun 	.enable = px30_lvds_enable,
562*4882a593Smuzhiyun 	.disable = px30_lvds_disable,
563*4882a593Smuzhiyun };
564*4882a593Smuzhiyun 
rk3126_lvds_enable(struct rockchip_lvds * lvds)565*4882a593Smuzhiyun static void rk3126_lvds_enable(struct rockchip_lvds *lvds)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3126_GRF_LVDS_CON0,
568*4882a593Smuzhiyun 		     RK3126_LVDS_P2S_EN(1) | RK3126_LVDS_MODE_EN(1) |
569*4882a593Smuzhiyun 		     RK3126_LVDS_MSBSEL(1) | RK3126_LVDS_SELECT(lvds->format));
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun 
rk3126_lvds_disable(struct rockchip_lvds * lvds)572*4882a593Smuzhiyun static void rk3126_lvds_disable(struct rockchip_lvds *lvds)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3126_GRF_LVDS_CON0,
575*4882a593Smuzhiyun 		     RK3126_LVDS_P2S_EN(0) | RK3126_LVDS_MODE_EN(0));
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun static const struct rockchip_lvds_funcs rk3126_lvds_funcs = {
579*4882a593Smuzhiyun 	.enable = rk3126_lvds_enable,
580*4882a593Smuzhiyun 	.disable = rk3126_lvds_disable,
581*4882a593Smuzhiyun };
582*4882a593Smuzhiyun 
rk3288_lvds_enable(struct rockchip_lvds * lvds)583*4882a593Smuzhiyun static void rk3288_lvds_enable(struct rockchip_lvds *lvds)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun 	struct drm_display_mode *mode = &lvds->mode;
586*4882a593Smuzhiyun 	int pipe;
587*4882a593Smuzhiyun 	u32 val;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	pipe = drm_of_encoder_active_endpoint_id(lvds->dev->of_node,
590*4882a593Smuzhiyun 						 &lvds->encoder);
591*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3288_GRF_SOC_CON6,
592*4882a593Smuzhiyun 		     RK3288_LVDS_LCDC_SEL(pipe));
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	val = RK3288_LVDS_PWRDWN(0) | RK3288_LVDS_CON_CLKINV(0) |
595*4882a593Smuzhiyun 	      RK3288_LVDS_CON_CHASEL(lvds->dual_channel) |
596*4882a593Smuzhiyun 	      RK3288_LVDS_CON_SELECT(lvds->format);
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	if (lvds->dual_channel) {
599*4882a593Smuzhiyun 		u32 h_bp = mode->htotal - mode->hsync_start;
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 		val |= RK3288_LVDS_CON_ENABLE_2(1) |
602*4882a593Smuzhiyun 		       RK3288_LVDS_CON_ENABLE_1(1) |
603*4882a593Smuzhiyun 		       RK3288_LVDS_CON_STARTSEL(lvds->data_swap);
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 		if (h_bp % 2)
606*4882a593Smuzhiyun 			val |= RK3288_LVDS_CON_STARTPHASE(1);
607*4882a593Smuzhiyun 		else
608*4882a593Smuzhiyun 			val |= RK3288_LVDS_CON_STARTPHASE(0);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	} else {
611*4882a593Smuzhiyun 		val |= RK3288_LVDS_CON_ENABLE_2(0) |
612*4882a593Smuzhiyun 		       RK3288_LVDS_CON_ENABLE_1(1);
613*4882a593Smuzhiyun 	}
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3288_GRF_SOC_CON7, val);
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	phy_set_bus_width(lvds->phy, lvds->dual_channel ? 2 : 1);
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun 
rk3288_lvds_disable(struct rockchip_lvds * lvds)620*4882a593Smuzhiyun static void rk3288_lvds_disable(struct rockchip_lvds *lvds)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3288_GRF_SOC_CON7, RK3288_LVDS_PWRDWN(1));
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun static const struct rockchip_lvds_funcs rk3288_lvds_funcs = {
626*4882a593Smuzhiyun 	.enable = rk3288_lvds_enable,
627*4882a593Smuzhiyun 	.disable = rk3288_lvds_disable,
628*4882a593Smuzhiyun };
629*4882a593Smuzhiyun 
rk3368_lvds_enable(struct rockchip_lvds * lvds)630*4882a593Smuzhiyun static void rk3368_lvds_enable(struct rockchip_lvds *lvds)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3368_GRF_SOC_CON7,
633*4882a593Smuzhiyun 		     RK3368_LVDS_SELECT(lvds->format) |
634*4882a593Smuzhiyun 		     RK3368_LVDS_MODE_EN(1) | RK3368_LVDS_MSBSEL(1) |
635*4882a593Smuzhiyun 		     RK3368_LVDS_P2S_EN(1));
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun 
rk3368_lvds_disable(struct rockchip_lvds * lvds)638*4882a593Smuzhiyun static void rk3368_lvds_disable(struct rockchip_lvds *lvds)
639*4882a593Smuzhiyun {
640*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3368_GRF_SOC_CON7,
641*4882a593Smuzhiyun 		     RK3368_LVDS_MODE_EN(0) | RK3368_LVDS_P2S_EN(0));
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun static const struct rockchip_lvds_funcs rk3368_lvds_funcs = {
645*4882a593Smuzhiyun 	.enable = rk3368_lvds_enable,
646*4882a593Smuzhiyun 	.disable = rk3368_lvds_disable,
647*4882a593Smuzhiyun };
648*4882a593Smuzhiyun 
rockchip_secondary_lvds_probe(struct rockchip_lvds * lvds)649*4882a593Smuzhiyun static int __maybe_unused rockchip_secondary_lvds_probe(struct rockchip_lvds *lvds)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun 	if (lvds->dual_channel) {
652*4882a593Smuzhiyun 		struct rockchip_lvds *secondary = NULL;
653*4882a593Smuzhiyun 		struct device_node *port0, *port1;
654*4882a593Smuzhiyun 		int pixel_order;
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 		secondary = rockchip_lvds_find_by_id(lvds->dev->driver, 1);
657*4882a593Smuzhiyun 		if (!secondary)
658*4882a593Smuzhiyun 			return -EPROBE_DEFER;
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 		port0 = of_graph_get_port_by_id(lvds->dev->of_node, 1);
661*4882a593Smuzhiyun 		port1 = of_graph_get_port_by_id(secondary->dev->of_node, 1);
662*4882a593Smuzhiyun 		pixel_order = drm_of_lvds_get_dual_link_pixel_order(port0, port1);
663*4882a593Smuzhiyun 		of_node_put(port1);
664*4882a593Smuzhiyun 		of_node_put(port0);
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 		secondary->primary = lvds;
667*4882a593Smuzhiyun 		lvds->secondary = secondary;
668*4882a593Smuzhiyun 		lvds->pixel_order = pixel_order >= 0 ? pixel_order : 0;
669*4882a593Smuzhiyun 	}
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	return 0;
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun 
rk3562_lvds_enable(struct rockchip_lvds * lvds)674*4882a593Smuzhiyun static void rk3562_lvds_enable(struct rockchip_lvds *lvds)
675*4882a593Smuzhiyun {
676*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3562_GRF_VO_CON1,
677*4882a593Smuzhiyun 		     RK3568_LVDS0_MODE_EN(1) | RK3568_LVDS0_P2S_EN(1) |
678*4882a593Smuzhiyun 		     RK3568_LVDS0_DCLK_INV_SEL(1));
679*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3562_GRF_VO_CON0,
680*4882a593Smuzhiyun 		     RK3568_LVDS0_SELECT(lvds->format) | RK3568_LVDS0_MSBSEL(1));
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun 
rk3562_lvds_disable(struct rockchip_lvds * lvds)683*4882a593Smuzhiyun static void rk3562_lvds_disable(struct rockchip_lvds *lvds)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3562_GRF_VO_CON1, RK3568_LVDS0_MODE_EN(0));
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun static const struct rockchip_lvds_funcs rk3562_lvds_funcs = {
689*4882a593Smuzhiyun 	.enable = rk3562_lvds_enable,
690*4882a593Smuzhiyun 	.disable = rk3562_lvds_disable,
691*4882a593Smuzhiyun };
692*4882a593Smuzhiyun 
rk3568_lvds_enable(struct rockchip_lvds * lvds)693*4882a593Smuzhiyun static void rk3568_lvds_enable(struct rockchip_lvds *lvds)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3568_GRF_VO_CON2,
696*4882a593Smuzhiyun 		     RK3568_LVDS0_MODE_EN(1) | RK3568_LVDS0_P2S_EN(1) |
697*4882a593Smuzhiyun 		     RK3568_LVDS0_DCLK_INV_SEL(1));
698*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3568_GRF_VO_CON0,
699*4882a593Smuzhiyun 		     RK3568_LVDS0_SELECT(lvds->format) | RK3568_LVDS0_MSBSEL(1));
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun 
rk3568_lvds_disable(struct rockchip_lvds * lvds)702*4882a593Smuzhiyun static void rk3568_lvds_disable(struct rockchip_lvds *lvds)
703*4882a593Smuzhiyun {
704*4882a593Smuzhiyun 	regmap_write(lvds->grf, RK3568_GRF_VO_CON2, RK3568_LVDS0_MODE_EN(0));
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun static const struct rockchip_lvds_funcs rk3568_lvds_funcs = {
708*4882a593Smuzhiyun 	.enable = rk3568_lvds_enable,
709*4882a593Smuzhiyun 	.disable = rk3568_lvds_disable,
710*4882a593Smuzhiyun };
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun static const struct of_device_id rockchip_lvds_dt_ids[] = {
713*4882a593Smuzhiyun 	{ .compatible = "rockchip,px30-lvds", .data = &px30_lvds_funcs },
714*4882a593Smuzhiyun 	{ .compatible = "rockchip,rk3126-lvds", .data = &rk3126_lvds_funcs },
715*4882a593Smuzhiyun 	{ .compatible = "rockchip,rk3288-lvds", .data = &rk3288_lvds_funcs },
716*4882a593Smuzhiyun 	{ .compatible = "rockchip,rk3368-lvds", .data = &rk3368_lvds_funcs },
717*4882a593Smuzhiyun 	{ .compatible = "rockchip,rk3562-lvds", .data = &rk3562_lvds_funcs },
718*4882a593Smuzhiyun 	{ .compatible = "rockchip,rk3568-lvds", .data = &rk3568_lvds_funcs },
719*4882a593Smuzhiyun 	{}
720*4882a593Smuzhiyun };
721*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rockchip_lvds_dt_ids);
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun struct platform_driver rockchip_lvds_driver = {
724*4882a593Smuzhiyun 	.probe = rockchip_lvds_probe,
725*4882a593Smuzhiyun 	.remove = rockchip_lvds_remove,
726*4882a593Smuzhiyun 	.driver = {
727*4882a593Smuzhiyun 		   .name = "rockchip-lvds",
728*4882a593Smuzhiyun 		   .of_match_table = of_match_ptr(rockchip_lvds_dt_ids),
729*4882a593Smuzhiyun 	},
730*4882a593Smuzhiyun };
731