1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Shunqing Chen <csq@rock-chips.com>
6 */
7
8 #ifndef _RK628_H
9 #define _RK628_H
10
11 #include <linux/module.h>
12 #include <linux/i2c.h>
13 #include <linux/regmap.h>
14 #include <linux/version.h>
15 #include <video/videomode.h>
16
17 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
18 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16))
19
20 #define GRF_SYSTEM_CON0 0x0000
21 #define SW_VSYNC_POL_MASK BIT(26)
22 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
23 #define SW_HSYNC_POL_MASK BIT(25)
24 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
25 #define SW_ADAPTER_I2CSLADR_MASK GENMASK(24, 22)
26 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
27 #define SW_EDID_MODE_MASK BIT(21)
28 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
29 #define SW_I2S_DATA_OEN_MASK BIT(10)
30 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
31 #define SW_BT_DATA_OEN_MASK BIT(9)
32 #define SW_BT_DATA_OEN BIT(9)
33 #define SW_EFUSE_HDCP_EN_MASK BIT(8)
34 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
35 #define SW_OUTPUT_MODE_MASK GENMASK(7, 3)
36 #define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3)
37 #define SW_INPUT_MODE_MASK GENMASK(2, 0)
38 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
39 #define GRF_SYSTEM_CON1 0x0004
40 #define GRF_SYSTEM_CON2 0x0008
41 #define GRF_SYSTEM_CON3 0x000c
42 #define GRF_GPIO_RX_CEC_SEL_MASK BIT(7)
43 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7)
44 #define GRF_GPIO_RXDDC_SDA_SEL_MASK BIT(6)
45 #define GRF_GPIO_RXDDC_SDA_SEL(x) UPDATE(x, 6, 6)
46 #define GRF_GPIO_RXDDC_SCL_SEL_MASK BIT(5)
47 #define GRF_GPIO_RXDDC_SCL_SEL(x) UPDATE(x, 5, 5)
48 #define GRF_SCALER_CON0 0x0010
49 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
50 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
51 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
52 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
53 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
54 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
55 #define GRF_SCALER_CON1 0x0014
56 #define SCL_V_FACTOR(x) UPDATE(x, 31, 16)
57 #define SCL_H_FACTOR(x) UPDATE(x, 15, 0)
58 #define GRF_SCALER_CON2 0x0018
59 #define DSP_FRAME_VST(x) UPDATE(x, 28, 16)
60 #define DSP_FRAME_HST(x) UPDATE(x, 12, 0)
61 #define GRF_SCALER_CON3 0x001c
62 #define DSP_HS_END(x) UPDATE(x, 23, 16)
63 #define DSP_HTOTAL(x) UPDATE(x, 12, 0)
64 #define GRF_SCALER_CON4 0x0020
65 #define DSP_HACT_ST(x) UPDATE(x, 28, 16)
66 #define DSP_HACT_END(x) UPDATE(x, 12, 0)
67 #define GRF_SCALER_CON5 0x0024
68 #define DSP_VS_END(x) UPDATE(x, 23, 16)
69 #define DSP_VTOTAL(x) UPDATE(x, 12, 0)
70 #define GRF_SCALER_CON6 0x0028
71 #define DSP_VACT_ST(x) UPDATE(x, 28, 16)
72 #define DSP_VACT_END(x) UPDATE(x, 12, 0)
73 #define GRF_SCALER_CON7 0x002c
74 #define DSP_HBOR_ST(x) UPDATE(x, 28, 16)
75 #define DSP_HBOR_END(x) UPDATE(x, 12, 0)
76 #define GRF_SCALER_CON8 0x0030
77 #define DSP_VBOR_ST(x) UPDATE(x, 28, 16)
78 #define DSP_VBOR_END(x) UPDATE(x, 12, 0)
79 #define GRF_POST_PROC_CON 0x0034
80 #define SW_DCLK_OUT_INV_EN BIT(9)
81 #define SW_DCLK_IN_INV_EN BIT(8)
82 #define SW_TXPHY_REFCLK_SEL_MASK GENMASK(6, 5)
83 #define SW_TXPHY_REFCLK_SEL(x) UPDATE(x, 6, 5)
84 #define SW_HDMITX_VCLK_PLLREF_SEL_MASK BIT(4)
85 #define SW_HDMITX_VCLK_PLLREF_SEL(x) UPDATE(x, 4, 4)
86 #define SW_HDMITX_DCLK_INV_EN BIT(3)
87 #define SW_SPLIT_MODE(x) UPDATE(x, 1, 1)
88 #define SW_SPLIT_EN BIT(0)
89 #define GRF_CSC_CTRL_CON 0x0038
90 #define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8)
91 #define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4)
92 #define SW_Y2R_EN(x) HIWORD_UPDATE(x, 0, 0)
93 #define GRF_LVDS_TX_CON 0x003c
94 #define SW_LVDS_CON_DUAL_SEL(x) HIWORD_UPDATE(x, 12, 12)
95 #define SW_LVDS_CON_DEN_POLARITY(x) HIWORD_UPDATE(x, 11, 11)
96 #define SW_LVDS_CON_HS_POLARITY(x) HIWORD_UPDATE(x, 10, 10)
97 #define SW_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 9, 9)
98 #define SW_LVDS_STARTPHASE(x) HIWORD_UPDATE(x, 8, 8)
99 #define SW_LVDS_CON_STARTSEL(x) HIWORD_UPDATE(x, 7, 7)
100 #define SW_LVDS_CON_CHASEL(x) HIWORD_UPDATE(x, 6, 6)
101 #define SW_LVDS_TIE_VSYNC_VALUE(x) HIWORD_UPDATE(x, 5, 5)
102 #define SW_LVDS_TIE_HSYNC_VALUE(x) HIWORD_UPDATE(x, 4, 4)
103 #define SW_LVDS_TIE_DEN_ONLY(x) HIWORD_UPDATE(x, 3, 3)
104 #define SW_LVDS_CON_MSBSEL(x) HIWORD_UPDATE(x, 2, 2)
105 #define SW_LVDS_CON_SELECT(x) HIWORD_UPDATE(x, 1, 0)
106 #define GRF_RGB_DEC_CON0 0x0040
107 #define SW_HRES_MASK GENMASK(28, 16)
108 #define SW_HRES(x) UPDATE(x, 28, 16)
109 #define DUAL_DATA_SWAP BIT(6)
110 #define DEC_DUALEDGE_EN BIT(5)
111 #define SW_PROGRESS_EN BIT(4)
112 #define SW_YC_SWAP BIT(3)
113 #define SW_CAP_EN_ASYNC BIT(1)
114 #define SW_CAP_EN_PSYNC BIT(0)
115 #define GRF_RGB_DEC_CON1 0x0044
116 #define SW_SET_X_MASK GENMASK(28, 16)
117 #define SW_SET_X(x) HIWORD_UPDATE(x, 28, 16)
118 #define SW_SET_Y_MASK GENMASK(28, 16)
119 #define SW_SET_Y(x) HIWORD_UPDATE(x, 28, 16)
120 #define GRF_RGB_DEC_CON2 0x0048
121 #define GRF_RGB_ENC_CON 0x004c
122 #define BT1120_UV_SWAP(x) HIWORD_UPDATE(x, 5, 5)
123 #define ENC_DUALEDGE_EN(x) HIWORD_UPDATE(x, 3, 3)
124 #define GRF_MIPI_LANE_DELAY_CON0 0x0050
125 #define GRF_MIPI_LANE_DELAY_CON1 0x0054
126 #define GRF_BT1120_DCLK_DELAY_CON0 0x0058
127 #define GRF_BT1120_DCLK_DELAY_CON1 0x005c
128 #define GRF_MIPI_TX0_CON 0x0060
129 #define DPIUPDATECFG BIT(26)
130 #define DPICOLORM BIT(25)
131 #define DPISHUTDN BIT(24)
132 #define CSI_PHYRSTZ BIT(21)
133 #define CSI_PHYSHUTDOWNZ BIT(20)
134 #define FORCETXSTOPMODE_MASK GENMASK(19, 16)
135 #define FORCETXSTOPMODE(x) UPDATE(x, 19, 16)
136 #define FORCERXMODE_MASK GENMASK(15, 12)
137 #define FORCERXMODE(x) UPDATE(x, 15, 12)
138 #define PHY_TESTCLR BIT(10)
139 #define PHY_TESTCLK BIT(9)
140 #define PHY_TESTEN BIT(8)
141 #define PHY_TESTDIN_MASK GENMASK(7, 0)
142 #define PHY_TESTDIN(x) UPDATE(x, 7, 0)
143 #define GRF_DPHY0_STATUS 0x0064
144 #define DPHY_PHYLOCK BIT(24)
145 #define PHY_TESTDOUT_SHIFT 8
146 #define GRF_MIPI_TX1_CON 0x0068
147 #define GRF_DPHY1_STATUS 0x006c
148 #define GRF_GPIO0AB_SEL_CON 0x0070
149 #define GRF_GPIO1AB_SEL_CON 0x0074
150 #define GRF_GPIO2AB_SEL_CON 0x0078
151 #define GRF_GPIO2C_SEL_CON 0x007c
152 #define GRF_GPIO3AB_SEL_CON 0x0080
153 #define GRF_GPIO2A_SMT 0x0090
154 #define GRF_GPIO2B_SMT 0x0094
155 #define GRF_GPIO2C_SMT 0x0098
156 #define GRF_GPIO3AB_SMT 0x009c
157 #define GRF_GPIO0A_P_CON 0x00a0
158 #define GRF_GPIO1A_P_CON 0x00a4
159 #define GRF_GPIO2A_P_CON 0x00a8
160 #define GRF_GPIO2B_P_CON 0x00ac
161 #define GRF_GPIO2C_P_CON 0x00b0
162 #define GRF_GPIO3A_P_CON 0x00b4
163 #define GRF_GPIO3B_P_CON 0x00b8
164 #define GRF_GPIO0B_D_CON 0x00c0
165 #define GRF_GPIO1B_D_CON 0x00c4
166 #define GRF_GPIO2A_D0_CON 0x00c8
167 #define GRF_GPIO2A_D1_CON 0x00cc
168 #define GRF_GPIO2B_D0_CON 0x00d0
169 #define GRF_GPIO2B_D1_CON 0x00d4
170 #define GRF_GPIO2C_D0_CON 0x00d8
171 #define GRF_GPIO2C_D1_CON 0x00dc
172 #define GRF_GPIO3A_D0_CON 0x00e0
173 #define GRF_GPIO3A_D1_CON 0x00e4
174 #define GRF_GPIO3B_D_CON 0x00e8
175 #define GRF_GPIO_SR_CON 0x00ec
176 #define GRF_INTR0_EN 0x0100
177 #define GRF_INTR0_CLR_EN 0x0104
178 #define GRF_INTR0_STATUS 0x0108
179 #define GRF_INTR0_RAW_STATUS 0x010c
180 #define GRF_INTR1_EN 0x0110
181 #define GRF_INTR1_CLR_EN 0x0114
182 #define GRF_INTR1_STATUS 0x0118
183 #define GRF_INTR1_RAW_STATUS 0x011c
184 #define GRF_SYSTEM_STATUS0 0x0120
185 /* 0: i2c mode and mcu mode; 1: i2c mode only */
186 #define I2C_ONLY_FLAG BIT(6)
187 #define GRF_SYSTEM_STATUS3 0x012c
188 #define GRF_SYSTEM_STATUS4 0x0130
189 #define GRF_OS_REG0 0x0140
190 #define GRF_OS_REG1 0x0144
191 #define GRF_OS_REG2 0x0148
192 #define GRF_OS_REG3 0x014c
193 #define GRF_SOC_VERSION 0x0150
194 #define GRF_MAX_REGISTER GRF_SOC_VERSION
195
196 enum {
197 COMBTXPHY_MODULEA_EN = BIT(0),
198 COMBTXPHY_MODULEB_EN = BIT(1),
199 };
200
201 enum {
202 OUTPUT_MODE_GVI = 1,
203 OUTPUT_MODE_LVDS,
204 OUTPUT_MODE_HDMI,
205 OUTPUT_MODE_CSI,
206 OUTPUT_MODE_DSI,
207 OUTPUT_MODE_BT1120 = 8,
208 OUTPUT_MODE_RGB = 16,
209 OUTPUT_MODE_YUV = 24,
210 };
211
212 enum {
213 INPUT_MODE_HDMI,
214 INPUT_MODE_BT1120 = 2,
215 INPUT_MODE_RGB,
216 INPUT_MODE_YUV,
217 };
218
219 enum {
220 RK628_DEV_GRF,
221 RK628_DEV_COMBRXPHY,
222 RK628_DEV_HDMIRX = 3,
223 RK628_DEV_CSI,
224 RK628_DEV_DSI0,
225 RK628_DEV_DSI1,
226 RK628_DEV_HDMITX,
227 RK628_DEV_GVI,
228 RK628_DEV_COMBTXPHY,
229 RK628_DEV_ADAPTER,
230 RK628_DEV_EFUSE,
231 RK628_DEV_CRU,
232 RK628_DEV_GPIO0,
233 RK628_DEV_GPIO1,
234 RK628_DEV_GPIO2,
235 RK628_DEV_GPIO3,
236 RK628_DEV_MAX,
237 };
238
239 struct rk628 {
240 struct device *dev;
241 struct i2c_client *client;
242 struct regmap *regmap[RK628_DEV_MAX];
243 void *txphy;
244 };
245
rk628_i2c_write(struct rk628 * rk628,u32 reg,u32 val)246 static inline int rk628_i2c_write(struct rk628 *rk628, u32 reg, u32 val)
247 {
248 int region = (reg >> 16) & 0xff;
249 int ret = 0;
250
251 ret = regmap_write(rk628->regmap[region], reg, val);
252 if (ret < 0)
253 pr_info("%s: i2c err reg=0x%x, val=0x%x, ret=%d\n", __func__, reg, val, ret);
254
255 return ret;
256 }
257
rk628_i2c_read(struct rk628 * rk628,u32 reg,u32 * val)258 static inline int rk628_i2c_read(struct rk628 *rk628, u32 reg, u32 *val)
259 {
260 int region = (reg >> 16) & 0xff;
261 int ret = 0;
262
263 ret = regmap_read(rk628->regmap[region], reg, val);
264 if (ret < 0)
265 pr_info("%s: i2c err reg=0x%x, val=0x%x ret=%d\n", __func__, reg, *val, ret);
266
267 return ret;
268 }
269
rk628_i2c_update_bits(struct rk628 * rk628,u32 reg,u32 mask,u32 val)270 static inline int rk628_i2c_update_bits(struct rk628 *rk628, u32 reg, u32 mask,
271 u32 val)
272 {
273 int region = (reg >> 16) & 0xff;
274
275 return regmap_update_bits(rk628->regmap[region], reg, mask, val);
276 }
277
278 struct rk628 *rk628_i2c_register(struct i2c_client *client);
279 void rk628_post_process_en(struct rk628 *rk628,
280 struct videomode *src,
281 struct videomode *dst,
282 u64 *dst_pclk);
283
284 #endif
285