1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip Audio PWM driver 4 * 5 * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd 6 * 7 */ 8 9 #ifndef _ROCKCHIP_AUDIO_PWM_H 10 #define _ROCKCHIP_AUDIO_PWM_H 11 12 /* AUDIO PWM REGS offset */ 13 #define AUDPWM_VERSION (0x0000) 14 #define AUDPWM_XFER (0x0004) 15 #define AUDPWM_SRC_CFG (0x0008) 16 #define AUDPWM_PWM_CFG (0x0010) 17 #define AUDPWM_PWM_ST (0x0014) 18 #define AUDPWM_PWM_BUF_01 (0x0018) 19 #define AUDPWM_PWM_BUF_23 (0x001c) 20 #define AUDPWM_FIFO_CFG (0x0020) 21 #define AUDPWM_FIFO_LVL (0x0024) 22 #define AUDPWM_FIFO_INT_EN (0x0028) 23 #define AUDPWM_FIFO_INT_ST (0x002c) 24 #define AUDPWM_FIFO_ENTRY (0x0080) 25 26 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) 27 28 /* Transfer Control Register */ 29 #define AUDPWM_XFER_LSTOP HIWORD_UPDATE(1, 1, 1) 30 #define AUDPWM_XFER_START HIWORD_UPDATE(1, 0, 0) 31 #define AUDPWM_XFER_STOP HIWORD_UPDATE(0, 0, 0) 32 33 /* Source Data Configuration Register */ 34 #define AUDPWM_ALIGN_LEFT HIWORD_UPDATE(1, 5, 5) 35 #define AUDPWM_ALIGN_RIGHT HIWORD_UPDATE(0, 5, 5) 36 #define AUDPWM_SRC_WIDTH(x) HIWORD_UPDATE((x) - 1, 4, 0) 37 38 /* PWM Configuration Register */ 39 #define AUDPWM_SAMPLE_WIDTH(x) HIWORD_UPDATE((x) - 8, 9, 8) 40 #define AUDPWM_LINEAR_INTERP_EN HIWORD_UPDATE(1, 4, 4) 41 #define AUDPWM_INTERP_RATE(x) HIWORD_UPDATE((x), 3, 0) 42 43 /* FIFO Configuration Register */ 44 #define AUDPWM_DMA_EN HIWORD_UPDATE(1, 7, 7) 45 #define AUDPWM_DMA_DIS HIWORD_UPDATE(0, 7, 7) 46 #define AUDPWM_DMA_WATERMARK(x) HIWORD_UPDATE((x) - 1, 4, 0) 47 48 #endif /* _ROCKCHIP_AUDIO_PWM_H */ 49