1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 6*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 7*4882a593Smuzhiyun * (at your option) any later version. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 10*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*4882a593Smuzhiyun * GNU General Public License for more details. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __RK618_H__ 16*4882a593Smuzhiyun #define __RK618_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <linux/clk.h> 19*4882a593Smuzhiyun #include <linux/delay.h> 20*4882a593Smuzhiyun #include <linux/regmap.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 23*4882a593Smuzhiyun #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define RK618_LVDS_CON 0x0084 26*4882a593Smuzhiyun #define LVDS_CON_START_PHASE(x) HIWORD_UPDATE(x, 14, 14) 27*4882a593Smuzhiyun #define LVDS_DCLK_INV HIWORD_UPDATE(1, 13, 13) 28*4882a593Smuzhiyun #define LVDS_CON_CHADS_10PF HIWORD_UPDATE(3, 12, 11) 29*4882a593Smuzhiyun #define LVDS_CON_CHADS_5PF HIWORD_UPDATE(2, 12, 11) 30*4882a593Smuzhiyun #define LVDS_CON_CHADS_7PF HIWORD_UPDATE(1, 12, 11) 31*4882a593Smuzhiyun #define LVDS_CON_CHADS_3PF HIWORD_UPDATE(0, 12, 11) 32*4882a593Smuzhiyun #define LVDS_CON_CHA1TTL_ENABLE HIWORD_UPDATE(1, 10, 10) 33*4882a593Smuzhiyun #define LVDS_CON_CHA1TTL_DISABLE HIWORD_UPDATE(0, 10, 10) 34*4882a593Smuzhiyun #define LVDS_CON_CHA0TTL_ENABLE HIWORD_UPDATE(1, 9, 9) 35*4882a593Smuzhiyun #define LVDS_CON_CHA0TTL_DISABLE HIWORD_UPDATE(0, 9, 9) 36*4882a593Smuzhiyun #define LVDS_CON_CHA1_POWER_UP HIWORD_UPDATE(1, 8, 8) 37*4882a593Smuzhiyun #define LVDS_CON_CHA1_POWER_DOWN HIWORD_UPDATE(0, 8, 8) 38*4882a593Smuzhiyun #define LVDS_CON_CHA0_POWER_UP HIWORD_UPDATE(1, 7, 7) 39*4882a593Smuzhiyun #define LVDS_CON_CHA0_POWER_DOWN HIWORD_UPDATE(0, 7, 7) 40*4882a593Smuzhiyun #define LVDS_CON_CBG_POWER_UP HIWORD_UPDATE(1, 6, 6) 41*4882a593Smuzhiyun #define LVDS_CON_CBG_POWER_DOWN HIWORD_UPDATE(0, 6, 6) 42*4882a593Smuzhiyun #define LVDS_CON_PLL_POWER_DOWN HIWORD_UPDATE(1, 5, 5) 43*4882a593Smuzhiyun #define LVDS_CON_PLL_POWER_UP HIWORD_UPDATE(0, 5, 5) 44*4882a593Smuzhiyun #define LVDS_CON_START_SEL_EVEN_PIXEL HIWORD_UPDATE(1, 4, 4) 45*4882a593Smuzhiyun #define LVDS_CON_START_SEL_ODD_PIXEL HIWORD_UPDATE(0, 4, 4) 46*4882a593Smuzhiyun #define LVDS_CON_CHASEL_DOUBLE_CHANNEL HIWORD_UPDATE(1, 3, 3) 47*4882a593Smuzhiyun #define LVDS_CON_CHASEL_SINGLE_CHANNEL HIWORD_UPDATE(0, 3, 3) 48*4882a593Smuzhiyun #define LVDS_CON_MSBSEL_D7 HIWORD_UPDATE(1, 2, 2) 49*4882a593Smuzhiyun #define LVDS_CON_MSBSEL_D0 HIWORD_UPDATE(0, 2, 2) 50*4882a593Smuzhiyun #define LVDS_CON_SELECT(x) HIWORD_UPDATE(x, 1, 0) 51*4882a593Smuzhiyun #define LVDS_CON_SELECT_6BIT_MODE HIWORD_UPDATE(3, 1, 0) 52*4882a593Smuzhiyun #define LVDS_CON_SELECT_8BIT_MODE_3 HIWORD_UPDATE(2, 1, 0) 53*4882a593Smuzhiyun #define LVDS_CON_SELECT_8BIT_MODE_2 HIWORD_UPDATE(1, 1, 0) 54*4882a593Smuzhiyun #define LVDS_CON_SELECT_8BIT_MODE_1 HIWORD_UPDATE(0, 1, 0) 55*4882a593Smuzhiyun #define RK618_IO_CON0 0x0088 56*4882a593Smuzhiyun #define VIF1_SYNC_MODE_ENABLE HIWORD_UPDATE(1, 15, 15) 57*4882a593Smuzhiyun #define VIF1_SYNC_MODE_DISABLE HIWORD_UPDATE(0, 15, 15) 58*4882a593Smuzhiyun #define VIF0_SYNC_MODE_ENABLE HIWORD_UPDATE(1, 14, 14) 59*4882a593Smuzhiyun #define VIF0_SYNC_MODE_DISABLE HIWORD_UPDATE(0, 14, 14) 60*4882a593Smuzhiyun #define PORT2_OUTPUT_LVDS HIWORD_UPDATE(1, 11, 11) 61*4882a593Smuzhiyun #define PORT2_OUTPUT_TTL HIWORD_UPDATE(0, 11, 11) 62*4882a593Smuzhiyun #define PORT1_OUTPUT_TTL_DISABLE HIWORD_UPDATE(1, 10, 10) 63*4882a593Smuzhiyun #define PORT1_OUTPUT_TTL_ENABLE HIWORD_UPDATE(0, 10, 10) 64*4882a593Smuzhiyun #define PORT2_IO_PULL_DOWN_DISABLE HIWORD_UPDATE(1, 9, 9) 65*4882a593Smuzhiyun #define PORT2_IO_PULL_DOWN_ENABLE HIWORD_UPDATE(0, 9, 9) 66*4882a593Smuzhiyun #define PORT1_IO_PULL_DOWN_DISABLE HIWORD_UPDATE(1, 8, 8) 67*4882a593Smuzhiyun #define PORT1_IO_PULL_DOWN_ENABLE HIWORD_UPDATE(0, 8, 8) 68*4882a593Smuzhiyun #define PORT0_IO_PULL_DOWN_DISABLE HIWORD_UPDATE(1, 7, 7) 69*4882a593Smuzhiyun #define PORT0_IO_PULL_DOWN_ENABLE HIWORD_UPDATE(0, 7, 7) 70*4882a593Smuzhiyun #define HDMI_IO_PULL_UP_DISABLE HIWORD_UPDATE(1, 6, 6) 71*4882a593Smuzhiyun #define HDMI_IO_PULL_UP_ENABLE HIWORD_UPDATE(0, 6, 6) 72*4882a593Smuzhiyun #define I2C_IO_PULL_UP_DISABLE HIWORD_UPDATE(1, 2, 2) 73*4882a593Smuzhiyun #define I2C_IO_PULL_UP_ENABLE HIWORD_UPDATE(0, 2, 2) 74*4882a593Smuzhiyun #define INT_IO_PULL_UP HIWORD_UPDATE(1, 1, 1) 75*4882a593Smuzhiyun #define INT_IO_PULL_DOWN HIWORD_UPDATE(0, 1, 1) 76*4882a593Smuzhiyun #define CLKIN_IO_PULL_UP HIWORD_UPDATE(1, 0, 0) 77*4882a593Smuzhiyun #define CLKIN_IO_PULL_DOWN HIWORD_UPDATE(0, 0, 0) 78*4882a593Smuzhiyun #define RK618_IO_CON1 0x008c 79*4882a593Smuzhiyun #define PORT2_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 9, 9) 80*4882a593Smuzhiyun #define PORT2_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 9, 9) 81*4882a593Smuzhiyun #define PORT1_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 8, 8) 82*4882a593Smuzhiyun #define PORT1_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 8, 8) 83*4882a593Smuzhiyun #define PORT0_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 7, 7) 84*4882a593Smuzhiyun #define PORT0_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 7, 7) 85*4882a593Smuzhiyun #define HDMI_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 6, 6) 86*4882a593Smuzhiyun #define HDMI_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 6, 6) 87*4882a593Smuzhiyun #define I2C_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 2, 2) 88*4882a593Smuzhiyun #define I2C_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 2, 2) 89*4882a593Smuzhiyun #define INT_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 1, 1) 90*4882a593Smuzhiyun #define INT_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 1, 1) 91*4882a593Smuzhiyun #define CLKIN_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 0, 0) 92*4882a593Smuzhiyun #define CLKIN_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 0, 0) 93*4882a593Smuzhiyun #define RK618_MISC_CON 0x009c 94*4882a593Smuzhiyun #define HDMI_INT_STATUS BIT(20) 95*4882a593Smuzhiyun #define MIPI_INT_STATUS BIT(19) 96*4882a593Smuzhiyun #define MIPI_EDPI_HALT BIT(16) 97*4882a593Smuzhiyun #define HDMI_HSYNC_POL_INV BIT(15) 98*4882a593Smuzhiyun #define HDMI_VSYNC_POL_INV BIT(14) 99*4882a593Smuzhiyun #define HDMI_CLK_SEL_MASK GENMASK(13, 12) 100*4882a593Smuzhiyun #define HDMI_CLK_SEL_VIDEO_INF0_CLK UPDATE(2, 13, 12) 101*4882a593Smuzhiyun #define HDMI_CLK_SEL_SCALER_CLK UPDATE(1, 13, 12) 102*4882a593Smuzhiyun #define HDMI_CLK_SEL_VIDEO_INF1_CLK 0 103*4882a593Smuzhiyun #define INT_ACTIVE_LOW BIT(5) 104*4882a593Smuzhiyun #define INT_ACTIVE_HIGH 0 105*4882a593Smuzhiyun #define DOUBLE_CH_LVDS_DEN_POLARITY BIT(4) 106*4882a593Smuzhiyun #define DOUBLE_CH_LVDS_DEN_LOW BIT(4) 107*4882a593Smuzhiyun #define DOUBLE_CH_LVDS_DEN_HIGH 0 108*4882a593Smuzhiyun #define DOUBLE_CH_LVDS_HSYNC_POLARITY BIT(3) 109*4882a593Smuzhiyun #define DOUBLE_CH_LVDS_HSYNC_LOW BIT(3) 110*4882a593Smuzhiyun #define DOUBLE_CH_LVDS_HSYNC_HIGH 0 111*4882a593Smuzhiyun #define MIPI_DPICOLOM BIT(2) 112*4882a593Smuzhiyun #define MIPI_DPISHUTDN BIT(1) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun struct rk618 { 115*4882a593Smuzhiyun struct device *dev; 116*4882a593Smuzhiyun struct i2c_client *client; 117*4882a593Smuzhiyun struct clk *clkin; 118*4882a593Smuzhiyun struct regmap *regmap; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct regulator *supply; 121*4882a593Smuzhiyun struct gpio_desc *enable_gpio; 122*4882a593Smuzhiyun struct gpio_desc *reset_gpio; /* power on reset */ 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #endif 126