1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip usb PHY driver
4 *
5 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
6 * Copyright (C) 2014 ROCKCHIP, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/extcon-provider.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/power_supply.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/regmap.h>
29 #include <linux/usb/of.h>
30 #include <linux/wakelock.h>
31
32 static int enable_usb_uart;
33
34 #define HIWORD_UPDATE(val, mask) \
35 ((val) | (mask) << 16)
36
37 #define UOC_CON0 0x00
38 #define UOC_CON0_SIDDQ BIT(13)
39 #define UOC_CON0_DISABLE BIT(4)
40 #define UOC_CON0_COMMON_ON_N BIT(0)
41
42 #define UOC_CON2 0x08
43 #define UOC_CON2_SOFT_CON_SEL BIT(2)
44
45 #define UOC_CON3 0x0c
46 /* bits present on rk3188 and rk3288 phys */
47 #define UOC_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
48 #define UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC (1 << 3)
49 #define UOC_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
50 #define UOC_CON3_UTMI_OPMODE_NODRIVING (1 << 1)
51 #define UOC_CON3_UTMI_OPMODE_MASK (3 << 1)
52 #define UOC_CON3_UTMI_SUSPENDN BIT(0)
53
54 #define RK3288_UOC0_CON0 0x320
55 #define RK3288_UOC0_CON0_COMMON_ON_N BIT(0)
56 #define RK3288_UOC0_CON0_DISABLE BIT(4)
57
58 #define RK3288_UOC0_CON2 0x328
59 #define RK3288_UOC0_CON2_SOFT_CON_SEL BIT(2)
60 #define RK3288_UOC0_CON2_CHRGSEL BIT(5)
61 #define RK3288_UOC0_CON2_VDATDETENB BIT(6)
62 #define RK3288_UOC0_CON2_VDATSRCENB BIT(7)
63 #define RK3288_UOC0_CON2_DCDENB BIT(14)
64
65 #define RK3288_UOC0_CON3 0x32c
66 #define RK3288_UOC0_CON3_UTMI_SUSPENDN BIT(0)
67 #define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING BIT(1)
68 #define RK3288_UOC0_CON3_UTMI_OPMODE_MASK (3 << 1)
69 #define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC BIT(3)
70 #define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
71 #define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
72 #define RK3288_UOC0_CON3_BYPASSDMEN BIT(6)
73 #define RK3288_UOC0_CON3_BYPASSSEL BIT(7)
74 #define RK3288_UOC0_CON3_IDDIG_SET_OTG (0 << 12)
75 #define RK3288_UOC0_CON3_IDDIG_SET_HOST (2 << 12)
76 #define RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL (3 << 12)
77 #define RK3288_UOC0_CON3_IDDIG_SET_MASK (3 << 12)
78
79 #define RK3288_UOC0_CON4 0x330
80 #define RK3288_UOC0_CON4_BVALID_IRQ_EN BIT(2)
81 #define RK3288_UOC0_CON4_BVALID_IRQ_PD BIT(3)
82
83 #define RK3288_SOC_STATUS2 0x288
84 #define RK3288_SOC_STATUS2_UTMISRP_BVALID BIT(14)
85 #define RK3288_SOC_STATUS2_UTMIOTG_IDDIG BIT(17)
86
87 #define RK3288_SOC_STATUS19 0x2cc
88 #define RK3288_SOC_STATUS19_CHGDET BIT(23)
89 #define RK3288_SOC_STATUS19_FSVPLUS BIT(24)
90 #define RK3288_SOC_STATUS19_FSVMINUS BIT(25)
91
92 #define OTG_SCHEDULE_DELAY (1 * HZ)
93 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
94 #define CHG_DCD_MAX_RETRIES 6
95 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
96 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
97
98 enum usb_chg_state {
99 USB_CHG_STATE_UNDEFINED = 0,
100 USB_CHG_STATE_WAIT_FOR_DCD,
101 USB_CHG_STATE_DCD_DONE,
102 USB_CHG_STATE_PRIMARY_DONE,
103 USB_CHG_STATE_SECONDARY_DONE,
104 USB_CHG_STATE_DETECTED,
105 };
106
107 static const unsigned int rockchip_usb_phy_extcon_cable[] = {
108 EXTCON_USB,
109 EXTCON_USB_HOST,
110 EXTCON_USB_VBUS_EN,
111 EXTCON_CHG_USB_SDP,
112 EXTCON_CHG_USB_CDP,
113 EXTCON_CHG_USB_DCP,
114 EXTCON_NONE,
115 };
116
117 struct rockchip_usb_phys {
118 int reg;
119 const char *pll_name;
120 };
121
122 struct rockchip_usb_phy_base;
123 struct rockchip_usb_phy_pdata {
124 struct rockchip_usb_phys *phys;
125 int (*init_usb_uart)(struct regmap *grf,
126 const struct rockchip_usb_phy_pdata *pdata);
127 int usb_uart_phy;
128 };
129
130 struct rockchip_usb_phy_base {
131 struct device *dev;
132 struct regmap *reg_base;
133 struct extcon_dev *edev;
134 const struct rockchip_usb_phy_pdata *pdata;
135 };
136
137 struct rockchip_usb_phy {
138 struct rockchip_usb_phy_base *base;
139 struct device_node *np;
140 unsigned int reg_offset;
141 struct clk *clk;
142 struct clk *clk480m;
143 struct clk_hw clk480m_hw;
144 struct phy *phy;
145 bool uart_enabled;
146 int bvalid_irq;
147 struct reset_control *reset;
148 struct regulator *vbus;
149 struct mutex mutex; /* protects registers of phy */
150 struct delayed_work chg_work;
151 struct delayed_work otg_sm_work;
152 struct wake_lock wakelock;
153 enum usb_chg_state chg_state;
154 enum power_supply_type chg_type;
155 enum usb_dr_mode mode;
156 };
157
otg_mode_show(struct device * dev,struct device_attribute * attr,char * buf)158 static ssize_t otg_mode_show(struct device *dev,
159 struct device_attribute *attr, char *buf)
160 {
161 struct rockchip_usb_phy *rk_phy = dev_get_drvdata(dev);
162
163 if (!rk_phy) {
164 dev_err(dev, "Fail to get otg phy.\n");
165 return -EINVAL;
166 }
167
168 switch (rk_phy->mode) {
169 case USB_DR_MODE_HOST:
170 return sprintf(buf, "host\n");
171 case USB_DR_MODE_PERIPHERAL:
172 return sprintf(buf, "peripheral\n");
173 case USB_DR_MODE_OTG:
174 return sprintf(buf, "otg\n");
175 case USB_DR_MODE_UNKNOWN:
176 return sprintf(buf, "UNKNOWN\n");
177 default:
178 break;
179 }
180
181 return -EINVAL;
182 }
183
otg_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)184 static ssize_t otg_mode_store(struct device *dev, struct device_attribute *attr,
185 const char *buf, size_t count)
186 {
187 struct rockchip_usb_phy *rk_phy = dev_get_drvdata(dev);
188 enum usb_dr_mode new_dr_mode;
189 int ret = count;
190 int val = 0;
191
192 if (!rk_phy) {
193 dev_err(dev, "Fail to get otg phy.\n");
194 return -EINVAL;
195 }
196
197 mutex_lock(&rk_phy->mutex);
198
199 if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
200 new_dr_mode = USB_DR_MODE_OTG;
201 } else if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
202 new_dr_mode = USB_DR_MODE_HOST;
203 } else if (!strncmp(buf, "2", 1) || !strncmp(buf, "peripheral", 10)) {
204 new_dr_mode = USB_DR_MODE_PERIPHERAL;
205 } else {
206 dev_err(&rk_phy->phy->dev, "Error mode! Input 'otg' or 'host' or 'peripheral'\n");
207 ret = -EINVAL;
208 goto out_unlock;
209 }
210
211 if (rk_phy->mode == new_dr_mode) {
212 dev_warn(&rk_phy->phy->dev, "Same as current mode.\n");
213 goto out_unlock;
214 }
215
216 rk_phy->mode = new_dr_mode;
217
218 switch (rk_phy->mode) {
219 case USB_DR_MODE_HOST:
220 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_HOST,
221 RK3288_UOC0_CON3_IDDIG_SET_MASK);
222 break;
223 case USB_DR_MODE_PERIPHERAL:
224 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL,
225 RK3288_UOC0_CON3_IDDIG_SET_MASK);
226 break;
227 case USB_DR_MODE_OTG:
228 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_OTG,
229 RK3288_UOC0_CON3_IDDIG_SET_MASK);
230 break;
231 default:
232 break;
233 }
234
235 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
236
237 out_unlock:
238 mutex_unlock(&rk_phy->mutex);
239
240 return ret;
241 }
242
243 static DEVICE_ATTR_RW(otg_mode);
244
245 /* Group all the usb2 phy attributes */
246 static struct attribute *usb2_phy_attrs[] = {
247 &dev_attr_otg_mode.attr,
248 NULL,
249 };
250
251 static struct attribute_group usb2_phy_attr_group = {
252 .name = NULL, /* we want them in the same directory */
253 .attrs = usb2_phy_attrs,
254 };
255
rockchip_usb_phy_power(struct rockchip_usb_phy * phy,bool siddq)256 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
257 bool siddq)
258 {
259 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
260
261 return regmap_write(phy->base->reg_base, phy->reg_offset, val);
262 }
263
rockchip_usb_phy480m_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)264 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
265 unsigned long parent_rate)
266 {
267 return 480000000;
268 }
269
rockchip_usb_phy480m_disable(struct clk_hw * hw)270 static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
271 {
272 struct rockchip_usb_phy *phy = container_of(hw,
273 struct rockchip_usb_phy,
274 clk480m_hw);
275
276 if (phy->vbus)
277 regulator_disable(phy->vbus);
278
279 /* Power down usb phy analog blocks by set siddq 1 */
280 rockchip_usb_phy_power(phy, 1);
281 }
282
rockchip_usb_phy480m_enable(struct clk_hw * hw)283 static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
284 {
285 struct rockchip_usb_phy *phy = container_of(hw,
286 struct rockchip_usb_phy,
287 clk480m_hw);
288
289 /* Power up usb phy analog blocks by set siddq 0 */
290 return rockchip_usb_phy_power(phy, 0);
291 }
292
rockchip_usb_phy480m_is_enabled(struct clk_hw * hw)293 static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
294 {
295 struct rockchip_usb_phy *phy = container_of(hw,
296 struct rockchip_usb_phy,
297 clk480m_hw);
298 int ret;
299 u32 val;
300
301 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
302 if (ret < 0)
303 return ret;
304
305 return (val & UOC_CON0_SIDDQ) ? 0 : 1;
306 }
307
308 static const struct clk_ops rockchip_usb_phy480m_ops = {
309 .enable = rockchip_usb_phy480m_enable,
310 .disable = rockchip_usb_phy480m_disable,
311 .is_enabled = rockchip_usb_phy480m_is_enabled,
312 .recalc_rate = rockchip_usb_phy480m_recalc_rate,
313 };
314
rk3288_usb_phy_init(struct phy * _phy)315 static int rk3288_usb_phy_init(struct phy *_phy)
316 {
317 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
318 int ret = 0;
319 unsigned int val;
320
321 if (phy->bvalid_irq > 0) {
322 mutex_lock(&phy->mutex);
323
324 /* clear bvalid status and enable bvalid detect irq */
325 val = HIWORD_UPDATE(RK3288_UOC0_CON4_BVALID_IRQ_EN
326 | RK3288_UOC0_CON4_BVALID_IRQ_PD,
327 RK3288_UOC0_CON4_BVALID_IRQ_EN
328 | RK3288_UOC0_CON4_BVALID_IRQ_PD);
329 ret = regmap_write(phy->base->reg_base, RK3288_UOC0_CON4, val);
330 if (ret) {
331 dev_err(phy->base->dev,
332 "failed to enable bvalid irq\n");
333 goto out;
334 }
335
336 schedule_delayed_work(&phy->otg_sm_work, OTG_SCHEDULE_DELAY);
337
338 out:
339 mutex_unlock(&phy->mutex);
340 }
341
342 return ret;
343 }
344
rk3288_usb_phy_exit(struct phy * _phy)345 static int rk3288_usb_phy_exit(struct phy *_phy)
346 {
347 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
348
349 if (phy->bvalid_irq > 0)
350 flush_delayed_work(&phy->otg_sm_work);
351
352 return 0;
353 }
354
rockchip_usb_phy_power_off(struct phy * _phy)355 static int rockchip_usb_phy_power_off(struct phy *_phy)
356 {
357 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
358
359 if (phy->uart_enabled)
360 return -EBUSY;
361
362 clk_disable_unprepare(phy->clk480m);
363
364 return 0;
365 }
366
rockchip_usb_phy_power_on(struct phy * _phy)367 static int rockchip_usb_phy_power_on(struct phy *_phy)
368 {
369 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
370
371 if (phy->uart_enabled)
372 return -EBUSY;
373
374 if (phy->vbus) {
375 int ret;
376
377 ret = regulator_enable(phy->vbus);
378 if (ret)
379 return ret;
380 }
381
382 return clk_prepare_enable(phy->clk480m);
383 }
384
rockchip_usb_phy_reset(struct phy * _phy)385 static int rockchip_usb_phy_reset(struct phy *_phy)
386 {
387 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
388
389 if (phy->reset) {
390 reset_control_assert(phy->reset);
391 udelay(10);
392 reset_control_deassert(phy->reset);
393 }
394
395 return 0;
396 }
397
398 static struct phy_ops ops = {
399 .power_on = rockchip_usb_phy_power_on,
400 .power_off = rockchip_usb_phy_power_off,
401 .reset = rockchip_usb_phy_reset,
402 .owner = THIS_MODULE,
403 };
404
rockchip_usb_phy_action(void * data)405 static void rockchip_usb_phy_action(void *data)
406 {
407 struct rockchip_usb_phy *rk_phy = data;
408
409 if (!rk_phy->uart_enabled) {
410 of_clk_del_provider(rk_phy->np);
411 clk_unregister(rk_phy->clk480m);
412 }
413
414 if (rk_phy->clk)
415 clk_put(rk_phy->clk);
416 }
417
rockchip_usb_phy_extcon_register(struct rockchip_usb_phy_base * base)418 static int rockchip_usb_phy_extcon_register(struct rockchip_usb_phy_base *base)
419 {
420 int ret;
421 struct device_node *node = base->dev->of_node;
422 struct extcon_dev *edev;
423
424 if (of_property_read_bool(node, "extcon")) {
425 edev = extcon_get_edev_by_phandle(base->dev, 0);
426 if (IS_ERR(edev)) {
427 if (PTR_ERR(edev) != -EPROBE_DEFER)
428 dev_err(base->dev,
429 "Invalid or missing extcon\n");
430 return PTR_ERR(edev);
431 }
432 } else {
433 /* Initialize extcon device */
434 edev = devm_extcon_dev_allocate(base->dev,
435 rockchip_usb_phy_extcon_cable);
436
437 if (IS_ERR(edev))
438 return -ENOMEM;
439
440 ret = devm_extcon_dev_register(base->dev, edev);
441 if (ret) {
442 dev_err(base->dev,
443 "failed to register extcon device\n");
444 return ret;
445 }
446 }
447
448 base->edev = edev;
449
450 return 0;
451 }
452
rk3288_usb_phy_otg_sm_work(struct work_struct * work)453 static void rk3288_usb_phy_otg_sm_work(struct work_struct *work)
454 {
455 struct rockchip_usb_phy *rk_phy = container_of(work,
456 struct rockchip_usb_phy,
457 otg_sm_work.work);
458 unsigned int val;
459 static unsigned int cable;
460 static bool chg_det_completed;
461 bool sch_work;
462 bool vbus_attached;
463 bool id;
464
465 mutex_lock(&rk_phy->mutex);
466
467 sch_work = false;
468
469 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS2, &val);
470 id = (val & RK3288_SOC_STATUS2_UTMIOTG_IDDIG) ? true : false;
471
472 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS2, &val);
473 vbus_attached =
474 (val & RK3288_SOC_STATUS2_UTMISRP_BVALID) ? true : false;
475
476 if (!vbus_attached || !id || rk_phy->mode == USB_DR_MODE_HOST) {
477 dev_dbg(&rk_phy->phy->dev, "peripheral disconnected\n");
478 wake_unlock(&rk_phy->wakelock);
479 extcon_set_state_sync(rk_phy->base->edev, cable, false);
480 rk_phy->chg_state = USB_CHG_STATE_UNDEFINED;
481 chg_det_completed = false;
482 goto out;
483 }
484
485 if (chg_det_completed) {
486 sch_work = true;
487 goto out;
488 }
489
490 switch (rk_phy->chg_state) {
491 case USB_CHG_STATE_UNDEFINED:
492 mutex_unlock(&rk_phy->mutex);
493 schedule_delayed_work(&rk_phy->chg_work, 0);
494 return;
495 case USB_CHG_STATE_DETECTED:
496 switch (rk_phy->chg_type) {
497 case POWER_SUPPLY_TYPE_USB:
498 dev_dbg(&rk_phy->phy->dev, "sdp cable is connected\n");
499 wake_lock(&rk_phy->wakelock);
500 cable = EXTCON_CHG_USB_SDP;
501 sch_work = true;
502 break;
503 case POWER_SUPPLY_TYPE_USB_DCP:
504 dev_dbg(&rk_phy->phy->dev, "dcp cable is connected\n");
505 cable = EXTCON_CHG_USB_DCP;
506 sch_work = true;
507 break;
508 case POWER_SUPPLY_TYPE_USB_CDP:
509 dev_dbg(&rk_phy->phy->dev, "cdp cable is connected\n");
510 wake_lock(&rk_phy->wakelock);
511 cable = EXTCON_CHG_USB_CDP;
512 sch_work = true;
513 break;
514 default:
515 break;
516 }
517 chg_det_completed = true;
518 break;
519 default:
520 break;
521 }
522
523 if (extcon_get_state(rk_phy->base->edev, cable) != vbus_attached)
524 extcon_set_state_sync(rk_phy->base->edev, cable,
525 vbus_attached);
526
527 out:
528 if (sch_work)
529 schedule_delayed_work(&rk_phy->otg_sm_work, OTG_SCHEDULE_DELAY);
530
531 mutex_unlock(&rk_phy->mutex);
532 }
533
chg_to_string(enum power_supply_type chg_type)534 static const char *chg_to_string(enum power_supply_type chg_type)
535 {
536 switch (chg_type) {
537 case POWER_SUPPLY_TYPE_USB:
538 return "USB_SDP_CHARGER";
539 case POWER_SUPPLY_TYPE_USB_DCP:
540 return "USB_DCP_CHARGER";
541 case POWER_SUPPLY_TYPE_USB_CDP:
542 return "USB_CDP_CHARGER";
543 default:
544 return "INVALID_CHARGER";
545 }
546 }
547
rk3288_chg_detect_work(struct work_struct * work)548 static void rk3288_chg_detect_work(struct work_struct *work)
549 {
550 struct rockchip_usb_phy *rk_phy =
551 container_of(work, struct rockchip_usb_phy, chg_work.work);
552 unsigned int val;
553 static int dcd_retries;
554 static int primary_retries;
555 unsigned long delay;
556 bool fsvplus;
557 bool vout;
558 bool tmout;
559
560 dev_dbg(&rk_phy->phy->dev, "chg detection work state = %d\n",
561 rk_phy->chg_state);
562
563 switch (rk_phy->chg_state) {
564 case USB_CHG_STATE_UNDEFINED:
565 mutex_lock(&rk_phy->mutex);
566 /* put the controller in non-driving mode */
567 val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL,
568 RK3288_UOC0_CON2_SOFT_CON_SEL);
569 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
570 val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING,
571 RK3288_UOC0_CON3_UTMI_SUSPENDN
572 | RK3288_UOC0_CON3_UTMI_OPMODE_MASK);
573 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
574 /* Start DCD processing stage 1 */
575 val = HIWORD_UPDATE(RK3288_UOC0_CON2_DCDENB,
576 RK3288_UOC0_CON2_DCDENB);
577 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
578 rk_phy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
579 dcd_retries = 0;
580 primary_retries = 0;
581 delay = CHG_DCD_POLL_TIME;
582 break;
583 case USB_CHG_STATE_WAIT_FOR_DCD:
584 /* get data contact detection status */
585 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
586 fsvplus = (val & RK3288_SOC_STATUS19_FSVPLUS) ? true : false;
587 tmout = ++dcd_retries == CHG_DCD_MAX_RETRIES;
588 /* stage 2 */
589 if (!fsvplus || tmout) {
590 vdpsrc:
591 /* stage 4 */
592 /* Turn off DCD circuitry */
593 val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_DCDENB);
594 regmap_write(rk_phy->base->reg_base,
595 RK3288_UOC0_CON2, val);
596 /* Voltage Source on DP, Probe on DM */
597 val = HIWORD_UPDATE(RK3288_UOC0_CON2_VDATSRCENB
598 | RK3288_UOC0_CON2_VDATDETENB,
599 RK3288_UOC0_CON2_VDATSRCENB
600 | RK3288_UOC0_CON2_VDATDETENB
601 | RK3288_UOC0_CON2_CHRGSEL);
602 regmap_write(rk_phy->base->reg_base,
603 RK3288_UOC0_CON2, val);
604 delay = CHG_PRIMARY_DET_TIME;
605 rk_phy->chg_state = USB_CHG_STATE_DCD_DONE;
606 } else {
607 /* stage 3 */
608 delay = CHG_DCD_POLL_TIME;
609 }
610 break;
611 case USB_CHG_STATE_DCD_DONE:
612 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
613 vout = (val & RK3288_SOC_STATUS19_CHGDET) ? true : false;
614
615 val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_VDATSRCENB
616 | RK3288_UOC0_CON2_VDATDETENB);
617 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
618 if (vout) {
619 /* Voltage Source on DM, Probe on DP */
620 val = HIWORD_UPDATE(RK3288_UOC0_CON2_VDATSRCENB
621 | RK3288_UOC0_CON2_VDATDETENB
622 | RK3288_UOC0_CON2_CHRGSEL,
623 RK3288_UOC0_CON2_VDATSRCENB
624 | RK3288_UOC0_CON2_VDATDETENB
625 | RK3288_UOC0_CON2_CHRGSEL);
626 regmap_write(rk_phy->base->reg_base,
627 RK3288_UOC0_CON2, val);
628 delay = CHG_SECONDARY_DET_TIME;
629 rk_phy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
630 } else {
631 if (dcd_retries == CHG_DCD_MAX_RETRIES) {
632 /* floating charger found */
633 rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
634 rk_phy->chg_state = USB_CHG_STATE_DETECTED;
635 delay = 0;
636 } else if (primary_retries < 2) {
637 primary_retries++;
638 goto vdpsrc;
639 } else {
640 rk_phy->chg_type = POWER_SUPPLY_TYPE_USB;
641 rk_phy->chg_state = USB_CHG_STATE_DETECTED;
642 delay = 0;
643 }
644 }
645 break;
646 case USB_CHG_STATE_PRIMARY_DONE:
647 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
648 vout = (val & RK3288_SOC_STATUS19_CHGDET) ? true : false;
649
650 /* Turn off voltage source */
651 val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_VDATSRCENB
652 | RK3288_UOC0_CON2_VDATDETENB
653 | RK3288_UOC0_CON2_CHRGSEL);
654 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
655 if (vout)
656 rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
657 else
658 rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
659 fallthrough;
660 case USB_CHG_STATE_SECONDARY_DONE:
661 rk_phy->chg_state = USB_CHG_STATE_DETECTED;
662 fallthrough;
663 case USB_CHG_STATE_DETECTED:
664 /* put the controller in normal mode */
665 val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_SOFT_CON_SEL);
666 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
667 val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_SUSPENDN,
668 RK3288_UOC0_CON3_UTMI_SUSPENDN
669 | RK3288_UOC0_CON3_UTMI_OPMODE_MASK);
670 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
671 mutex_unlock(&rk_phy->mutex);
672 rk3288_usb_phy_otg_sm_work(&rk_phy->otg_sm_work.work);
673 dev_info(&rk_phy->phy->dev, "charger = %s\n",
674 chg_to_string(rk_phy->chg_type));
675 return;
676 default:
677 mutex_unlock(&rk_phy->mutex);
678 return;
679 }
680
681 /*
682 * Hold the mutex lock during the whole charger
683 * detection stage, and release it after detect
684 * the charger type.
685 */
686 schedule_delayed_work(&rk_phy->chg_work, delay);
687 }
688
rk3288_usb_phy_bvalid_irq(int irq,void * data)689 static irqreturn_t rk3288_usb_phy_bvalid_irq(int irq, void *data)
690 {
691 struct rockchip_usb_phy *rk_phy = data;
692 int ret;
693 unsigned int val;
694
695 ret = regmap_read(rk_phy->base->reg_base, RK3288_UOC0_CON4, &val);
696 if (ret < 0 || !(val & RK3288_UOC0_CON4_BVALID_IRQ_PD))
697 return IRQ_NONE;
698
699 mutex_lock(&rk_phy->mutex);
700
701 /* clear bvalid detect irq pending status */
702 val = HIWORD_UPDATE(RK3288_UOC0_CON4_BVALID_IRQ_PD,
703 RK3288_UOC0_CON4_BVALID_IRQ_PD);
704 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON4, val);
705
706 mutex_unlock(&rk_phy->mutex);
707
708 if (rk_phy->uart_enabled)
709 goto out;
710
711 cancel_delayed_work_sync(&rk_phy->otg_sm_work);
712 rk3288_usb_phy_otg_sm_work(&rk_phy->otg_sm_work.work);
713 out:
714 return IRQ_HANDLED;
715 }
716
rk3288_usb_phy_probe_init(struct rockchip_usb_phy * rk_phy)717 static int rk3288_usb_phy_probe_init(struct rockchip_usb_phy *rk_phy)
718 {
719 int ret = 0;
720 unsigned int val;
721
722 if (rk_phy->reg_offset == 0x320) {
723 /* Enable Bvalid interrupt and charge detection */
724 ops.init = rk3288_usb_phy_init;
725 ops.exit = rk3288_usb_phy_exit;
726 rk_phy->bvalid_irq = of_irq_get_byname(rk_phy->np,
727 "otg-bvalid");
728 regmap_read(rk_phy->base->reg_base, RK3288_UOC0_CON4, &val);
729 if (rk_phy->bvalid_irq <= 0) {
730 dev_err(&rk_phy->phy->dev,
731 "no vbus valid irq provided\n");
732 ret = -EINVAL;
733 goto out;
734 }
735
736 ret = devm_request_threaded_irq(rk_phy->base->dev,
737 rk_phy->bvalid_irq,
738 NULL,
739 rk3288_usb_phy_bvalid_irq,
740 IRQF_ONESHOT,
741 "rockchip_usb_phy_bvalid",
742 rk_phy);
743 if (ret) {
744 dev_err(&rk_phy->phy->dev,
745 "failed to request otg-bvalid irq handle\n");
746 goto out;
747 }
748
749 rk_phy->chg_state = USB_CHG_STATE_UNDEFINED;
750 wake_lock_init(&rk_phy->wakelock, WAKE_LOCK_SUSPEND,
751 "rockchip_otg");
752 INIT_DELAYED_WORK(&rk_phy->chg_work, rk3288_chg_detect_work);
753 INIT_DELAYED_WORK(&rk_phy->otg_sm_work,
754 rk3288_usb_phy_otg_sm_work);
755
756 rk_phy->mode = of_usb_get_dr_mode_by_phy(rk_phy->np, -1);
757 if (rk_phy->mode == USB_DR_MODE_OTG ||
758 rk_phy->mode == USB_DR_MODE_UNKNOWN) {
759 ret = sysfs_create_group(&rk_phy->phy->dev.kobj,
760 &usb2_phy_attr_group);
761 if (ret) {
762 dev_err(&rk_phy->phy->dev,
763 "Cannot create sysfs group\n");
764 goto out;
765 }
766 }
767 } else if (rk_phy->reg_offset == 0x334) {
768 /*
769 * Setting the COMMONONN to 1'b0 for EHCI PHY on RK3288 SoC.
770 *
771 * EHCI (auto) suspend causes the corresponding usb-phy into
772 * suspend mode which would power down the inner PLL blocks in
773 * usb-phy if the COMMONONN is set to 1'b1. The PLL output
774 * clocks contained CLK480M, CLK12MOHCI, CLK48MOHCI, PHYCLOCK0
775 * and so on, these clocks are not only supplied for EHCI and
776 * OHCI, but also supplied for GPU and other external modules,
777 * so setting COMMONONN to 1'b0 to keep the inner PLL blocks in
778 * usb-phy always powered.
779 */
780 regmap_write(rk_phy->base->reg_base, rk_phy->reg_offset,
781 BIT(16));
782 }
783 out:
784 return ret;
785 }
786
rockchip_usb_phy_init(struct rockchip_usb_phy_base * base,struct device_node * child)787 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
788 struct device_node *child)
789 {
790 struct device_node *np = base->dev->of_node;
791 struct rockchip_usb_phy *rk_phy;
792 unsigned int reg_offset;
793 const char *clk_name;
794 struct clk_init_data init = {};
795 int err, i;
796
797 rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
798 if (!rk_phy)
799 return -ENOMEM;
800
801 rk_phy->base = base;
802 rk_phy->np = child;
803 mutex_init(&rk_phy->mutex);
804
805 if (of_property_read_u32(child, "reg", ®_offset)) {
806 dev_err(base->dev, "missing reg property in node %pOFn\n",
807 child);
808 return -EINVAL;
809 }
810
811 rk_phy->reset = of_reset_control_get(child, "phy-reset");
812 if (IS_ERR(rk_phy->reset))
813 rk_phy->reset = NULL;
814
815 rk_phy->reg_offset = reg_offset;
816
817 rk_phy->clk = of_clk_get_by_name(child, "phyclk");
818 if (IS_ERR(rk_phy->clk))
819 rk_phy->clk = NULL;
820
821 i = 0;
822 init.name = NULL;
823 while (base->pdata->phys[i].reg) {
824 if (base->pdata->phys[i].reg == reg_offset) {
825 init.name = base->pdata->phys[i].pll_name;
826 break;
827 }
828 i++;
829 }
830
831 if (!init.name) {
832 dev_err(base->dev, "phy data not found\n");
833 return -EINVAL;
834 }
835
836 if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
837 dev_dbg(base->dev, "phy%d used as uart output\n", i);
838 rk_phy->uart_enabled = true;
839 } else {
840 if (rk_phy->clk) {
841 clk_name = __clk_get_name(rk_phy->clk);
842 init.flags = 0;
843 init.parent_names = &clk_name;
844 init.num_parents = 1;
845 } else {
846 init.flags = 0;
847 init.parent_names = NULL;
848 init.num_parents = 0;
849 }
850
851 init.ops = &rockchip_usb_phy480m_ops;
852 rk_phy->clk480m_hw.init = &init;
853
854 rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
855 if (IS_ERR(rk_phy->clk480m)) {
856 err = PTR_ERR(rk_phy->clk480m);
857 goto err_clk;
858 }
859
860 err = of_clk_add_provider(child, of_clk_src_simple_get,
861 rk_phy->clk480m);
862 if (err < 0)
863 goto err_clk_prov;
864 }
865
866 err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action,
867 rk_phy);
868 if (err)
869 return err;
870
871 rk_phy->phy = devm_phy_create(base->dev, child, &ops);
872 if (IS_ERR(rk_phy->phy)) {
873 dev_err(base->dev, "failed to create PHY\n");
874 return PTR_ERR(rk_phy->phy);
875 }
876 phy_set_drvdata(rk_phy->phy, rk_phy);
877
878 if (of_device_is_compatible(np, "rockchip,rk3288-usb-phy")) {
879 err = rk3288_usb_phy_probe_init(rk_phy);
880 if (err)
881 return err;
882 }
883
884 rk_phy->vbus = devm_regulator_get_optional(&rk_phy->phy->dev, "vbus");
885 if (IS_ERR(rk_phy->vbus)) {
886 if (PTR_ERR(rk_phy->vbus) == -EPROBE_DEFER)
887 return PTR_ERR(rk_phy->vbus);
888 rk_phy->vbus = NULL;
889 }
890
891 /*
892 * When acting as uart-pipe, just keep clock on otherwise
893 * only power up usb phy when it use, so disable it when init
894 */
895 if (rk_phy->uart_enabled)
896 return clk_prepare_enable(rk_phy->clk);
897 else
898 return rockchip_usb_phy_power(rk_phy, 1);
899
900 err_clk_prov:
901 if (!rk_phy->uart_enabled)
902 clk_unregister(rk_phy->clk480m);
903 err_clk:
904 if (rk_phy->clk)
905 clk_put(rk_phy->clk);
906 return err;
907 }
908
909 static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
910 .phys = (struct rockchip_usb_phys[]){
911 { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
912 { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
913 { /* sentinel */ }
914 },
915 };
916
rockchip_init_usb_uart_common(struct regmap * grf,const struct rockchip_usb_phy_pdata * pdata)917 static int __init rockchip_init_usb_uart_common(struct regmap *grf,
918 const struct rockchip_usb_phy_pdata *pdata)
919 {
920 int regoffs = pdata->phys[pdata->usb_uart_phy].reg;
921 int ret;
922 u32 val;
923
924 /*
925 * COMMON_ON and DISABLE settings are described in the TRM,
926 * but were not present in the original code.
927 * Also disable the analog phy components to save power.
928 */
929 val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N
930 | UOC_CON0_DISABLE
931 | UOC_CON0_SIDDQ,
932 UOC_CON0_COMMON_ON_N
933 | UOC_CON0_DISABLE
934 | UOC_CON0_SIDDQ);
935 ret = regmap_write(grf, regoffs + UOC_CON0, val);
936 if (ret)
937 return ret;
938
939 val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL,
940 UOC_CON2_SOFT_CON_SEL);
941 ret = regmap_write(grf, regoffs + UOC_CON2, val);
942 if (ret)
943 return ret;
944
945 val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING
946 | UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC
947 | UOC_CON3_UTMI_TERMSEL_FULLSPEED,
948 UOC_CON3_UTMI_SUSPENDN
949 | UOC_CON3_UTMI_OPMODE_MASK
950 | UOC_CON3_UTMI_XCVRSEELCT_MASK
951 | UOC_CON3_UTMI_TERMSEL_FULLSPEED);
952 ret = regmap_write(grf, UOC_CON3, val);
953 if (ret)
954 return ret;
955
956 return 0;
957 }
958
959 #define RK3188_UOC0_CON0 0x10c
960 #define RK3188_UOC0_CON0_BYPASSSEL BIT(9)
961 #define RK3188_UOC0_CON0_BYPASSDMEN BIT(8)
962
963 /*
964 * Enable the bypass of uart2 data through the otg usb phy.
965 * See description of rk3288-variant for details.
966 */
rk3188_init_usb_uart(struct regmap * grf,const struct rockchip_usb_phy_pdata * pdata)967 static int __init rk3188_init_usb_uart(struct regmap *grf,
968 const struct rockchip_usb_phy_pdata *pdata)
969 {
970 u32 val;
971 int ret;
972
973 ret = rockchip_init_usb_uart_common(grf, pdata);
974 if (ret)
975 return ret;
976
977 val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL
978 | RK3188_UOC0_CON0_BYPASSDMEN,
979 RK3188_UOC0_CON0_BYPASSSEL
980 | RK3188_UOC0_CON0_BYPASSDMEN);
981 ret = regmap_write(grf, RK3188_UOC0_CON0, val);
982 if (ret)
983 return ret;
984
985 return 0;
986 }
987
988 static const struct rockchip_usb_phy_pdata rk3188_pdata = {
989 .phys = (struct rockchip_usb_phys[]){
990 { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
991 { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
992 { /* sentinel */ }
993 },
994 .init_usb_uart = rk3188_init_usb_uart,
995 .usb_uart_phy = 0,
996 };
997
998 /*
999 * Enable the bypass of uart2 data through the otg usb phy.
1000 * Original description in the TRM.
1001 * 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
1002 * 2. Disable the pull-up resistance on the D+ line by setting
1003 * OPMODE0[1:0] to 2’b01.
1004 * 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
1005 * mode, set COMMONONN to 1’b1.
1006 * 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
1007 * 5. Set BYPASSSEL0 to 1’b1.
1008 * 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
1009 * To receive data, monitor FSVPLUS0.
1010 *
1011 * The actual code in the vendor kernel does some things differently.
1012 */
rk3288_init_usb_uart(struct regmap * grf,const struct rockchip_usb_phy_pdata * pdata)1013 static int __init rk3288_init_usb_uart(struct regmap *grf,
1014 const struct rockchip_usb_phy_pdata *pdata)
1015 {
1016 u32 val;
1017 int ret;
1018
1019 ret = rockchip_init_usb_uart_common(grf, pdata);
1020 if (ret)
1021 return ret;
1022
1023 val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
1024 | RK3288_UOC0_CON3_BYPASSDMEN,
1025 RK3288_UOC0_CON3_BYPASSSEL
1026 | RK3288_UOC0_CON3_BYPASSDMEN);
1027 ret = regmap_write(grf, RK3288_UOC0_CON3, val);
1028 if (ret)
1029 return ret;
1030
1031 return 0;
1032 }
1033
1034 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
1035 .phys = (struct rockchip_usb_phys[]){
1036 { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
1037 { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
1038 { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
1039 { /* sentinel */ }
1040 },
1041 .init_usb_uart = rk3288_init_usb_uart,
1042 .usb_uart_phy = 0,
1043 };
1044
rockchip_usb_phy_probe(struct platform_device * pdev)1045 static int rockchip_usb_phy_probe(struct platform_device *pdev)
1046 {
1047 struct device *dev = &pdev->dev;
1048 struct rockchip_usb_phy_base *phy_base;
1049 struct phy_provider *phy_provider;
1050 const struct of_device_id *match;
1051 struct device_node *child;
1052 int err;
1053
1054 phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
1055 if (!phy_base)
1056 return -ENOMEM;
1057
1058 match = of_match_device(dev->driver->of_match_table, dev);
1059 if (!match || !match->data) {
1060 dev_err(dev, "missing phy data\n");
1061 return -EINVAL;
1062 }
1063
1064 phy_base->pdata = match->data;
1065
1066 phy_base->dev = dev;
1067 phy_base->reg_base = ERR_PTR(-ENODEV);
1068 if (dev->parent && dev->parent->of_node)
1069 phy_base->reg_base = syscon_node_to_regmap(
1070 dev->parent->of_node);
1071 if (IS_ERR(phy_base->reg_base))
1072 phy_base->reg_base = syscon_regmap_lookup_by_phandle(
1073 dev->of_node, "rockchip,grf");
1074 if (IS_ERR(phy_base->reg_base)) {
1075 dev_err(&pdev->dev, "Missing rockchip,grf property\n");
1076 return PTR_ERR(phy_base->reg_base);
1077 }
1078
1079 err = rockchip_usb_phy_extcon_register(phy_base);
1080 if (err)
1081 return err;
1082
1083 for_each_available_child_of_node(dev->of_node, child) {
1084 err = rockchip_usb_phy_init(phy_base, child);
1085 if (err) {
1086 of_node_put(child);
1087 return err;
1088 }
1089 }
1090
1091 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1092
1093 return PTR_ERR_OR_ZERO(phy_provider);
1094 }
1095
1096 static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
1097 { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
1098 { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
1099 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
1100 {}
1101 };
1102
1103 MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
1104
1105 static struct platform_driver rockchip_usb_driver = {
1106 .probe = rockchip_usb_phy_probe,
1107 .driver = {
1108 .name = "rockchip-usb-phy",
1109 .of_match_table = rockchip_usb_phy_dt_ids,
1110 },
1111 };
1112
1113 module_platform_driver(rockchip_usb_driver);
1114
1115 #ifndef MODULE
rockchip_init_usb_uart(void)1116 static int __init rockchip_init_usb_uart(void)
1117 {
1118 const struct of_device_id *match;
1119 const struct rockchip_usb_phy_pdata *data;
1120 struct device_node *np;
1121 struct regmap *grf;
1122 int ret;
1123
1124 if (!enable_usb_uart)
1125 return 0;
1126
1127 np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
1128 &match);
1129 if (!np) {
1130 pr_err("%s: failed to find usbphy node\n", __func__);
1131 return -ENOTSUPP;
1132 }
1133
1134 pr_debug("%s: using settings for %s\n", __func__, match->compatible);
1135 data = match->data;
1136
1137 if (!data->init_usb_uart) {
1138 pr_err("%s: usb-uart not available on %s\n",
1139 __func__, match->compatible);
1140 return -ENOTSUPP;
1141 }
1142
1143 grf = ERR_PTR(-ENODEV);
1144 if (np->parent)
1145 grf = syscon_node_to_regmap(np->parent);
1146 if (IS_ERR(grf))
1147 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1148 if (IS_ERR(grf)) {
1149 pr_err("%s: Missing rockchip,grf property, %lu\n",
1150 __func__, PTR_ERR(grf));
1151 return PTR_ERR(grf);
1152 }
1153
1154 ret = data->init_usb_uart(grf, data);
1155 if (ret) {
1156 pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
1157 enable_usb_uart = 0;
1158 return ret;
1159 }
1160
1161 return 0;
1162 }
1163 early_initcall(rockchip_init_usb_uart);
1164
rockchip_usb_uart(char * buf)1165 static int __init rockchip_usb_uart(char *buf)
1166 {
1167 enable_usb_uart = true;
1168 return 0;
1169 }
1170 early_param("rockchip.usb_uart", rockchip_usb_uart);
1171 #endif
1172
1173 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
1174 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
1175 MODULE_LICENSE("GPL v2");
1176