1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip Audio PWM driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ROCKCHIP_AUDIO_PWM_H 10*4882a593Smuzhiyun #define _ROCKCHIP_AUDIO_PWM_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* AUDIO PWM REGS offset */ 13*4882a593Smuzhiyun #define AUDPWM_VERSION (0x0000) 14*4882a593Smuzhiyun #define AUDPWM_XFER (0x0004) 15*4882a593Smuzhiyun #define AUDPWM_SRC_CFG (0x0008) 16*4882a593Smuzhiyun #define AUDPWM_PWM_CFG (0x0010) 17*4882a593Smuzhiyun #define AUDPWM_PWM_ST (0x0014) 18*4882a593Smuzhiyun #define AUDPWM_PWM_BUF_01 (0x0018) 19*4882a593Smuzhiyun #define AUDPWM_PWM_BUF_23 (0x001c) 20*4882a593Smuzhiyun #define AUDPWM_FIFO_CFG (0x0020) 21*4882a593Smuzhiyun #define AUDPWM_FIFO_LVL (0x0024) 22*4882a593Smuzhiyun #define AUDPWM_FIFO_INT_EN (0x0028) 23*4882a593Smuzhiyun #define AUDPWM_FIFO_INT_ST (0x002c) 24*4882a593Smuzhiyun #define AUDPWM_FIFO_ENTRY (0x0080) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Transfer Control Register */ 29*4882a593Smuzhiyun #define AUDPWM_XFER_LSTOP HIWORD_UPDATE(1, 1, 1) 30*4882a593Smuzhiyun #define AUDPWM_XFER_START HIWORD_UPDATE(1, 0, 0) 31*4882a593Smuzhiyun #define AUDPWM_XFER_STOP HIWORD_UPDATE(0, 0, 0) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Source Data Configuration Register */ 34*4882a593Smuzhiyun #define AUDPWM_ALIGN_LEFT HIWORD_UPDATE(1, 5, 5) 35*4882a593Smuzhiyun #define AUDPWM_ALIGN_RIGHT HIWORD_UPDATE(0, 5, 5) 36*4882a593Smuzhiyun #define AUDPWM_SRC_WIDTH(x) HIWORD_UPDATE((x) - 1, 4, 0) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* PWM Configuration Register */ 39*4882a593Smuzhiyun #define AUDPWM_SAMPLE_WIDTH(x) HIWORD_UPDATE((x) - 8, 9, 8) 40*4882a593Smuzhiyun #define AUDPWM_LINEAR_INTERP_EN HIWORD_UPDATE(1, 4, 4) 41*4882a593Smuzhiyun #define AUDPWM_INTERP_RATE(x) HIWORD_UPDATE((x), 3, 0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* FIFO Configuration Register */ 44*4882a593Smuzhiyun #define AUDPWM_DMA_EN HIWORD_UPDATE(1, 7, 7) 45*4882a593Smuzhiyun #define AUDPWM_DMA_DIS HIWORD_UPDATE(0, 7, 7) 46*4882a593Smuzhiyun #define AUDPWM_DMA_WATERMARK(x) HIWORD_UPDATE((x) - 1, 4, 0) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* _ROCKCHIP_AUDIO_PWM_H */ 49