| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 110 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3328_PLL_CON(16),
793 priv->cpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[CPLL], in rk3328_clk_get_rate()
794 priv->cru, CPLL); in rk3328_clk_get_rate()
880 ret = rockchip_pll_set_rate(&rk3328_pll_clks[CPLL], in rk3328_clk_set_rate()
881 priv->cru, CPLL, rate); in rk3328_clk_set_rate()
1288 priv->cpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[CPLL], in rkclk_init()
1289 priv->cru, CPLL); in rkclk_init()
1304 rockchip_pll_set_rate(&rk3328_pll_clks[CPLL], in rkclk_init()
1305 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
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| H A D | clk_rk3128.c | 85 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(8),
455 rockchip_pll_set_rate(&rk3128_pll_clks[CPLL], in rk3128_vop_set_clk()
456 priv->cru, CPLL, src_clk_div * hz); in rk3128_vop_set_clk()
490 parent = rockchip_pll_get_rate(&rk3128_pll_clks[CPLL], in rk3128_vop_get_rate()
491 priv->cru, CPLL); in rk3128_vop_get_rate()
837 rockchip_pll_set_rate(&rk3128_pll_clks[CPLL], in rkclk_init()
838 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
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| H A D | clk_rk322x.c | 86 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(6),
649 ret = rockchip_pll_set_rate(&rk322x_pll_clks[CPLL], in rk322x_clk_set_rate()
650 priv->cru, CPLL, rate); in rk322x_clk_set_rate()
963 priv->cpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[CPLL], in rkclk_init()
964 priv->cru, CPLL); in rkclk_init()
996 rockchip_pll_set_rate(&rk322x_pll_clks[CPLL], in rkclk_init()
997 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
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| H A D | clk_rk1808.c | 84 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK1808_PLL_CON(16),
609 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_mac_set_clk()
610 priv->cru, CPLL); in rk1808_mac_set_clk()
1009 ret = rockchip_pll_set_rate(&rk1808_pll_clks[CPLL], in rk1808_clk_set_rate()
1010 priv->cru, CPLL, rate); in rk1808_clk_set_rate()
1308 priv->cpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_clk_probe()
1309 priv->cru, CPLL); in rk1808_clk_probe()
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| H A D | clk_rv1106.c | 43 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1106_PLL_CON(8),
1060 rate = rockchip_pll_get_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_get_rate()
1061 CPLL); in rv1106_clk_get_rate()
1158 ret = rockchip_pll_set_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_set_rate()
1159 CPLL, rate); in rv1106_clk_set_rate()
1278 ret = rockchip_pll_set_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_init()
1279 CPLL, CPLL_HZ); in rv1106_clk_init()
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| H A D | clk_rk3528.c | 69 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
1350 rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_get_rate()
1351 CPLL); in rk3528_clk_get_rate()
1469 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_set_rate()
1470 CPLL, rate); in rk3528_clk_set_rate()
1471 priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], in rk3528_clk_set_rate()
1472 priv->cru, CPLL); in rk3528_clk_set_rate()
1893 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_init()
1894 CPLL, CPLL_HZ); in rk3528_clk_init()
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| H A D | clk_rk3368.c | 321 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
755 parent = rkclk_pll_get_rate(cru, CPLL); in rk3368_vop_get_clk()
794 if ((rkclk_pll_get_rate(cru, CPLL) % hz) == 0) { in rk3368_vop_set_clk()
795 lcdc_div = rkclk_pll_get_rate(cru, CPLL) / hz; in rk3368_vop_set_clk()
1278 rkclk_set_pll(cru, CPLL, &cpll_init_cfg); in rkclk_init()
1284 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
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| H A D | clk_rk3588.c | 59 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),
1538 rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_get_rate()
1539 CPLL); in rk3588_clk_get_rate()
1673 ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_set_rate()
1674 CPLL, rate); in rk3588_clk_set_rate()
1675 priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], in rk3588_clk_set_rate()
1676 priv->cru, CPLL); in rk3588_clk_set_rate()
2033 ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_init()
2034 CPLL, CPLL_HZ); in rk3588_clk_init()
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| H A D | clk_rv1126.c | 64 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16),
1629 rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_get_rate()
1630 CPLL); in rv1126_clk_get_rate()
1751 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_set_rate()
1752 CPLL, rate); in rv1126_clk_set_rate()
2147 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_init()
2148 CPLL, CPLL_HZ); in rv1126_clk_init()
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| H A D | clk_rk3568.c | 72 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
2520 rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_get_rate()
2521 CPLL); in rk3568_clk_get_rate()
2703 ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_set_rate()
2704 CPLL, rate); in rk3568_clk_set_rate()
2705 priv->cpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], in rk3568_clk_set_rate()
2706 priv->cru, CPLL); in rk3568_clk_set_rate()
3249 ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_init()
3250 CPLL, CPLL_HZ); in rk3568_clk_init()
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| H A D | clk_px30.c | 823 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); in px30_vop_get_clk()
862 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); in px30_vop_set_clk()
1174 pll_rate = px30_clk_get_pll_rate(priv, CPLL); in px30_mac_set_clk()
1309 rate = px30_clk_get_pll_rate(priv, CPLL); in px30_clk_get_rate()
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| H A D | clk_rk3562.c | 53 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3562_PMU1_PLL_CON(0),
1380 rate = rockchip_pll_get_rate(&rk3562_pll_clks[CPLL], priv->cru, in rk3562_clk_get_rate()
1381 CPLL); in rk3562_clk_get_rate()
1820 ret = rockchip_pll_set_rate(&rk3562_pll_clks[CPLL], priv->cru, in rk3562_clk_init()
1821 CPLL, CPLL_HZ); in rk3562_clk_init()
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | exynos5422-odroid-core.dtsi | 67 /* derived from 666MHz CPLL */
85 /* derived from 666MHz CPLL */
112 /* derived from 666MHz CPLL */
151 /* derived from 666MHz CPLL */
160 /* derived from 666MHz CPLL */
217 /* derived from 666MHz CPLL */
277 /* derived from 666MHz CPLL */
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 19 #define CPLL 8 macro
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| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | xlnx-versal-clk.h | 35 #define CPLL 26 macro
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3368.h | 17 CPLL, enumerator
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| H A D | cru_rk3128.h | 65 CPLL, enumerator
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| H A D | cru_rk322x.h | 62 CPLL, enumerator
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| H A D | cru_rk3328.h | 60 CPLL, enumerator
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| H A D | cru_rv1106.h | 28 CPLL, enumerator
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| H A D | cru_rk1808.h | 22 CPLL, enumerator
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| H A D | cru_rk3528.h | 23 CPLL, enumerator
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| H A D | cru_rv1126.h | 50 CPLL, enumerator
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| H A D | cru_px30.h | 29 CPLL, enumerator
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| H A D | cru_rk3562.h | 28 CPLL, enumerator
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