Searched +full:core +full:- +full:pwr +full:- +full:off +full:- +full:time (Results 1 – 25 of 119) sorted by relevance
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1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Thierry Reding <thierry.reding@gmail.com>11 - Jonathan Hunter <jonathanh@nvidia.com>16 - nvidia,tegra20-pmc17 - nvidia,tegra20-pmc18 - nvidia,tegra30-pmc19 - nvidia,tegra114-pmc[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/mfd/max77620.h>17 stdout-path = "serial0:115200n8";26 vdd-supply = <&vdd_gpu>;36 clock-frequency = <400000>;41 interrupt-parent = <&tegra_pmc>;44 #interrupt-cells = <2>;45 interrupt-controller;47 #gpio-cells = <2>;48 gpio-controller;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/gpio-keys.h>5 #include <dt-bindings/input/linux-event-codes.h>6 #include <dt-bindings/mfd/max77620.h>12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";22 stdout-path = "serial0:115200n8";33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;34 hvddio-pex-supply = <&vdd_1v8>;35 dvddio-pex-supply = <&vdd_pex_1v05>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>6 #include "tegra20-cpu-opp.dtsi"19 stdout-path = "serial0:115200n8";30 vdd-supply = <&hdmi_vdd_reg>;31 pll-supply = <&hdmi_pll_reg>;33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;34 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)40 pinctrl-names = "default";[all …]
1 // SPDX-License-Identifier: GPL-2.015 stdout-path = "serial0:115200n8";24 vdd-supply = <&hdmi_vdd_reg>;25 pll-supply = <&hdmi_pll_reg>;27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)34 pinctrl-names = "default";35 pinctrl-0 = <&state_default>;295 clock-frequency = <400000>;300 clock-frequency = <100000>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>6 #include "tegra20-cpu-opp.dtsi"7 #include "tegra20-cpu-opp-microvolt.dtsi"21 stdout-path = "serial0:115200n8";40 vdd-supply = <&hdmi_vdd_reg>;41 pll-supply = <&hdmi_pll_reg>;43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;44 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/input/input.h>13 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use14 * tegra30-cardhu-a04.dts.17 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th19 * The (downstream internal) U-Boot of Cardhu display the board-id as40 stdout-path = "serial0:115200n8";51 avdd-pexb-supply = <&ldo1_reg>;52 vdd-pexb-supply = <&ldo1_reg>;53 avdd-pex-pll-supply = <&ldo1_reg>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>6 #include "tegra20-cpu-opp.dtsi"19 stdout-path = "serial0:115200n8";38 vdd-supply = <&hdmi_vdd_reg>;39 pll-supply = <&hdmi_pll_reg>;41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)48 pinctrl-names = "default";[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR MIT16 avdd-pexa-supply = <&vdd2_reg>;17 avdd-pexb-supply = <&vdd2_reg>;18 avdd-pex-pll-supply = <&vdd2_reg>;19 avdd-plle-supply = <&ldo6_reg>;20 hvdd-pex-supply = <®_module_3v3>;21 vddio-pex-ctl-supply = <®_module_3v3>;22 vdd-pexa-supply = <&vdd2_reg>;23 vdd-pexb-supply = <&vdd2_reg>;27 nvidia,num-lanes = <4>;[all …]
1 // SPDX-License-Identifier: GPL-2.015 nvidia,ddc-i2c-bus = <&hdmi_ddc>;16 nvidia,hpd-gpio =18 pll-supply = <®_1v8_avdd_hdmi_pll>;19 vdd-supply = <®_3v3_avdd_hdmi>;24 pinctrl-names = "default";25 pinctrl-0 = <&state_default>;28 /* Analogue Audio (On-module) */29 clk1-out-pw4 {34 nvidia,enable-input = <TEGRA_PIN_DISABLE>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/input/input.h>13 stdout-path = "serial0:115200n8";19 * missing a unit-address. However, the bootloader on these Chromebook21 * Adding the unit-address causes the bootloader to create a /memory33 /delete-node/ memory@80000000;39 vdd-supply = <&vdd_3v3_hdmi>;40 pll-supply = <&vdd_hdmi_pll>;41 hdmi-supply = <&vdd_5v0_hdmi>;43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;[all …]
1 // SPDX-License-Identifier: GPL-2.022 nvidia,ddc-i2c-bus = <&hdmi_ddc>;23 nvidia,hpd-gpio =25 pll-supply = <®_1v8_avdd_hdmi_pll>;26 vdd-supply = <®_3v3_avdd_hdmi>;31 pinctrl-names = "default";32 pinctrl-0 = <&state_default>;35 /* Analogue Audio AC97 to WM9712 (On-module) */36 audio-refclk {51 * (All on-module), SODIMM Pin 45 Wakeup[all …]
1 // SPDX-License-Identifier: GPL-2.015 avdd-pexa-supply = <&vdd2_reg>;16 avdd-pexb-supply = <&vdd2_reg>;17 avdd-pex-pll-supply = <&vdd2_reg>;18 avdd-plle-supply = <&ldo6_reg>;19 hvdd-pex-supply = <®_module_3v3>;20 vddio-pex-ctl-supply = <®_module_3v3>;21 vdd-pexa-supply = <&vdd2_reg>;22 vdd-pexb-supply = <&vdd2_reg>;26 nvidia,num-lanes = <4>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>18 stdout-path = "serial0:115200n8";37 hdmi-supply = <&vdd_5v0_hdmi>;38 vdd-supply = <&hdmi_vdd_reg>;39 pll-supply = <&hdmi_pll_reg>;41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)48 pinctrl-names = "default";[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>18 stdout-path = "serial0:115200n8";37 vdd-supply = <&hdmi_vdd_reg>;38 pll-supply = <&hdmi_pll_reg>;39 hdmi-supply = <&vdd_hdmi>;41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)48 pinctrl-names = "default";[all …]
1 // SPDX-License-Identifier: GPL-2.0-only10 * devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core12 * enough on some SoCs like Intel Tangier. In such case PCI core sets a new14 * pci_platform_pm_ops (see drivers/pci/pci-mid.c).27 #include <asm/intel-mid.h>106 static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg) in mid_pwr_get_state() argument108 return readl(pwr->regs + PM_SSS(reg)); in mid_pwr_get_state()111 static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value) in mid_pwr_set_state() argument113 writel(value, pwr->regs + PM_SSC(reg)); in mid_pwr_set_state()116 static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value) in mid_pwr_set_wake() argument[all …]
1 /dts-v1/;3 #include <dt-bindings/input/input.h>11 stdout-path = &uarta;39 display-timings {42 clock-frequency = <54030000>;45 hback-porch = <160>;46 hfront-porch = <24>;47 hsync-len = <136>;48 vback-porch = <3>;49 vfront-porch = <61>;[all …]
1 #include <dt-bindings/input/input.h>19 vdd-supply = <&vdd_3v3_hdmi>;20 pll-supply = <&vdd_hdmi_pll>;21 hdmi-supply = <&vdd_5v0_hdmi>;23 nvidia,ddc-i2c-bus = <&hdmi_ddc>;24 nvidia,hpd-gpio =36 vdd-supply = <&vdd_3v3_panel>;52 clock-frequency = <100000>;54 acodec: audio-codec@10 {57 interrupt-parent = <&gpio>;[all …]
1 /dts-v1/;3 #include <dt-bindings/input/input.h>11 stdout-path = &uartd;38 display-timings {41 clock-frequency = <70600000>;44 hback-porch = <58>;45 hfront-porch = <58>;46 hsync-len = <58>;47 vback-porch = <4>;48 vfront-porch = <4>;[all …]
1 /dts-v1/;3 #include <dt-bindings/input/input.h>11 stdout-path = &uartd;38 display-timings {41 clock-frequency = <42430000>;44 hback-porch = <138>;45 hfront-porch = <34>;46 hsync-len = <136>;47 vback-porch = <21>;48 vfront-porch = <4>;[all …]
... is 0x%04x(%d) Off Loose interpretation of 11h spec - may join non ...
1 // SPDX-License-Identifier: GPL-2.0-only8 * Date: 2016-8-2421 #include "sdhci-pltfm.h"22 #include "sdhci-xenon.h"41 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()42 return -ETIMEDOUT; in xenon_enable_internal_clk()50 /* Set SDCLK-off-while-idle */91 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()96 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()137 /* Disable the Re-Tuning Request functionality */ in xenon_retune_setup()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.12 #define pr_fmt(fmt) "tegra-pmc: " fmt14 #include <linux/arm-smccc.h>16 #include <linux/clk-provider.h>18 #include <linux/clk/clk-conf.h>36 #include <linux/pinctrl/pinconf-generic.h>51 #include <dt-bindings/interrupt-controller/arm-gic.h>52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>53 #include <dt-bindings/gpio/tegra186-gpio.h>[all …]
10 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/12 * SPDX-License-Identifier: GPL-2.0+57 return -ENODEV; in read_eeprom()64 return -EIO; in read_eeprom()70 return -EIO; in read_eeprom()80 gpio_request(LED_PWR_BL_GPIO, "LED PWR BL"); in shc_request_gpio()81 gpio_request(LED_PWR_RD_GPIO, "LED PWR RD"); in shc_request_gpio()89 gpio_request(LED_PWR_GN_GPIO, "LED PWR GN"); in shc_request_gpio()111 /* Wi-Fi power regulator enable - high = enabled */ in force_modules_running()114 * Wait for Wi-Fi power regulator to reach a stable voltage in force_modules_running()[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 /dts-v1/;10 model = "Firefly ROC-RK3308-CC board";11 compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";13 stdout-path = "serial2:1500000n8";16 ir-receiver {17 compatible = "gpio-ir-receiver";19 pinctrl-names = "default";20 pinctrl-0 = <&ir_recv_pin>;24 compatible = "pwm-ir-tx";[all …]