1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 5*4882a593Smuzhiyun#include "tegra20.dtsi" 6*4882a593Smuzhiyun#include "tegra20-cpu-opp.dtsi" 7*4882a593Smuzhiyun#include "tegra20-cpu-opp-microvolt.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Toshiba AC100 / Dynabook AZ"; 11*4882a593Smuzhiyun compatible = "compal,paz00", "nvidia,tegra20"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun rtc0 = "/i2c@7000d000/tps6586x@34"; 15*4882a593Smuzhiyun rtc1 = "/rtc@7000e000"; 16*4882a593Smuzhiyun serial0 = &uarta; 17*4882a593Smuzhiyun serial1 = &uartc; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun chosen { 21*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun memory@0 { 25*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun host1x@50000000 { 29*4882a593Smuzhiyun dc@54200000 { 30*4882a593Smuzhiyun rgb { 31*4882a593Smuzhiyun status = "okay"; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun nvidia,panel = <&panel>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun hdmi@54280000 { 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun vdd-supply = <&hdmi_vdd_reg>; 41*4882a593Smuzhiyun pll-supply = <&hdmi_pll_reg>; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun nvidia,ddc-i2c-bus = <&hdmi_ddc>; 44*4882a593Smuzhiyun nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 45*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun pinmux@70000014 { 50*4882a593Smuzhiyun pinctrl-names = "default"; 51*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun state_default: pinmux { 54*4882a593Smuzhiyun ata { 55*4882a593Smuzhiyun nvidia,pins = "ata", "atc", "atd", "ate", 56*4882a593Smuzhiyun "dap2", "gmb", "gmc", "gmd", "spia", 57*4882a593Smuzhiyun "spib", "spic", "spid", "spie"; 58*4882a593Smuzhiyun nvidia,function = "gmi"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun atb { 61*4882a593Smuzhiyun nvidia,pins = "atb", "gma", "gme"; 62*4882a593Smuzhiyun nvidia,function = "sdio4"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun cdev1 { 65*4882a593Smuzhiyun nvidia,pins = "cdev1"; 66*4882a593Smuzhiyun nvidia,function = "plla_out"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun cdev2 { 69*4882a593Smuzhiyun nvidia,pins = "cdev2"; 70*4882a593Smuzhiyun nvidia,function = "pllp_out4"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun crtp { 73*4882a593Smuzhiyun nvidia,pins = "crtp"; 74*4882a593Smuzhiyun nvidia,function = "crt"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun csus { 77*4882a593Smuzhiyun nvidia,pins = "csus"; 78*4882a593Smuzhiyun nvidia,function = "pllc_out1"; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun dap1 { 81*4882a593Smuzhiyun nvidia,pins = "dap1"; 82*4882a593Smuzhiyun nvidia,function = "dap1"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun dap3 { 85*4882a593Smuzhiyun nvidia,pins = "dap3"; 86*4882a593Smuzhiyun nvidia,function = "dap3"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun dap4 { 89*4882a593Smuzhiyun nvidia,pins = "dap4"; 90*4882a593Smuzhiyun nvidia,function = "dap4"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun ddc { 93*4882a593Smuzhiyun nvidia,pins = "ddc"; 94*4882a593Smuzhiyun nvidia,function = "i2c2"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun dta { 97*4882a593Smuzhiyun nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 98*4882a593Smuzhiyun nvidia,function = "rsvd1"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun dtf { 101*4882a593Smuzhiyun nvidia,pins = "dtf"; 102*4882a593Smuzhiyun nvidia,function = "i2c3"; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun gpu { 105*4882a593Smuzhiyun nvidia,pins = "gpu", "sdb", "sdd"; 106*4882a593Smuzhiyun nvidia,function = "pwm"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun gpu7 { 109*4882a593Smuzhiyun nvidia,pins = "gpu7"; 110*4882a593Smuzhiyun nvidia,function = "rtck"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun gpv { 113*4882a593Smuzhiyun nvidia,pins = "gpv", "slxa", "slxk"; 114*4882a593Smuzhiyun nvidia,function = "pcie"; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun hdint { 117*4882a593Smuzhiyun nvidia,pins = "hdint", "pta"; 118*4882a593Smuzhiyun nvidia,function = "hdmi"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun i2cp { 121*4882a593Smuzhiyun nvidia,pins = "i2cp"; 122*4882a593Smuzhiyun nvidia,function = "i2cp"; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun irrx { 125*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx"; 126*4882a593Smuzhiyun nvidia,function = "uarta"; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun kbca { 129*4882a593Smuzhiyun nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; 130*4882a593Smuzhiyun nvidia,function = "kbc"; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun kbcb { 133*4882a593Smuzhiyun nvidia,pins = "kbcb", "kbcd"; 134*4882a593Smuzhiyun nvidia,function = "sdio2"; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun lcsn { 137*4882a593Smuzhiyun nvidia,pins = "lcsn", "ld0", "ld1", "ld2", 138*4882a593Smuzhiyun "ld3", "ld4", "ld5", "ld6", "ld7", 139*4882a593Smuzhiyun "ld8", "ld9", "ld10", "ld11", "ld12", 140*4882a593Smuzhiyun "ld13", "ld14", "ld15", "ld16", "ld17", 141*4882a593Smuzhiyun "ldc", "ldi", "lhp0", "lhp1", "lhp2", 142*4882a593Smuzhiyun "lhs", "lm0", "lm1", "lpp", "lpw0", 143*4882a593Smuzhiyun "lpw1", "lpw2", "lsc0", "lsc1", "lsck", 144*4882a593Smuzhiyun "lsda", "lsdi", "lspi", "lvp0", "lvp1", 145*4882a593Smuzhiyun "lvs"; 146*4882a593Smuzhiyun nvidia,function = "displaya"; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun owc { 149*4882a593Smuzhiyun nvidia,pins = "owc"; 150*4882a593Smuzhiyun nvidia,function = "owr"; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun pmc { 153*4882a593Smuzhiyun nvidia,pins = "pmc"; 154*4882a593Smuzhiyun nvidia,function = "pwr_on"; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun rm { 157*4882a593Smuzhiyun nvidia,pins = "rm"; 158*4882a593Smuzhiyun nvidia,function = "i2c1"; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun sdc { 161*4882a593Smuzhiyun nvidia,pins = "sdc"; 162*4882a593Smuzhiyun nvidia,function = "twc"; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun sdio1 { 165*4882a593Smuzhiyun nvidia,pins = "sdio1"; 166*4882a593Smuzhiyun nvidia,function = "sdio1"; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun slxc { 169*4882a593Smuzhiyun nvidia,pins = "slxc", "slxd"; 170*4882a593Smuzhiyun nvidia,function = "spi4"; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun spdi { 173*4882a593Smuzhiyun nvidia,pins = "spdi", "spdo"; 174*4882a593Smuzhiyun nvidia,function = "rsvd2"; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun spif { 177*4882a593Smuzhiyun nvidia,pins = "spif", "uac"; 178*4882a593Smuzhiyun nvidia,function = "rsvd4"; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun spig { 181*4882a593Smuzhiyun nvidia,pins = "spig", "spih"; 182*4882a593Smuzhiyun nvidia,function = "spi2_alt"; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun uaa { 185*4882a593Smuzhiyun nvidia,pins = "uaa", "uab", "uda"; 186*4882a593Smuzhiyun nvidia,function = "ulpi"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun uad { 189*4882a593Smuzhiyun nvidia,pins = "uad"; 190*4882a593Smuzhiyun nvidia,function = "spdif"; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun uca { 193*4882a593Smuzhiyun nvidia,pins = "uca", "ucb"; 194*4882a593Smuzhiyun nvidia,function = "uartc"; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun conf_ata { 197*4882a593Smuzhiyun nvidia,pins = "ata", "atb", "atc", "atd", "ate", 198*4882a593Smuzhiyun "cdev1", "cdev2", "dap1", "dap2", "dtf", 199*4882a593Smuzhiyun "gma", "gmb", "gmc", "gmd", "gme", 200*4882a593Smuzhiyun "gpu", "gpu7", "gpv", "i2cp", "pta", 201*4882a593Smuzhiyun "rm", "sdio1", "slxk", "spdo", "uac", 202*4882a593Smuzhiyun "uda"; 203*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 204*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun conf_ck32 { 207*4882a593Smuzhiyun nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 208*4882a593Smuzhiyun "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 209*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun conf_crtp { 212*4882a593Smuzhiyun nvidia,pins = "crtp", "dap3", "dap4", "dtb", 213*4882a593Smuzhiyun "dtc", "dte", "slxa", "slxc", "slxd", 214*4882a593Smuzhiyun "spdi"; 215*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun conf_csus { 219*4882a593Smuzhiyun nvidia,pins = "csus", "spia", "spib", "spid", 220*4882a593Smuzhiyun "spif"; 221*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 222*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun conf_ddc { 225*4882a593Smuzhiyun nvidia,pins = "ddc", "irrx", "irtx", "kbca", 226*4882a593Smuzhiyun "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 227*4882a593Smuzhiyun "spic", "spig", "uaa", "uab"; 228*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 229*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun conf_dta { 232*4882a593Smuzhiyun nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", 233*4882a593Smuzhiyun "spie", "spih", "uad", "uca", "ucb"; 234*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 235*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun conf_hdint { 238*4882a593Smuzhiyun nvidia,pins = "hdint", "ld0", "ld1", "ld2", 239*4882a593Smuzhiyun "ld3", "ld4", "ld5", "ld6", "ld7", 240*4882a593Smuzhiyun "ld8", "ld9", "ld10", "ld11", "ld12", 241*4882a593Smuzhiyun "ld13", "ld14", "ld15", "ld16", "ld17", 242*4882a593Smuzhiyun "ldc", "ldi", "lhs", "lsc0", "lspi", 243*4882a593Smuzhiyun "lvs", "pmc"; 244*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun conf_lc { 247*4882a593Smuzhiyun nvidia,pins = "lc", "ls"; 248*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun conf_lcsn { 251*4882a593Smuzhiyun nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", 252*4882a593Smuzhiyun "lm0", "lm1", "lpp", "lpw0", "lpw1", 253*4882a593Smuzhiyun "lpw2", "lsc1", "lsck", "lsda", "lsdi", 254*4882a593Smuzhiyun "lvp0", "lvp1", "sdb"; 255*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun conf_ld17_0 { 258*4882a593Smuzhiyun nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 259*4882a593Smuzhiyun "ld23_22"; 260*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun i2s@70002800 { 266*4882a593Smuzhiyun status = "okay"; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun serial@70006000 { 270*4882a593Smuzhiyun status = "okay"; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun serial@70006200 { 274*4882a593Smuzhiyun status = "okay"; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun pwm: pwm@7000a000 { 278*4882a593Smuzhiyun status = "okay"; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun lvds_ddc: i2c@7000c000 { 282*4882a593Smuzhiyun status = "okay"; 283*4882a593Smuzhiyun clock-frequency = <400000>; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun alc5632: alc5632@1e { 286*4882a593Smuzhiyun compatible = "realtek,alc5632"; 287*4882a593Smuzhiyun reg = <0x1e>; 288*4882a593Smuzhiyun gpio-controller; 289*4882a593Smuzhiyun #gpio-cells = <2>; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun hdmi_ddc: i2c@7000c400 { 294*4882a593Smuzhiyun status = "okay"; 295*4882a593Smuzhiyun clock-frequency = <100000>; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun nvec@7000c500 { 299*4882a593Smuzhiyun compatible = "nvidia,nvec"; 300*4882a593Smuzhiyun reg = <0x7000c500 0x100>; 301*4882a593Smuzhiyun interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 302*4882a593Smuzhiyun #address-cells = <1>; 303*4882a593Smuzhiyun #size-cells = <0>; 304*4882a593Smuzhiyun clock-frequency = <80000>; 305*4882a593Smuzhiyun request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 306*4882a593Smuzhiyun slave-addr = <138>; 307*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_I2C3>, 308*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 309*4882a593Smuzhiyun clock-names = "div-clk", "fast-clk"; 310*4882a593Smuzhiyun resets = <&tegra_car 67>; 311*4882a593Smuzhiyun reset-names = "i2c"; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun memory-controller@7000f400 { 315*4882a593Smuzhiyun nvidia,use-ram-code; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun emc-tables@0 { 318*4882a593Smuzhiyun nvidia,ram-code = <0x0>; 319*4882a593Smuzhiyun #address-cells = <1>; 320*4882a593Smuzhiyun #size-cells = <0>; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun emc-table@166500 { 323*4882a593Smuzhiyun reg = <166500>; 324*4882a593Smuzhiyun compatible = "nvidia,tegra20-emc-table"; 325*4882a593Smuzhiyun clock-frequency = <166500>; 326*4882a593Smuzhiyun nvidia,emc-registers = <0x0000000a 0x00000016 327*4882a593Smuzhiyun 0x00000008 0x00000003 0x00000004 0x00000004 328*4882a593Smuzhiyun 0x00000002 0x0000000c 0x00000003 0x00000003 329*4882a593Smuzhiyun 0x00000002 0x00000001 0x00000004 0x00000005 330*4882a593Smuzhiyun 0x00000004 0x00000009 0x0000000d 0x000004df 331*4882a593Smuzhiyun 0x00000000 0x00000003 0x00000003 0x00000003 332*4882a593Smuzhiyun 0x00000003 0x00000001 0x0000000a 0x000000c8 333*4882a593Smuzhiyun 0x00000003 0x00000006 0x00000004 0x00000008 334*4882a593Smuzhiyun 0x00000002 0x00000000 0x00000000 0x00000002 335*4882a593Smuzhiyun 0x00000000 0x00000000 0x00000083 0xe03b0323 336*4882a593Smuzhiyun 0x007fe010 0x00001414 0x00000000 0x00000000 337*4882a593Smuzhiyun 0x00000000 0x00000000 0x00000000 0x00000000>; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun emc-table@333000 { 341*4882a593Smuzhiyun reg = <333000>; 342*4882a593Smuzhiyun compatible = "nvidia,tegra20-emc-table"; 343*4882a593Smuzhiyun clock-frequency = <333000>; 344*4882a593Smuzhiyun nvidia,emc-registers = <0x00000018 0x00000033 345*4882a593Smuzhiyun 0x00000012 0x00000004 0x00000004 0x00000005 346*4882a593Smuzhiyun 0x00000003 0x0000000c 0x00000006 0x00000006 347*4882a593Smuzhiyun 0x00000003 0x00000001 0x00000004 0x00000005 348*4882a593Smuzhiyun 0x00000004 0x00000009 0x0000000d 0x00000bff 349*4882a593Smuzhiyun 0x00000000 0x00000003 0x00000003 0x00000006 350*4882a593Smuzhiyun 0x00000006 0x00000001 0x00000011 0x000000c8 351*4882a593Smuzhiyun 0x00000003 0x0000000e 0x00000007 0x00000008 352*4882a593Smuzhiyun 0x00000002 0x00000000 0x00000000 0x00000002 353*4882a593Smuzhiyun 0x00000000 0x00000000 0x00000083 0xf0440303 354*4882a593Smuzhiyun 0x007fe010 0x00001414 0x00000000 0x00000000 355*4882a593Smuzhiyun 0x00000000 0x00000000 0x00000000 0x00000000>; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun i2c@7000d000 { 361*4882a593Smuzhiyun status = "okay"; 362*4882a593Smuzhiyun clock-frequency = <400000>; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun pmic: tps6586x@34 { 365*4882a593Smuzhiyun compatible = "ti,tps6586x"; 366*4882a593Smuzhiyun reg = <0x34>; 367*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun #gpio-cells = <2>; 370*4882a593Smuzhiyun gpio-controller; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun sys-supply = <&p5valw_reg>; 373*4882a593Smuzhiyun vin-sm0-supply = <&sys_reg>; 374*4882a593Smuzhiyun vin-sm1-supply = <&sys_reg>; 375*4882a593Smuzhiyun vin-sm2-supply = <&sys_reg>; 376*4882a593Smuzhiyun vinldo01-supply = <&sm2_reg>; 377*4882a593Smuzhiyun vinldo23-supply = <&sm2_reg>; 378*4882a593Smuzhiyun vinldo4-supply = <&sm2_reg>; 379*4882a593Smuzhiyun vinldo678-supply = <&sm2_reg>; 380*4882a593Smuzhiyun vinldo9-supply = <&sm2_reg>; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun regulators { 383*4882a593Smuzhiyun sys_reg: sys { 384*4882a593Smuzhiyun regulator-name = "vdd_sys"; 385*4882a593Smuzhiyun regulator-always-on; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun core_vdd_reg: sm0 { 389*4882a593Smuzhiyun regulator-name = "+1.2vs_sm0,vdd_core"; 390*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 391*4882a593Smuzhiyun regulator-max-microvolt = <1225000>; 392*4882a593Smuzhiyun regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; 393*4882a593Smuzhiyun regulator-coupled-max-spread = <170000 450000>; 394*4882a593Smuzhiyun regulator-always-on; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun nvidia,tegra-core-regulator; 397*4882a593Smuzhiyun }; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun cpu_vdd_reg: sm1 { 400*4882a593Smuzhiyun regulator-name = "+1.0vs_sm1,vdd_cpu"; 401*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 402*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 403*4882a593Smuzhiyun regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; 404*4882a593Smuzhiyun regulator-coupled-max-spread = <450000 450000>; 405*4882a593Smuzhiyun regulator-always-on; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun nvidia,tegra-cpu-regulator; 408*4882a593Smuzhiyun }; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun sm2_reg: sm2 { 411*4882a593Smuzhiyun regulator-name = "+3.7vs_sm2,vin_ldo*"; 412*4882a593Smuzhiyun regulator-min-microvolt = <3700000>; 413*4882a593Smuzhiyun regulator-max-microvolt = <3700000>; 414*4882a593Smuzhiyun regulator-always-on; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun /* LDO0 is not connected to anything */ 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun ldo1 { 420*4882a593Smuzhiyun regulator-name = "+1.1vs_ldo1,avdd_pll*"; 421*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 422*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 423*4882a593Smuzhiyun regulator-always-on; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun rtc_vdd_reg: ldo2 { 427*4882a593Smuzhiyun regulator-name = "+1.2vs_ldo2,vdd_rtc"; 428*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 429*4882a593Smuzhiyun regulator-max-microvolt = <1225000>; 430*4882a593Smuzhiyun regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; 431*4882a593Smuzhiyun regulator-coupled-max-spread = <170000 450000>; 432*4882a593Smuzhiyun regulator-always-on; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun nvidia,tegra-rtc-regulator; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun ldo3 { 438*4882a593Smuzhiyun regulator-name = "+3.3vs_ldo3,avdd_usb*"; 439*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 440*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 441*4882a593Smuzhiyun regulator-always-on; 442*4882a593Smuzhiyun }; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun ldo4 { 445*4882a593Smuzhiyun regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; 446*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 447*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 448*4882a593Smuzhiyun regulator-always-on; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun ldo5 { 452*4882a593Smuzhiyun regulator-name = "+2.85vs_ldo5,vcore_mmc"; 453*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 454*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 455*4882a593Smuzhiyun regulator-always-on; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun ldo6 { 459*4882a593Smuzhiyun /* 460*4882a593Smuzhiyun * Research indicates this should be 461*4882a593Smuzhiyun * 1.8v; other boards that use this 462*4882a593Smuzhiyun * rail for the same purpose need it 463*4882a593Smuzhiyun * set to 1.8v. The schematic signal 464*4882a593Smuzhiyun * name is incorrect; perhaps copied 465*4882a593Smuzhiyun * from an incorrect NVIDIA reference. 466*4882a593Smuzhiyun */ 467*4882a593Smuzhiyun regulator-name = "+2.85vs_ldo6,avdd_vdac"; 468*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 469*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun hdmi_vdd_reg: ldo7 { 473*4882a593Smuzhiyun regulator-name = "+3.3vs_ldo7,avdd_hdmi"; 474*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 475*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 476*4882a593Smuzhiyun }; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun hdmi_pll_reg: ldo8 { 479*4882a593Smuzhiyun regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; 480*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 481*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun ldo9 { 485*4882a593Smuzhiyun regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; 486*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 487*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 488*4882a593Smuzhiyun regulator-always-on; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun ldo_rtc { 492*4882a593Smuzhiyun regulator-name = "+3.3vs_rtc"; 493*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 494*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 495*4882a593Smuzhiyun regulator-always-on; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun }; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun adt7461@4c { 501*4882a593Smuzhiyun compatible = "adi,adt7461"; 502*4882a593Smuzhiyun reg = <0x4c>; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun pmc@7000e400 { 507*4882a593Smuzhiyun nvidia,invert-interrupt; 508*4882a593Smuzhiyun nvidia,suspend-mode = <1>; 509*4882a593Smuzhiyun nvidia,cpu-pwr-good-time = <2000>; 510*4882a593Smuzhiyun nvidia,cpu-pwr-off-time = <0>; 511*4882a593Smuzhiyun nvidia,core-pwr-good-time = <3845 3845>; 512*4882a593Smuzhiyun nvidia,core-pwr-off-time = <0>; 513*4882a593Smuzhiyun nvidia,sys-clock-req-active-high; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun usb@c5000000 { 517*4882a593Smuzhiyun compatible = "nvidia,tegra20-udc"; 518*4882a593Smuzhiyun status = "okay"; 519*4882a593Smuzhiyun dr_mode = "peripheral"; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun usb-phy@c5000000 { 523*4882a593Smuzhiyun status = "okay"; 524*4882a593Smuzhiyun }; 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun usb@c5004000 { 527*4882a593Smuzhiyun status = "okay"; 528*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 529*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun usb-phy@c5004000 { 533*4882a593Smuzhiyun status = "okay"; 534*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 535*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 536*4882a593Smuzhiyun }; 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun usb@c5008000 { 539*4882a593Smuzhiyun status = "okay"; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun usb-phy@c5008000 { 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun }; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun mmc@c8000000 { 547*4882a593Smuzhiyun status = "okay"; 548*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; 549*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 550*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 551*4882a593Smuzhiyun bus-width = <4>; 552*4882a593Smuzhiyun }; 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun mmc@c8000600 { 555*4882a593Smuzhiyun status = "okay"; 556*4882a593Smuzhiyun bus-width = <8>; 557*4882a593Smuzhiyun non-removable; 558*4882a593Smuzhiyun }; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun backlight: backlight { 561*4882a593Smuzhiyun compatible = "pwm-backlight"; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 564*4882a593Smuzhiyun pwms = <&pwm 0 5000000>; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; 567*4882a593Smuzhiyun default-brightness-level = <10>; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun backlight-boot-off; 570*4882a593Smuzhiyun }; 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun clk32k_in: clock@0 { 573*4882a593Smuzhiyun compatible = "fixed-clock"; 574*4882a593Smuzhiyun clock-frequency = <32768>; 575*4882a593Smuzhiyun #clock-cells = <0>; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun gpio-keys { 579*4882a593Smuzhiyun compatible = "gpio-keys"; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun wakeup { 582*4882a593Smuzhiyun label = "Wakeup"; 583*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; 584*4882a593Smuzhiyun linux,code = <KEY_WAKEUP>; 585*4882a593Smuzhiyun wakeup-source; 586*4882a593Smuzhiyun }; 587*4882a593Smuzhiyun }; 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun gpio-leds { 590*4882a593Smuzhiyun compatible = "gpio-leds"; 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun led-0 { 593*4882a593Smuzhiyun label = "wifi-led"; 594*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; 595*4882a593Smuzhiyun linux,default-trigger = "rfkill0"; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun }; 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun panel: panel { 600*4882a593Smuzhiyun compatible = "samsung,ltn101nt05"; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun ddc-i2c-bus = <&lvds_ddc>; 603*4882a593Smuzhiyun power-supply = <&vdd_pnl_reg>; 604*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun backlight = <&backlight>; 607*4882a593Smuzhiyun }; 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun p5valw_reg: regulator@0 { 610*4882a593Smuzhiyun compatible = "regulator-fixed"; 611*4882a593Smuzhiyun regulator-name = "+5valw"; 612*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 613*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 614*4882a593Smuzhiyun regulator-always-on; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun vdd_pnl_reg: regulator@1 { 618*4882a593Smuzhiyun compatible = "regulator-fixed"; 619*4882a593Smuzhiyun regulator-name = "+3VS,vdd_pnl"; 620*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 621*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 622*4882a593Smuzhiyun regulator-boot-on; 623*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; 624*4882a593Smuzhiyun enable-active-high; 625*4882a593Smuzhiyun }; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun sound { 628*4882a593Smuzhiyun compatible = "nvidia,tegra-audio-alc5632-paz00", 629*4882a593Smuzhiyun "nvidia,tegra-audio-alc5632"; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun nvidia,model = "Compal PAZ00"; 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun nvidia,audio-routing = 634*4882a593Smuzhiyun "Int Spk", "SPKOUT", 635*4882a593Smuzhiyun "Int Spk", "SPKOUTN", 636*4882a593Smuzhiyun "Headset Mic", "MICBIAS1", 637*4882a593Smuzhiyun "MIC1", "Headset Mic", 638*4882a593Smuzhiyun "Headset Stereophone", "HPR", 639*4882a593Smuzhiyun "Headset Stereophone", "HPL", 640*4882a593Smuzhiyun "DMICDAT", "Digital Mic"; 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun nvidia,audio-codec = <&alc5632>; 643*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s1>; 644*4882a593Smuzhiyun nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 645*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 648*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 649*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_CDEV1>; 650*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 651*4882a593Smuzhiyun }; 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun cpus { 654*4882a593Smuzhiyun cpu0: cpu@0 { 655*4882a593Smuzhiyun cpu-supply = <&cpu_vdd_reg>; 656*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 657*4882a593Smuzhiyun }; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun cpu@1 { 660*4882a593Smuzhiyun cpu-supply = <&cpu_vdd_reg>; 661*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 662*4882a593Smuzhiyun }; 663*4882a593Smuzhiyun }; 664*4882a593Smuzhiyun}; 665