xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/tegra20-ventana.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/dts-v1/;
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
4*4882a593Smuzhiyun#include "tegra20.dtsi"
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/ {
7*4882a593Smuzhiyun	model = "NVIDIA Tegra20 Ventana evaluation board";
8*4882a593Smuzhiyun	compatible = "nvidia,ventana", "nvidia,tegra20";
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	chosen {
11*4882a593Smuzhiyun		stdout-path = &uartd;
12*4882a593Smuzhiyun	};
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	aliases {
15*4882a593Smuzhiyun		rtc0 = "/i2c@7000d000/tps6586x@34";
16*4882a593Smuzhiyun		rtc1 = "/rtc@7000e000";
17*4882a593Smuzhiyun		serial0 = &uartd;
18*4882a593Smuzhiyun		usb0 = "/usb@c5000000";
19*4882a593Smuzhiyun		usb1 = "/usb@c5004000";
20*4882a593Smuzhiyun		usb2 = "/usb@c5008000";
21*4882a593Smuzhiyun		mmc0 = "/sdhci@c8000600";
22*4882a593Smuzhiyun		mmc1 = "/sdhci@c8000400";
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	memory {
26*4882a593Smuzhiyun		reg = <0x00000000 0x40000000>;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	host1x@50000000 {
30*4882a593Smuzhiyun		status = "okay";
31*4882a593Smuzhiyun		dc@54200000 {
32*4882a593Smuzhiyun			status = "okay";
33*4882a593Smuzhiyun			rgb {
34*4882a593Smuzhiyun				status = "okay";
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun				nvidia,panel = <&panel>;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun				display-timings {
39*4882a593Smuzhiyun					timing@0 {
40*4882a593Smuzhiyun						/* Seaboard has 1366x768 */
41*4882a593Smuzhiyun						clock-frequency = <70600000>;
42*4882a593Smuzhiyun						hactive = <1366>;
43*4882a593Smuzhiyun						vactive = <768>;
44*4882a593Smuzhiyun						hback-porch = <58>;
45*4882a593Smuzhiyun						hfront-porch = <58>;
46*4882a593Smuzhiyun						hsync-len = <58>;
47*4882a593Smuzhiyun						vback-porch = <4>;
48*4882a593Smuzhiyun						vfront-porch = <4>;
49*4882a593Smuzhiyun						vsync-len = <4>;
50*4882a593Smuzhiyun						hsync-active = <1>;
51*4882a593Smuzhiyun					};
52*4882a593Smuzhiyun				};
53*4882a593Smuzhiyun			};
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		hdmi@54280000 {
57*4882a593Smuzhiyun			status = "okay";
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun			vdd-supply = <&hdmi_vdd_reg>;
60*4882a593Smuzhiyun			pll-supply = <&hdmi_pll_reg>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
63*4882a593Smuzhiyun			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
64*4882a593Smuzhiyun				GPIO_ACTIVE_HIGH>;
65*4882a593Smuzhiyun		};
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	pinmux@70000014 {
69*4882a593Smuzhiyun		pinctrl-names = "default";
70*4882a593Smuzhiyun		pinctrl-0 = <&state_default>;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		state_default: pinmux {
73*4882a593Smuzhiyun			ata {
74*4882a593Smuzhiyun				nvidia,pins = "ata";
75*4882a593Smuzhiyun				nvidia,function = "ide";
76*4882a593Smuzhiyun			};
77*4882a593Smuzhiyun			atb {
78*4882a593Smuzhiyun				nvidia,pins = "atb", "gma", "gme";
79*4882a593Smuzhiyun				nvidia,function = "sdio4";
80*4882a593Smuzhiyun			};
81*4882a593Smuzhiyun			atc {
82*4882a593Smuzhiyun				nvidia,pins = "atc";
83*4882a593Smuzhiyun				nvidia,function = "nand";
84*4882a593Smuzhiyun			};
85*4882a593Smuzhiyun			atd {
86*4882a593Smuzhiyun				nvidia,pins = "atd", "ate", "gmb", "spia",
87*4882a593Smuzhiyun					"spib", "spic";
88*4882a593Smuzhiyun				nvidia,function = "gmi";
89*4882a593Smuzhiyun			};
90*4882a593Smuzhiyun			cdev1 {
91*4882a593Smuzhiyun				nvidia,pins = "cdev1";
92*4882a593Smuzhiyun				nvidia,function = "plla_out";
93*4882a593Smuzhiyun			};
94*4882a593Smuzhiyun			cdev2 {
95*4882a593Smuzhiyun				nvidia,pins = "cdev2";
96*4882a593Smuzhiyun				nvidia,function = "pllp_out4";
97*4882a593Smuzhiyun			};
98*4882a593Smuzhiyun			crtp {
99*4882a593Smuzhiyun				nvidia,pins = "crtp", "lm1";
100*4882a593Smuzhiyun				nvidia,function = "crt";
101*4882a593Smuzhiyun			};
102*4882a593Smuzhiyun			csus {
103*4882a593Smuzhiyun				nvidia,pins = "csus";
104*4882a593Smuzhiyun				nvidia,function = "vi_sensor_clk";
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun			dap1 {
107*4882a593Smuzhiyun				nvidia,pins = "dap1";
108*4882a593Smuzhiyun				nvidia,function = "dap1";
109*4882a593Smuzhiyun			};
110*4882a593Smuzhiyun			dap2 {
111*4882a593Smuzhiyun				nvidia,pins = "dap2";
112*4882a593Smuzhiyun				nvidia,function = "dap2";
113*4882a593Smuzhiyun			};
114*4882a593Smuzhiyun			dap3 {
115*4882a593Smuzhiyun				nvidia,pins = "dap3";
116*4882a593Smuzhiyun				nvidia,function = "dap3";
117*4882a593Smuzhiyun			};
118*4882a593Smuzhiyun			dap4 {
119*4882a593Smuzhiyun				nvidia,pins = "dap4";
120*4882a593Smuzhiyun				nvidia,function = "dap4";
121*4882a593Smuzhiyun			};
122*4882a593Smuzhiyun			dta {
123*4882a593Smuzhiyun				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
124*4882a593Smuzhiyun				nvidia,function = "vi";
125*4882a593Smuzhiyun			};
126*4882a593Smuzhiyun			dtf {
127*4882a593Smuzhiyun				nvidia,pins = "dtf";
128*4882a593Smuzhiyun				nvidia,function = "i2c3";
129*4882a593Smuzhiyun			};
130*4882a593Smuzhiyun			gmc {
131*4882a593Smuzhiyun				nvidia,pins = "gmc";
132*4882a593Smuzhiyun				nvidia,function = "uartd";
133*4882a593Smuzhiyun			};
134*4882a593Smuzhiyun			gmd {
135*4882a593Smuzhiyun				nvidia,pins = "gmd";
136*4882a593Smuzhiyun				nvidia,function = "sflash";
137*4882a593Smuzhiyun			};
138*4882a593Smuzhiyun			gpu {
139*4882a593Smuzhiyun				nvidia,pins = "gpu";
140*4882a593Smuzhiyun				nvidia,function = "pwm";
141*4882a593Smuzhiyun			};
142*4882a593Smuzhiyun			gpu7 {
143*4882a593Smuzhiyun				nvidia,pins = "gpu7";
144*4882a593Smuzhiyun				nvidia,function = "rtck";
145*4882a593Smuzhiyun			};
146*4882a593Smuzhiyun			gpv {
147*4882a593Smuzhiyun				nvidia,pins = "gpv", "slxa", "slxk";
148*4882a593Smuzhiyun				nvidia,function = "pcie";
149*4882a593Smuzhiyun			};
150*4882a593Smuzhiyun			hdint {
151*4882a593Smuzhiyun				nvidia,pins = "hdint";
152*4882a593Smuzhiyun				nvidia,function = "hdmi";
153*4882a593Smuzhiyun			};
154*4882a593Smuzhiyun			i2cp {
155*4882a593Smuzhiyun				nvidia,pins = "i2cp";
156*4882a593Smuzhiyun				nvidia,function = "i2cp";
157*4882a593Smuzhiyun			};
158*4882a593Smuzhiyun			irrx {
159*4882a593Smuzhiyun				nvidia,pins = "irrx", "irtx";
160*4882a593Smuzhiyun				nvidia,function = "uartb";
161*4882a593Smuzhiyun			};
162*4882a593Smuzhiyun			kbca {
163*4882a593Smuzhiyun				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
164*4882a593Smuzhiyun					"kbce", "kbcf";
165*4882a593Smuzhiyun				nvidia,function = "kbc";
166*4882a593Smuzhiyun			};
167*4882a593Smuzhiyun			lcsn {
168*4882a593Smuzhiyun				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
169*4882a593Smuzhiyun					"lsdi", "lvp0";
170*4882a593Smuzhiyun				nvidia,function = "rsvd4";
171*4882a593Smuzhiyun			};
172*4882a593Smuzhiyun			ld0 {
173*4882a593Smuzhiyun				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
174*4882a593Smuzhiyun					"ld5", "ld6", "ld7", "ld8", "ld9",
175*4882a593Smuzhiyun					"ld10", "ld11", "ld12", "ld13", "ld14",
176*4882a593Smuzhiyun					"ld15", "ld16", "ld17", "ldi", "lhp0",
177*4882a593Smuzhiyun					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
178*4882a593Smuzhiyun					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
179*4882a593Smuzhiyun					"lspi", "lvp1", "lvs";
180*4882a593Smuzhiyun				nvidia,function = "displaya";
181*4882a593Smuzhiyun			};
182*4882a593Smuzhiyun			owc {
183*4882a593Smuzhiyun				nvidia,pins = "owc", "spdi", "spdo", "uac";
184*4882a593Smuzhiyun				nvidia,function = "rsvd2";
185*4882a593Smuzhiyun			};
186*4882a593Smuzhiyun			pmc {
187*4882a593Smuzhiyun				nvidia,pins = "pmc";
188*4882a593Smuzhiyun				nvidia,function = "pwr_on";
189*4882a593Smuzhiyun			};
190*4882a593Smuzhiyun			rm {
191*4882a593Smuzhiyun				nvidia,pins = "rm";
192*4882a593Smuzhiyun				nvidia,function = "i2c1";
193*4882a593Smuzhiyun			};
194*4882a593Smuzhiyun			sdb {
195*4882a593Smuzhiyun				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
196*4882a593Smuzhiyun				nvidia,function = "sdio3";
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun			sdio1 {
199*4882a593Smuzhiyun				nvidia,pins = "sdio1";
200*4882a593Smuzhiyun				nvidia,function = "sdio1";
201*4882a593Smuzhiyun			};
202*4882a593Smuzhiyun			slxd {
203*4882a593Smuzhiyun				nvidia,pins = "slxd";
204*4882a593Smuzhiyun				nvidia,function = "spdif";
205*4882a593Smuzhiyun			};
206*4882a593Smuzhiyun			spid {
207*4882a593Smuzhiyun				nvidia,pins = "spid", "spie", "spif";
208*4882a593Smuzhiyun				nvidia,function = "spi1";
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun			spig {
211*4882a593Smuzhiyun				nvidia,pins = "spig", "spih";
212*4882a593Smuzhiyun				nvidia,function = "spi2_alt";
213*4882a593Smuzhiyun			};
214*4882a593Smuzhiyun			uaa {
215*4882a593Smuzhiyun				nvidia,pins = "uaa", "uab", "uda";
216*4882a593Smuzhiyun				nvidia,function = "ulpi";
217*4882a593Smuzhiyun			};
218*4882a593Smuzhiyun			uad {
219*4882a593Smuzhiyun				nvidia,pins = "uad";
220*4882a593Smuzhiyun				nvidia,function = "irda";
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun			uca {
223*4882a593Smuzhiyun				nvidia,pins = "uca", "ucb";
224*4882a593Smuzhiyun				nvidia,function = "uartc";
225*4882a593Smuzhiyun			};
226*4882a593Smuzhiyun			conf_ata {
227*4882a593Smuzhiyun				nvidia,pins = "ata", "atb", "atc", "atd",
228*4882a593Smuzhiyun					"cdev1", "cdev2", "dap1", "dap2",
229*4882a593Smuzhiyun					"dap4", "ddc", "dtf", "gma", "gmc",
230*4882a593Smuzhiyun					"gme", "gpu", "gpu7", "i2cp", "irrx",
231*4882a593Smuzhiyun					"irtx", "pta", "rm", "sdc", "sdd",
232*4882a593Smuzhiyun					"slxc", "slxd", "slxk", "spdi", "spdo",
233*4882a593Smuzhiyun					"uac", "uad", "uca", "ucb", "uda";
234*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
236*4882a593Smuzhiyun			};
237*4882a593Smuzhiyun			conf_ate {
238*4882a593Smuzhiyun				nvidia,pins = "ate", "csus", "dap3", "gmd",
239*4882a593Smuzhiyun					"gpv", "owc", "spia", "spib", "spic",
240*4882a593Smuzhiyun					"spid", "spie", "spig";
241*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
242*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
243*4882a593Smuzhiyun			};
244*4882a593Smuzhiyun			conf_ck32 {
245*4882a593Smuzhiyun				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
246*4882a593Smuzhiyun					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
247*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248*4882a593Smuzhiyun			};
249*4882a593Smuzhiyun			conf_crtp {
250*4882a593Smuzhiyun				nvidia,pins = "crtp", "gmb", "slxa", "spih";
251*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
252*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
253*4882a593Smuzhiyun			};
254*4882a593Smuzhiyun			conf_dta {
255*4882a593Smuzhiyun				nvidia,pins = "dta", "dtb", "dtc", "dtd";
256*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
257*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun			conf_dte {
260*4882a593Smuzhiyun				nvidia,pins = "dte", "spif";
261*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
262*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
263*4882a593Smuzhiyun			};
264*4882a593Smuzhiyun			conf_hdint {
265*4882a593Smuzhiyun				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
266*4882a593Smuzhiyun					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
267*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
268*4882a593Smuzhiyun			};
269*4882a593Smuzhiyun			conf_kbca {
270*4882a593Smuzhiyun				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
271*4882a593Smuzhiyun					"kbce", "kbcf", "sdio1", "uaa", "uab";
272*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
273*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
274*4882a593Smuzhiyun			};
275*4882a593Smuzhiyun			conf_lc {
276*4882a593Smuzhiyun				nvidia,pins = "lc", "ls";
277*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
278*4882a593Smuzhiyun			};
279*4882a593Smuzhiyun			conf_ld0 {
280*4882a593Smuzhiyun				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
281*4882a593Smuzhiyun					"ld5", "ld6", "ld7", "ld8", "ld9",
282*4882a593Smuzhiyun					"ld10", "ld11", "ld12", "ld13", "ld14",
283*4882a593Smuzhiyun					"ld15", "ld16", "ld17", "ldi", "lhp0",
284*4882a593Smuzhiyun					"lhp1", "lhp2", "lhs", "lm0", "lpp",
285*4882a593Smuzhiyun					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
286*4882a593Smuzhiyun					"lvp1", "lvs", "pmc", "sdb";
287*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
288*4882a593Smuzhiyun			};
289*4882a593Smuzhiyun			conf_ld17_0 {
290*4882a593Smuzhiyun				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
291*4882a593Smuzhiyun					"ld23_22";
292*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
293*4882a593Smuzhiyun			};
294*4882a593Smuzhiyun			drive_sdio1 {
295*4882a593Smuzhiyun				nvidia,pins = "drive_sdio1";
296*4882a593Smuzhiyun				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
297*4882a593Smuzhiyun				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
298*4882a593Smuzhiyun				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
299*4882a593Smuzhiyun				nvidia,pull-down-strength = <31>;
300*4882a593Smuzhiyun				nvidia,pull-up-strength = <31>;
301*4882a593Smuzhiyun				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
302*4882a593Smuzhiyun				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
303*4882a593Smuzhiyun			};
304*4882a593Smuzhiyun		};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun		state_i2cmux_ddc: pinmux_i2cmux_ddc {
307*4882a593Smuzhiyun			ddc {
308*4882a593Smuzhiyun				nvidia,pins = "ddc";
309*4882a593Smuzhiyun				nvidia,function = "i2c2";
310*4882a593Smuzhiyun			};
311*4882a593Smuzhiyun			pta {
312*4882a593Smuzhiyun				nvidia,pins = "pta";
313*4882a593Smuzhiyun				nvidia,function = "rsvd4";
314*4882a593Smuzhiyun			};
315*4882a593Smuzhiyun		};
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun		state_i2cmux_pta: pinmux_i2cmux_pta {
318*4882a593Smuzhiyun			ddc {
319*4882a593Smuzhiyun				nvidia,pins = "ddc";
320*4882a593Smuzhiyun				nvidia,function = "rsvd4";
321*4882a593Smuzhiyun			};
322*4882a593Smuzhiyun			pta {
323*4882a593Smuzhiyun				nvidia,pins = "pta";
324*4882a593Smuzhiyun				nvidia,function = "i2c2";
325*4882a593Smuzhiyun			};
326*4882a593Smuzhiyun		};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun		state_i2cmux_idle: pinmux_i2cmux_idle {
329*4882a593Smuzhiyun			ddc {
330*4882a593Smuzhiyun				nvidia,pins = "ddc";
331*4882a593Smuzhiyun				nvidia,function = "rsvd4";
332*4882a593Smuzhiyun			};
333*4882a593Smuzhiyun			pta {
334*4882a593Smuzhiyun				nvidia,pins = "pta";
335*4882a593Smuzhiyun				nvidia,function = "rsvd4";
336*4882a593Smuzhiyun			};
337*4882a593Smuzhiyun		};
338*4882a593Smuzhiyun	};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun	i2s@70002800 {
341*4882a593Smuzhiyun		status = "okay";
342*4882a593Smuzhiyun	};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun	serial@70006300 {
345*4882a593Smuzhiyun		status = "okay";
346*4882a593Smuzhiyun		clock-frequency = < 216000000 >;	};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun	pwm: pwm@7000a000 {
349*4882a593Smuzhiyun		status = "okay";
350*4882a593Smuzhiyun	};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun	i2c@7000c000 {
353*4882a593Smuzhiyun		status = "okay";
354*4882a593Smuzhiyun		clock-frequency = <400000>;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun		wm8903: wm8903@1a {
357*4882a593Smuzhiyun			compatible = "wlf,wm8903";
358*4882a593Smuzhiyun			reg = <0x1a>;
359*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
360*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun			gpio-controller;
363*4882a593Smuzhiyun			#gpio-cells = <2>;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun			micdet-cfg = <0>;
366*4882a593Smuzhiyun			micdet-delay = <100>;
367*4882a593Smuzhiyun			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
368*4882a593Smuzhiyun		};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun		/* ALS and proximity sensor */
371*4882a593Smuzhiyun		isl29018@44 {
372*4882a593Smuzhiyun			compatible = "isil,isl29018";
373*4882a593Smuzhiyun			reg = <0x44>;
374*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
375*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
376*4882a593Smuzhiyun		};
377*4882a593Smuzhiyun	};
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun	i2c@7000c400 {
380*4882a593Smuzhiyun		status = "okay";
381*4882a593Smuzhiyun		clock-frequency = <100000>;
382*4882a593Smuzhiyun	};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun	i2cmux {
385*4882a593Smuzhiyun		compatible = "i2c-mux-pinctrl";
386*4882a593Smuzhiyun		#address-cells = <1>;
387*4882a593Smuzhiyun		#size-cells = <0>;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun		i2c-parent = <&{/i2c@7000c400}>;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun		pinctrl-names = "ddc", "pta", "idle";
392*4882a593Smuzhiyun		pinctrl-0 = <&state_i2cmux_ddc>;
393*4882a593Smuzhiyun		pinctrl-1 = <&state_i2cmux_pta>;
394*4882a593Smuzhiyun		pinctrl-2 = <&state_i2cmux_idle>;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun		hdmi_ddc: i2c@0 {
397*4882a593Smuzhiyun			reg = <0>;
398*4882a593Smuzhiyun			#address-cells = <1>;
399*4882a593Smuzhiyun			#size-cells = <0>;
400*4882a593Smuzhiyun		};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun		lvds_ddc: i2c@1 {
403*4882a593Smuzhiyun			reg = <1>;
404*4882a593Smuzhiyun			#address-cells = <1>;
405*4882a593Smuzhiyun			#size-cells = <0>;
406*4882a593Smuzhiyun		};
407*4882a593Smuzhiyun	};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun	i2c@7000c500 {
410*4882a593Smuzhiyun		status = "okay";
411*4882a593Smuzhiyun		clock-frequency = <400000>;
412*4882a593Smuzhiyun	};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun	i2c@7000d000 {
415*4882a593Smuzhiyun		status = "okay";
416*4882a593Smuzhiyun		clock-frequency = <400000>;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun		pmic: tps6586x@34 {
419*4882a593Smuzhiyun			compatible = "ti,tps6586x";
420*4882a593Smuzhiyun			reg = <0x34>;
421*4882a593Smuzhiyun			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun			ti,system-power-controller;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun			#gpio-cells = <2>;
426*4882a593Smuzhiyun			gpio-controller;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun			sys-supply = <&vdd_5v0_reg>;
429*4882a593Smuzhiyun			vin-sm0-supply = <&sys_reg>;
430*4882a593Smuzhiyun			vin-sm1-supply = <&sys_reg>;
431*4882a593Smuzhiyun			vin-sm2-supply = <&sys_reg>;
432*4882a593Smuzhiyun			vinldo01-supply = <&sm2_reg>;
433*4882a593Smuzhiyun			vinldo23-supply = <&sm2_reg>;
434*4882a593Smuzhiyun			vinldo4-supply = <&sm2_reg>;
435*4882a593Smuzhiyun			vinldo678-supply = <&sm2_reg>;
436*4882a593Smuzhiyun			vinldo9-supply = <&sm2_reg>;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun			regulators {
439*4882a593Smuzhiyun				sys_reg: sys {
440*4882a593Smuzhiyun					regulator-name = "vdd_sys";
441*4882a593Smuzhiyun					regulator-always-on;
442*4882a593Smuzhiyun				};
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun				sm0 {
445*4882a593Smuzhiyun					regulator-name = "vdd_sm0,vdd_core";
446*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
447*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
448*4882a593Smuzhiyun					regulator-always-on;
449*4882a593Smuzhiyun				};
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun				sm1 {
452*4882a593Smuzhiyun					regulator-name = "vdd_sm1,vdd_cpu";
453*4882a593Smuzhiyun					regulator-min-microvolt = <1000000>;
454*4882a593Smuzhiyun					regulator-max-microvolt = <1000000>;
455*4882a593Smuzhiyun					regulator-always-on;
456*4882a593Smuzhiyun				};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun				sm2_reg: sm2 {
459*4882a593Smuzhiyun					regulator-name = "vdd_sm2,vin_ldo*";
460*4882a593Smuzhiyun					regulator-min-microvolt = <3700000>;
461*4882a593Smuzhiyun					regulator-max-microvolt = <3700000>;
462*4882a593Smuzhiyun					regulator-always-on;
463*4882a593Smuzhiyun				};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun				/* LDO0 is not connected to anything */
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun				ldo1 {
468*4882a593Smuzhiyun					regulator-name = "vdd_ldo1,avdd_pll*";
469*4882a593Smuzhiyun					regulator-min-microvolt = <1100000>;
470*4882a593Smuzhiyun					regulator-max-microvolt = <1100000>;
471*4882a593Smuzhiyun					regulator-always-on;
472*4882a593Smuzhiyun				};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun				ldo2 {
475*4882a593Smuzhiyun					regulator-name = "vdd_ldo2,vdd_rtc";
476*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
477*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
478*4882a593Smuzhiyun				};
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun				ldo3 {
481*4882a593Smuzhiyun					regulator-name = "vdd_ldo3,avdd_usb*";
482*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
483*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
484*4882a593Smuzhiyun					regulator-always-on;
485*4882a593Smuzhiyun				};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun				ldo4 {
488*4882a593Smuzhiyun					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
489*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
490*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
491*4882a593Smuzhiyun					regulator-always-on;
492*4882a593Smuzhiyun				};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun				ldo5 {
495*4882a593Smuzhiyun					regulator-name = "vdd_ldo5,vcore_mmc";
496*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
497*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
498*4882a593Smuzhiyun					regulator-always-on;
499*4882a593Smuzhiyun				};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun				ldo6 {
502*4882a593Smuzhiyun					regulator-name = "vdd_ldo6,avdd_vdac";
503*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
504*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
505*4882a593Smuzhiyun				};
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun				hdmi_vdd_reg: ldo7 {
508*4882a593Smuzhiyun					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
509*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
510*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
511*4882a593Smuzhiyun				};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun				hdmi_pll_reg: ldo8 {
514*4882a593Smuzhiyun					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
515*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
516*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
517*4882a593Smuzhiyun				};
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun				ldo9 {
520*4882a593Smuzhiyun					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
521*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
522*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
523*4882a593Smuzhiyun					regulator-always-on;
524*4882a593Smuzhiyun				};
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun				ldo_rtc {
527*4882a593Smuzhiyun					regulator-name = "vdd_rtc_out,vdd_cell";
528*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
529*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
530*4882a593Smuzhiyun					regulator-always-on;
531*4882a593Smuzhiyun				};
532*4882a593Smuzhiyun			};
533*4882a593Smuzhiyun		};
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun		temperature-sensor@4c {
536*4882a593Smuzhiyun			compatible = "onnn,nct1008";
537*4882a593Smuzhiyun			reg = <0x4c>;
538*4882a593Smuzhiyun		};
539*4882a593Smuzhiyun	};
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun	pmc@7000e400 {
542*4882a593Smuzhiyun		nvidia,invert-interrupt;
543*4882a593Smuzhiyun		nvidia,suspend-mode = <1>;
544*4882a593Smuzhiyun		nvidia,cpu-pwr-good-time = <2000>;
545*4882a593Smuzhiyun		nvidia,cpu-pwr-off-time = <100>;
546*4882a593Smuzhiyun		nvidia,core-pwr-good-time = <3845 3845>;
547*4882a593Smuzhiyun		nvidia,core-pwr-off-time = <458>;
548*4882a593Smuzhiyun		nvidia,sys-clock-req-active-high;
549*4882a593Smuzhiyun	};
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun	usb@c5000000 {
552*4882a593Smuzhiyun		status = "okay";
553*4882a593Smuzhiyun	};
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun	usb-phy@c5000000 {
556*4882a593Smuzhiyun		status = "okay";
557*4882a593Smuzhiyun	};
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun	usb@c5004000 {
560*4882a593Smuzhiyun		status = "okay";
561*4882a593Smuzhiyun		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
562*4882a593Smuzhiyun			GPIO_ACTIVE_LOW>;
563*4882a593Smuzhiyun	};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun	usb-phy@c5004000 {
566*4882a593Smuzhiyun		status = "okay";
567*4882a593Smuzhiyun		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
568*4882a593Smuzhiyun			GPIO_ACTIVE_LOW>;
569*4882a593Smuzhiyun	};
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun	usb@c5008000 {
572*4882a593Smuzhiyun		status = "okay";
573*4882a593Smuzhiyun	};
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun	usb-phy@c5008000 {
576*4882a593Smuzhiyun		status = "okay";
577*4882a593Smuzhiyun	};
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun	sdhci@c8000000 {
580*4882a593Smuzhiyun		status = "okay";
581*4882a593Smuzhiyun		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
582*4882a593Smuzhiyun		bus-width = <4>;
583*4882a593Smuzhiyun		keep-power-in-suspend;
584*4882a593Smuzhiyun	};
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun	sdhci@c8000400 {
587*4882a593Smuzhiyun		status = "okay";
588*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
589*4882a593Smuzhiyun		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
590*4882a593Smuzhiyun		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
591*4882a593Smuzhiyun		bus-width = <4>;
592*4882a593Smuzhiyun	};
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun	sdhci@c8000600 {
595*4882a593Smuzhiyun		status = "okay";
596*4882a593Smuzhiyun		bus-width = <8>;
597*4882a593Smuzhiyun		non-removable;
598*4882a593Smuzhiyun	};
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun	backlight: backlight {
601*4882a593Smuzhiyun		compatible = "pwm-backlight";
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
604*4882a593Smuzhiyun		power-supply = <&vdd_bl_reg>;
605*4882a593Smuzhiyun		pwms = <&pwm 2 5000000>;
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
608*4882a593Smuzhiyun		default-brightness-level = <6>;
609*4882a593Smuzhiyun	};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun	clocks {
612*4882a593Smuzhiyun		compatible = "simple-bus";
613*4882a593Smuzhiyun		#address-cells = <1>;
614*4882a593Smuzhiyun		#size-cells = <0>;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun		clk32k_in: clock@0 {
617*4882a593Smuzhiyun			compatible = "fixed-clock";
618*4882a593Smuzhiyun			reg=<0>;
619*4882a593Smuzhiyun			#clock-cells = <0>;
620*4882a593Smuzhiyun			clock-frequency = <32768>;
621*4882a593Smuzhiyun		};
622*4882a593Smuzhiyun	};
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun	gpio-keys {
625*4882a593Smuzhiyun		compatible = "gpio-keys";
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun		power {
628*4882a593Smuzhiyun			label = "Power";
629*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
630*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
631*4882a593Smuzhiyun			gpio-key,wakeup;
632*4882a593Smuzhiyun		};
633*4882a593Smuzhiyun	};
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun	panel: panel {
636*4882a593Smuzhiyun		compatible = "chunghwa,claa101wa01a", "simple-panel";
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun		power-supply = <&vdd_pnl_reg>;
639*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun		backlight = <&backlight>;
642*4882a593Smuzhiyun		ddc-i2c-bus = <&lvds_ddc>;
643*4882a593Smuzhiyun	};
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun	regulators {
646*4882a593Smuzhiyun		compatible = "simple-bus";
647*4882a593Smuzhiyun		#address-cells = <1>;
648*4882a593Smuzhiyun		#size-cells = <0>;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun		vdd_5v0_reg: regulator@0 {
651*4882a593Smuzhiyun			compatible = "regulator-fixed";
652*4882a593Smuzhiyun			reg = <0>;
653*4882a593Smuzhiyun			regulator-name = "vdd_5v0";
654*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
655*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
656*4882a593Smuzhiyun			regulator-always-on;
657*4882a593Smuzhiyun		};
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun		regulator@1 {
660*4882a593Smuzhiyun			compatible = "regulator-fixed";
661*4882a593Smuzhiyun			reg = <1>;
662*4882a593Smuzhiyun			regulator-name = "vdd_1v5";
663*4882a593Smuzhiyun			regulator-min-microvolt = <1500000>;
664*4882a593Smuzhiyun			regulator-max-microvolt = <1500000>;
665*4882a593Smuzhiyun			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
666*4882a593Smuzhiyun		};
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun		regulator@2 {
669*4882a593Smuzhiyun			compatible = "regulator-fixed";
670*4882a593Smuzhiyun			reg = <2>;
671*4882a593Smuzhiyun			regulator-name = "vdd_1v2";
672*4882a593Smuzhiyun			regulator-min-microvolt = <1200000>;
673*4882a593Smuzhiyun			regulator-max-microvolt = <1200000>;
674*4882a593Smuzhiyun			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
675*4882a593Smuzhiyun			enable-active-high;
676*4882a593Smuzhiyun		};
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun		vdd_pnl_reg: regulator@3 {
679*4882a593Smuzhiyun			compatible = "regulator-fixed";
680*4882a593Smuzhiyun			reg = <3>;
681*4882a593Smuzhiyun			regulator-name = "vdd_pnl";
682*4882a593Smuzhiyun			regulator-min-microvolt = <2800000>;
683*4882a593Smuzhiyun			regulator-max-microvolt = <2800000>;
684*4882a593Smuzhiyun			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
685*4882a593Smuzhiyun			enable-active-high;
686*4882a593Smuzhiyun		};
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun		vdd_bl_reg: regulator@4 {
689*4882a593Smuzhiyun			compatible = "regulator-fixed";
690*4882a593Smuzhiyun			reg = <4>;
691*4882a593Smuzhiyun			regulator-name = "vdd_bl";
692*4882a593Smuzhiyun			regulator-min-microvolt = <2800000>;
693*4882a593Smuzhiyun			regulator-max-microvolt = <2800000>;
694*4882a593Smuzhiyun			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
695*4882a593Smuzhiyun			enable-active-high;
696*4882a593Smuzhiyun		};
697*4882a593Smuzhiyun	};
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun	sound {
700*4882a593Smuzhiyun		compatible = "nvidia,tegra-audio-wm8903-ventana",
701*4882a593Smuzhiyun			     "nvidia,tegra-audio-wm8903";
702*4882a593Smuzhiyun		nvidia,model = "NVIDIA Tegra Ventana";
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun		nvidia,audio-routing =
705*4882a593Smuzhiyun			"Headphone Jack", "HPOUTR",
706*4882a593Smuzhiyun			"Headphone Jack", "HPOUTL",
707*4882a593Smuzhiyun			"Int Spk", "ROP",
708*4882a593Smuzhiyun			"Int Spk", "RON",
709*4882a593Smuzhiyun			"Int Spk", "LOP",
710*4882a593Smuzhiyun			"Int Spk", "LON",
711*4882a593Smuzhiyun			"Mic Jack", "MICBIAS",
712*4882a593Smuzhiyun			"IN1L", "Mic Jack";
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun		nvidia,i2s-controller = <&tegra_i2s1>;
715*4882a593Smuzhiyun		nvidia,audio-codec = <&wm8903>;
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
718*4882a593Smuzhiyun		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
719*4882a593Smuzhiyun		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
720*4882a593Smuzhiyun			GPIO_ACTIVE_HIGH>;
721*4882a593Smuzhiyun		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
722*4882a593Smuzhiyun			GPIO_ACTIVE_HIGH>;
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
725*4882a593Smuzhiyun			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
726*4882a593Smuzhiyun			 <&tegra_car TEGRA20_CLK_CDEV1>;
727*4882a593Smuzhiyun		clock-names = "pll_a", "pll_a_out0", "mclk";
728*4882a593Smuzhiyun	};
729*4882a593Smuzhiyun};
730