xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/tegra20-ventana.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/dts-v1/;
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
5*4882a593Smuzhiyun#include "tegra20.dtsi"
6*4882a593Smuzhiyun#include "tegra20-cpu-opp.dtsi"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	model = "NVIDIA Tegra20 Ventana evaluation board";
10*4882a593Smuzhiyun	compatible = "nvidia,ventana", "nvidia,tegra20";
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun	aliases {
13*4882a593Smuzhiyun		rtc0 = "/i2c@7000d000/tps6586x@34";
14*4882a593Smuzhiyun		rtc1 = "/rtc@7000e000";
15*4882a593Smuzhiyun		serial0 = &uartd;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	chosen {
19*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	memory@0 {
23*4882a593Smuzhiyun		reg = <0x00000000 0x40000000>;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	host1x@50000000 {
27*4882a593Smuzhiyun		dc@54200000 {
28*4882a593Smuzhiyun			rgb {
29*4882a593Smuzhiyun				status = "okay";
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun				nvidia,panel = <&panel>;
32*4882a593Smuzhiyun			};
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		hdmi@54280000 {
36*4882a593Smuzhiyun			status = "okay";
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun			vdd-supply = <&hdmi_vdd_reg>;
39*4882a593Smuzhiyun			pll-supply = <&hdmi_pll_reg>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42*4882a593Smuzhiyun			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
43*4882a593Smuzhiyun				GPIO_ACTIVE_HIGH>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	pinmux@70000014 {
48*4882a593Smuzhiyun		pinctrl-names = "default";
49*4882a593Smuzhiyun		pinctrl-0 = <&state_default>;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		state_default: pinmux {
52*4882a593Smuzhiyun			ata {
53*4882a593Smuzhiyun				nvidia,pins = "ata";
54*4882a593Smuzhiyun				nvidia,function = "ide";
55*4882a593Smuzhiyun			};
56*4882a593Smuzhiyun			atb {
57*4882a593Smuzhiyun				nvidia,pins = "atb", "gma", "gme";
58*4882a593Smuzhiyun				nvidia,function = "sdio4";
59*4882a593Smuzhiyun			};
60*4882a593Smuzhiyun			atc {
61*4882a593Smuzhiyun				nvidia,pins = "atc";
62*4882a593Smuzhiyun				nvidia,function = "nand";
63*4882a593Smuzhiyun			};
64*4882a593Smuzhiyun			atd {
65*4882a593Smuzhiyun				nvidia,pins = "atd", "ate", "gmb", "spia",
66*4882a593Smuzhiyun					"spib", "spic";
67*4882a593Smuzhiyun				nvidia,function = "gmi";
68*4882a593Smuzhiyun			};
69*4882a593Smuzhiyun			cdev1 {
70*4882a593Smuzhiyun				nvidia,pins = "cdev1";
71*4882a593Smuzhiyun				nvidia,function = "plla_out";
72*4882a593Smuzhiyun			};
73*4882a593Smuzhiyun			cdev2 {
74*4882a593Smuzhiyun				nvidia,pins = "cdev2";
75*4882a593Smuzhiyun				nvidia,function = "pllp_out4";
76*4882a593Smuzhiyun			};
77*4882a593Smuzhiyun			crtp {
78*4882a593Smuzhiyun				nvidia,pins = "crtp", "lm1";
79*4882a593Smuzhiyun				nvidia,function = "crt";
80*4882a593Smuzhiyun			};
81*4882a593Smuzhiyun			csus {
82*4882a593Smuzhiyun				nvidia,pins = "csus";
83*4882a593Smuzhiyun				nvidia,function = "vi_sensor_clk";
84*4882a593Smuzhiyun			};
85*4882a593Smuzhiyun			dap1 {
86*4882a593Smuzhiyun				nvidia,pins = "dap1";
87*4882a593Smuzhiyun				nvidia,function = "dap1";
88*4882a593Smuzhiyun			};
89*4882a593Smuzhiyun			dap2 {
90*4882a593Smuzhiyun				nvidia,pins = "dap2";
91*4882a593Smuzhiyun				nvidia,function = "dap2";
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun			dap3 {
94*4882a593Smuzhiyun				nvidia,pins = "dap3";
95*4882a593Smuzhiyun				nvidia,function = "dap3";
96*4882a593Smuzhiyun			};
97*4882a593Smuzhiyun			dap4 {
98*4882a593Smuzhiyun				nvidia,pins = "dap4";
99*4882a593Smuzhiyun				nvidia,function = "dap4";
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun			dta {
102*4882a593Smuzhiyun				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
103*4882a593Smuzhiyun				nvidia,function = "vi";
104*4882a593Smuzhiyun			};
105*4882a593Smuzhiyun			dtf {
106*4882a593Smuzhiyun				nvidia,pins = "dtf";
107*4882a593Smuzhiyun				nvidia,function = "i2c3";
108*4882a593Smuzhiyun			};
109*4882a593Smuzhiyun			gmc {
110*4882a593Smuzhiyun				nvidia,pins = "gmc";
111*4882a593Smuzhiyun				nvidia,function = "uartd";
112*4882a593Smuzhiyun			};
113*4882a593Smuzhiyun			gmd {
114*4882a593Smuzhiyun				nvidia,pins = "gmd";
115*4882a593Smuzhiyun				nvidia,function = "sflash";
116*4882a593Smuzhiyun			};
117*4882a593Smuzhiyun			gpu {
118*4882a593Smuzhiyun				nvidia,pins = "gpu";
119*4882a593Smuzhiyun				nvidia,function = "pwm";
120*4882a593Smuzhiyun			};
121*4882a593Smuzhiyun			gpu7 {
122*4882a593Smuzhiyun				nvidia,pins = "gpu7";
123*4882a593Smuzhiyun				nvidia,function = "rtck";
124*4882a593Smuzhiyun			};
125*4882a593Smuzhiyun			gpv {
126*4882a593Smuzhiyun				nvidia,pins = "gpv", "slxa", "slxk";
127*4882a593Smuzhiyun				nvidia,function = "pcie";
128*4882a593Smuzhiyun			};
129*4882a593Smuzhiyun			hdint {
130*4882a593Smuzhiyun				nvidia,pins = "hdint";
131*4882a593Smuzhiyun				nvidia,function = "hdmi";
132*4882a593Smuzhiyun			};
133*4882a593Smuzhiyun			i2cp {
134*4882a593Smuzhiyun				nvidia,pins = "i2cp";
135*4882a593Smuzhiyun				nvidia,function = "i2cp";
136*4882a593Smuzhiyun			};
137*4882a593Smuzhiyun			irrx {
138*4882a593Smuzhiyun				nvidia,pins = "irrx", "irtx";
139*4882a593Smuzhiyun				nvidia,function = "uartb";
140*4882a593Smuzhiyun			};
141*4882a593Smuzhiyun			kbca {
142*4882a593Smuzhiyun				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
143*4882a593Smuzhiyun					"kbce", "kbcf";
144*4882a593Smuzhiyun				nvidia,function = "kbc";
145*4882a593Smuzhiyun			};
146*4882a593Smuzhiyun			lcsn {
147*4882a593Smuzhiyun				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
148*4882a593Smuzhiyun					"lsdi", "lvp0";
149*4882a593Smuzhiyun				nvidia,function = "rsvd4";
150*4882a593Smuzhiyun			};
151*4882a593Smuzhiyun			ld0 {
152*4882a593Smuzhiyun				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
153*4882a593Smuzhiyun					"ld5", "ld6", "ld7", "ld8", "ld9",
154*4882a593Smuzhiyun					"ld10", "ld11", "ld12", "ld13", "ld14",
155*4882a593Smuzhiyun					"ld15", "ld16", "ld17", "ldi", "lhp0",
156*4882a593Smuzhiyun					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
157*4882a593Smuzhiyun					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
158*4882a593Smuzhiyun					"lspi", "lvp1", "lvs";
159*4882a593Smuzhiyun				nvidia,function = "displaya";
160*4882a593Smuzhiyun			};
161*4882a593Smuzhiyun			owc {
162*4882a593Smuzhiyun				nvidia,pins = "owc", "spdi", "spdo", "uac";
163*4882a593Smuzhiyun				nvidia,function = "rsvd2";
164*4882a593Smuzhiyun			};
165*4882a593Smuzhiyun			pmc {
166*4882a593Smuzhiyun				nvidia,pins = "pmc";
167*4882a593Smuzhiyun				nvidia,function = "pwr_on";
168*4882a593Smuzhiyun			};
169*4882a593Smuzhiyun			rm {
170*4882a593Smuzhiyun				nvidia,pins = "rm";
171*4882a593Smuzhiyun				nvidia,function = "i2c1";
172*4882a593Smuzhiyun			};
173*4882a593Smuzhiyun			sdb {
174*4882a593Smuzhiyun				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
175*4882a593Smuzhiyun				nvidia,function = "sdio3";
176*4882a593Smuzhiyun			};
177*4882a593Smuzhiyun			sdio1 {
178*4882a593Smuzhiyun				nvidia,pins = "sdio1";
179*4882a593Smuzhiyun				nvidia,function = "sdio1";
180*4882a593Smuzhiyun			};
181*4882a593Smuzhiyun			slxd {
182*4882a593Smuzhiyun				nvidia,pins = "slxd";
183*4882a593Smuzhiyun				nvidia,function = "spdif";
184*4882a593Smuzhiyun			};
185*4882a593Smuzhiyun			spid {
186*4882a593Smuzhiyun				nvidia,pins = "spid", "spie", "spif";
187*4882a593Smuzhiyun				nvidia,function = "spi1";
188*4882a593Smuzhiyun			};
189*4882a593Smuzhiyun			spig {
190*4882a593Smuzhiyun				nvidia,pins = "spig", "spih";
191*4882a593Smuzhiyun				nvidia,function = "spi2_alt";
192*4882a593Smuzhiyun			};
193*4882a593Smuzhiyun			uaa {
194*4882a593Smuzhiyun				nvidia,pins = "uaa", "uab", "uda";
195*4882a593Smuzhiyun				nvidia,function = "ulpi";
196*4882a593Smuzhiyun			};
197*4882a593Smuzhiyun			uad {
198*4882a593Smuzhiyun				nvidia,pins = "uad";
199*4882a593Smuzhiyun				nvidia,function = "irda";
200*4882a593Smuzhiyun			};
201*4882a593Smuzhiyun			uca {
202*4882a593Smuzhiyun				nvidia,pins = "uca", "ucb";
203*4882a593Smuzhiyun				nvidia,function = "uartc";
204*4882a593Smuzhiyun			};
205*4882a593Smuzhiyun			conf_ata {
206*4882a593Smuzhiyun				nvidia,pins = "ata", "atb", "atc", "atd",
207*4882a593Smuzhiyun					"cdev1", "cdev2", "dap1", "dap2",
208*4882a593Smuzhiyun					"dap4", "ddc", "dtf", "gma", "gmc",
209*4882a593Smuzhiyun					"gme", "gpu", "gpu7", "i2cp", "irrx",
210*4882a593Smuzhiyun					"irtx", "pta", "rm", "sdc", "sdd",
211*4882a593Smuzhiyun					"slxc", "slxd", "slxk", "spdi", "spdo",
212*4882a593Smuzhiyun					"uac", "uad", "uca", "ucb", "uda";
213*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
215*4882a593Smuzhiyun			};
216*4882a593Smuzhiyun			conf_ate {
217*4882a593Smuzhiyun				nvidia,pins = "ate", "csus", "dap3", "gmd",
218*4882a593Smuzhiyun					"gpv", "owc", "spia", "spib", "spic",
219*4882a593Smuzhiyun					"spid", "spie", "spig";
220*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
221*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
222*4882a593Smuzhiyun			};
223*4882a593Smuzhiyun			conf_ck32 {
224*4882a593Smuzhiyun				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
225*4882a593Smuzhiyun					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
226*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227*4882a593Smuzhiyun			};
228*4882a593Smuzhiyun			conf_crtp {
229*4882a593Smuzhiyun				nvidia,pins = "crtp", "gmb", "slxa", "spih";
230*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
231*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
232*4882a593Smuzhiyun			};
233*4882a593Smuzhiyun			conf_dta {
234*4882a593Smuzhiyun				nvidia,pins = "dta", "dtb", "dtc", "dtd";
235*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
236*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun			conf_dte {
239*4882a593Smuzhiyun				nvidia,pins = "dte", "spif";
240*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
241*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
242*4882a593Smuzhiyun			};
243*4882a593Smuzhiyun			conf_hdint {
244*4882a593Smuzhiyun				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
245*4882a593Smuzhiyun					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
246*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
247*4882a593Smuzhiyun			};
248*4882a593Smuzhiyun			conf_kbca {
249*4882a593Smuzhiyun				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
250*4882a593Smuzhiyun					"kbce", "kbcf", "sdio1", "uaa", "uab";
251*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
252*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
253*4882a593Smuzhiyun			};
254*4882a593Smuzhiyun			conf_lc {
255*4882a593Smuzhiyun				nvidia,pins = "lc", "ls";
256*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
257*4882a593Smuzhiyun			};
258*4882a593Smuzhiyun			conf_ld0 {
259*4882a593Smuzhiyun				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
260*4882a593Smuzhiyun					"ld5", "ld6", "ld7", "ld8", "ld9",
261*4882a593Smuzhiyun					"ld10", "ld11", "ld12", "ld13", "ld14",
262*4882a593Smuzhiyun					"ld15", "ld16", "ld17", "ldi", "lhp0",
263*4882a593Smuzhiyun					"lhp1", "lhp2", "lhs", "lm0", "lpp",
264*4882a593Smuzhiyun					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
265*4882a593Smuzhiyun					"lvp1", "lvs", "pmc", "sdb";
266*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
267*4882a593Smuzhiyun			};
268*4882a593Smuzhiyun			conf_ld17_0 {
269*4882a593Smuzhiyun				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
270*4882a593Smuzhiyun					"ld23_22";
271*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
272*4882a593Smuzhiyun			};
273*4882a593Smuzhiyun			drive_sdio1 {
274*4882a593Smuzhiyun				nvidia,pins = "drive_sdio1";
275*4882a593Smuzhiyun				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
276*4882a593Smuzhiyun				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
277*4882a593Smuzhiyun				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
278*4882a593Smuzhiyun				nvidia,pull-down-strength = <31>;
279*4882a593Smuzhiyun				nvidia,pull-up-strength = <31>;
280*4882a593Smuzhiyun				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
281*4882a593Smuzhiyun				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
282*4882a593Smuzhiyun			};
283*4882a593Smuzhiyun		};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun		state_i2cmux_ddc: pinmux_i2cmux_ddc {
286*4882a593Smuzhiyun			ddc {
287*4882a593Smuzhiyun				nvidia,pins = "ddc";
288*4882a593Smuzhiyun				nvidia,function = "i2c2";
289*4882a593Smuzhiyun			};
290*4882a593Smuzhiyun			pta {
291*4882a593Smuzhiyun				nvidia,pins = "pta";
292*4882a593Smuzhiyun				nvidia,function = "rsvd4";
293*4882a593Smuzhiyun			};
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun		state_i2cmux_pta: pinmux_i2cmux_pta {
297*4882a593Smuzhiyun			ddc {
298*4882a593Smuzhiyun				nvidia,pins = "ddc";
299*4882a593Smuzhiyun				nvidia,function = "rsvd4";
300*4882a593Smuzhiyun			};
301*4882a593Smuzhiyun			pta {
302*4882a593Smuzhiyun				nvidia,pins = "pta";
303*4882a593Smuzhiyun				nvidia,function = "i2c2";
304*4882a593Smuzhiyun			};
305*4882a593Smuzhiyun		};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun		state_i2cmux_idle: pinmux_i2cmux_idle {
308*4882a593Smuzhiyun			ddc {
309*4882a593Smuzhiyun				nvidia,pins = "ddc";
310*4882a593Smuzhiyun				nvidia,function = "rsvd4";
311*4882a593Smuzhiyun			};
312*4882a593Smuzhiyun			pta {
313*4882a593Smuzhiyun				nvidia,pins = "pta";
314*4882a593Smuzhiyun				nvidia,function = "rsvd4";
315*4882a593Smuzhiyun			};
316*4882a593Smuzhiyun		};
317*4882a593Smuzhiyun	};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun	i2s@70002800 {
320*4882a593Smuzhiyun		status = "okay";
321*4882a593Smuzhiyun	};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun	serial@70006300 {
324*4882a593Smuzhiyun		status = "okay";
325*4882a593Smuzhiyun	};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun	pwm: pwm@7000a000 {
328*4882a593Smuzhiyun		status = "okay";
329*4882a593Smuzhiyun	};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun	i2c@7000c000 {
332*4882a593Smuzhiyun		status = "okay";
333*4882a593Smuzhiyun		clock-frequency = <400000>;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun		wm8903: wm8903@1a {
336*4882a593Smuzhiyun			compatible = "wlf,wm8903";
337*4882a593Smuzhiyun			reg = <0x1a>;
338*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
339*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun			gpio-controller;
342*4882a593Smuzhiyun			#gpio-cells = <2>;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun			micdet-cfg = <0>;
345*4882a593Smuzhiyun			micdet-delay = <100>;
346*4882a593Smuzhiyun			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
347*4882a593Smuzhiyun		};
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun		/* ALS and proximity sensor */
350*4882a593Smuzhiyun		isl29018@44 {
351*4882a593Smuzhiyun			compatible = "isil,isl29018";
352*4882a593Smuzhiyun			reg = <0x44>;
353*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
354*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
355*4882a593Smuzhiyun		};
356*4882a593Smuzhiyun	};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun	i2c@7000c400 {
359*4882a593Smuzhiyun		status = "okay";
360*4882a593Smuzhiyun		clock-frequency = <100000>;
361*4882a593Smuzhiyun	};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun	i2cmux {
364*4882a593Smuzhiyun		compatible = "i2c-mux-pinctrl";
365*4882a593Smuzhiyun		#address-cells = <1>;
366*4882a593Smuzhiyun		#size-cells = <0>;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun		i2c-parent = <&{/i2c@7000c400}>;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun		pinctrl-names = "ddc", "pta", "idle";
371*4882a593Smuzhiyun		pinctrl-0 = <&state_i2cmux_ddc>;
372*4882a593Smuzhiyun		pinctrl-1 = <&state_i2cmux_pta>;
373*4882a593Smuzhiyun		pinctrl-2 = <&state_i2cmux_idle>;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun		hdmi_ddc: i2c@0 {
376*4882a593Smuzhiyun			reg = <0>;
377*4882a593Smuzhiyun			#address-cells = <1>;
378*4882a593Smuzhiyun			#size-cells = <0>;
379*4882a593Smuzhiyun		};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun		lvds_ddc: i2c@1 {
382*4882a593Smuzhiyun			reg = <1>;
383*4882a593Smuzhiyun			#address-cells = <1>;
384*4882a593Smuzhiyun			#size-cells = <0>;
385*4882a593Smuzhiyun		};
386*4882a593Smuzhiyun	};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun	i2c@7000c500 {
389*4882a593Smuzhiyun		status = "okay";
390*4882a593Smuzhiyun		clock-frequency = <400000>;
391*4882a593Smuzhiyun	};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun	i2c@7000d000 {
394*4882a593Smuzhiyun		status = "okay";
395*4882a593Smuzhiyun		clock-frequency = <400000>;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun		pmic: tps6586x@34 {
398*4882a593Smuzhiyun			compatible = "ti,tps6586x";
399*4882a593Smuzhiyun			reg = <0x34>;
400*4882a593Smuzhiyun			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun			ti,system-power-controller;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun			#gpio-cells = <2>;
405*4882a593Smuzhiyun			gpio-controller;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun			sys-supply = <&vdd_5v0_reg>;
408*4882a593Smuzhiyun			vin-sm0-supply = <&sys_reg>;
409*4882a593Smuzhiyun			vin-sm1-supply = <&sys_reg>;
410*4882a593Smuzhiyun			vin-sm2-supply = <&sys_reg>;
411*4882a593Smuzhiyun			vinldo01-supply = <&sm2_reg>;
412*4882a593Smuzhiyun			vinldo23-supply = <&sm2_reg>;
413*4882a593Smuzhiyun			vinldo4-supply = <&sm2_reg>;
414*4882a593Smuzhiyun			vinldo678-supply = <&sm2_reg>;
415*4882a593Smuzhiyun			vinldo9-supply = <&sm2_reg>;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun			regulators {
418*4882a593Smuzhiyun				sys_reg: sys {
419*4882a593Smuzhiyun					regulator-name = "vdd_sys";
420*4882a593Smuzhiyun					regulator-always-on;
421*4882a593Smuzhiyun				};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun				sm0 {
424*4882a593Smuzhiyun					regulator-name = "vdd_sm0,vdd_core";
425*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
426*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
427*4882a593Smuzhiyun					regulator-always-on;
428*4882a593Smuzhiyun				};
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun				sm1 {
431*4882a593Smuzhiyun					regulator-name = "vdd_sm1,vdd_cpu";
432*4882a593Smuzhiyun					regulator-min-microvolt = <1000000>;
433*4882a593Smuzhiyun					regulator-max-microvolt = <1000000>;
434*4882a593Smuzhiyun					regulator-always-on;
435*4882a593Smuzhiyun				};
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun				sm2_reg: sm2 {
438*4882a593Smuzhiyun					regulator-name = "vdd_sm2,vin_ldo*";
439*4882a593Smuzhiyun					regulator-min-microvolt = <3700000>;
440*4882a593Smuzhiyun					regulator-max-microvolt = <3700000>;
441*4882a593Smuzhiyun					regulator-always-on;
442*4882a593Smuzhiyun				};
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun				/* LDO0 is not connected to anything */
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun				ldo1 {
447*4882a593Smuzhiyun					regulator-name = "vdd_ldo1,avdd_pll*";
448*4882a593Smuzhiyun					regulator-min-microvolt = <1100000>;
449*4882a593Smuzhiyun					regulator-max-microvolt = <1100000>;
450*4882a593Smuzhiyun					regulator-always-on;
451*4882a593Smuzhiyun				};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun				ldo2 {
454*4882a593Smuzhiyun					regulator-name = "vdd_ldo2,vdd_rtc";
455*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
456*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
457*4882a593Smuzhiyun				};
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun				ldo3 {
460*4882a593Smuzhiyun					regulator-name = "vdd_ldo3,avdd_usb*";
461*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
462*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
463*4882a593Smuzhiyun					regulator-always-on;
464*4882a593Smuzhiyun				};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun				ldo4 {
467*4882a593Smuzhiyun					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
468*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
469*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
470*4882a593Smuzhiyun					regulator-always-on;
471*4882a593Smuzhiyun				};
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun				ldo5 {
474*4882a593Smuzhiyun					regulator-name = "vdd_ldo5,vcore_mmc";
475*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
476*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
477*4882a593Smuzhiyun					regulator-always-on;
478*4882a593Smuzhiyun				};
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun				ldo6 {
481*4882a593Smuzhiyun					regulator-name = "vdd_ldo6,avdd_vdac";
482*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
483*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
484*4882a593Smuzhiyun				};
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun				hdmi_vdd_reg: ldo7 {
487*4882a593Smuzhiyun					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
488*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
489*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
490*4882a593Smuzhiyun				};
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun				hdmi_pll_reg: ldo8 {
493*4882a593Smuzhiyun					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
494*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
495*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
496*4882a593Smuzhiyun				};
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun				ldo9 {
499*4882a593Smuzhiyun					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
500*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
501*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
502*4882a593Smuzhiyun					regulator-always-on;
503*4882a593Smuzhiyun				};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun				ldo_rtc {
506*4882a593Smuzhiyun					regulator-name = "vdd_rtc_out,vdd_cell";
507*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
508*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
509*4882a593Smuzhiyun					regulator-always-on;
510*4882a593Smuzhiyun				};
511*4882a593Smuzhiyun			};
512*4882a593Smuzhiyun		};
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun		temperature-sensor@4c {
515*4882a593Smuzhiyun			compatible = "onnn,nct1008";
516*4882a593Smuzhiyun			reg = <0x4c>;
517*4882a593Smuzhiyun		};
518*4882a593Smuzhiyun	};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun	pmc@7000e400 {
521*4882a593Smuzhiyun		nvidia,invert-interrupt;
522*4882a593Smuzhiyun		nvidia,suspend-mode = <1>;
523*4882a593Smuzhiyun		nvidia,cpu-pwr-good-time = <2000>;
524*4882a593Smuzhiyun		nvidia,cpu-pwr-off-time = <100>;
525*4882a593Smuzhiyun		nvidia,core-pwr-good-time = <3845 3845>;
526*4882a593Smuzhiyun		nvidia,core-pwr-off-time = <458>;
527*4882a593Smuzhiyun		nvidia,sys-clock-req-active-high;
528*4882a593Smuzhiyun	};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun	usb@c5000000 {
531*4882a593Smuzhiyun		status = "okay";
532*4882a593Smuzhiyun	};
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun	usb-phy@c5000000 {
535*4882a593Smuzhiyun		status = "okay";
536*4882a593Smuzhiyun	};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun	usb@c5004000 {
539*4882a593Smuzhiyun		status = "okay";
540*4882a593Smuzhiyun		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
541*4882a593Smuzhiyun			GPIO_ACTIVE_LOW>;
542*4882a593Smuzhiyun	};
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun	usb-phy@c5004000 {
545*4882a593Smuzhiyun		status = "okay";
546*4882a593Smuzhiyun		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
547*4882a593Smuzhiyun			GPIO_ACTIVE_LOW>;
548*4882a593Smuzhiyun	};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun	usb@c5008000 {
551*4882a593Smuzhiyun		status = "okay";
552*4882a593Smuzhiyun	};
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun	usb-phy@c5008000 {
555*4882a593Smuzhiyun		status = "okay";
556*4882a593Smuzhiyun	};
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun	mmc@c8000000 {
559*4882a593Smuzhiyun		status = "okay";
560*4882a593Smuzhiyun		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
561*4882a593Smuzhiyun		bus-width = <4>;
562*4882a593Smuzhiyun		keep-power-in-suspend;
563*4882a593Smuzhiyun	};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun	mmc@c8000400 {
566*4882a593Smuzhiyun		status = "okay";
567*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
568*4882a593Smuzhiyun		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
569*4882a593Smuzhiyun		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
570*4882a593Smuzhiyun		bus-width = <4>;
571*4882a593Smuzhiyun	};
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun	mmc@c8000600 {
574*4882a593Smuzhiyun		status = "okay";
575*4882a593Smuzhiyun		bus-width = <8>;
576*4882a593Smuzhiyun		non-removable;
577*4882a593Smuzhiyun	};
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun	backlight: backlight {
580*4882a593Smuzhiyun		compatible = "pwm-backlight";
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
583*4882a593Smuzhiyun		power-supply = <&vdd_bl_reg>;
584*4882a593Smuzhiyun		pwms = <&pwm 2 5000000>;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
587*4882a593Smuzhiyun		default-brightness-level = <6>;
588*4882a593Smuzhiyun	};
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun	clk32k_in: clock@0 {
591*4882a593Smuzhiyun		compatible = "fixed-clock";
592*4882a593Smuzhiyun		clock-frequency = <32768>;
593*4882a593Smuzhiyun		#clock-cells = <0>;
594*4882a593Smuzhiyun	};
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun	cpus {
597*4882a593Smuzhiyun		cpu0: cpu@0 {
598*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table>;
599*4882a593Smuzhiyun		};
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun		cpu@1 {
602*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table>;
603*4882a593Smuzhiyun		};
604*4882a593Smuzhiyun	};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun	gpio-keys {
607*4882a593Smuzhiyun		compatible = "gpio-keys";
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun		power {
610*4882a593Smuzhiyun			label = "Power";
611*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
612*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
613*4882a593Smuzhiyun			wakeup-source;
614*4882a593Smuzhiyun		};
615*4882a593Smuzhiyun	};
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun	panel: panel {
618*4882a593Smuzhiyun		compatible = "chunghwa,claa101wa01a";
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun		power-supply = <&vdd_pnl_reg>;
621*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun		backlight = <&backlight>;
624*4882a593Smuzhiyun		ddc-i2c-bus = <&lvds_ddc>;
625*4882a593Smuzhiyun	};
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun	vdd_5v0_reg: regulator@0 {
628*4882a593Smuzhiyun		compatible = "regulator-fixed";
629*4882a593Smuzhiyun		regulator-name = "vdd_5v0";
630*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
631*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
632*4882a593Smuzhiyun		regulator-always-on;
633*4882a593Smuzhiyun	};
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun	regulator@1 {
636*4882a593Smuzhiyun		compatible = "regulator-fixed";
637*4882a593Smuzhiyun		regulator-name = "vdd_1v5";
638*4882a593Smuzhiyun		regulator-min-microvolt = <1500000>;
639*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
640*4882a593Smuzhiyun		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
641*4882a593Smuzhiyun	};
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun	regulator@2 {
644*4882a593Smuzhiyun		compatible = "regulator-fixed";
645*4882a593Smuzhiyun		regulator-name = "vdd_1v2";
646*4882a593Smuzhiyun		regulator-min-microvolt = <1200000>;
647*4882a593Smuzhiyun		regulator-max-microvolt = <1200000>;
648*4882a593Smuzhiyun		gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
649*4882a593Smuzhiyun		enable-active-high;
650*4882a593Smuzhiyun	};
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun	vdd_pnl_reg: regulator@3 {
653*4882a593Smuzhiyun		compatible = "regulator-fixed";
654*4882a593Smuzhiyun		regulator-name = "vdd_pnl";
655*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
656*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
657*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
658*4882a593Smuzhiyun		enable-active-high;
659*4882a593Smuzhiyun	};
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun	vdd_bl_reg: regulator@4 {
662*4882a593Smuzhiyun		compatible = "regulator-fixed";
663*4882a593Smuzhiyun		regulator-name = "vdd_bl";
664*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
665*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
666*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
667*4882a593Smuzhiyun		enable-active-high;
668*4882a593Smuzhiyun	};
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun	sound {
671*4882a593Smuzhiyun		compatible = "nvidia,tegra-audio-wm8903-ventana",
672*4882a593Smuzhiyun			     "nvidia,tegra-audio-wm8903";
673*4882a593Smuzhiyun		nvidia,model = "NVIDIA Tegra Ventana";
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun		nvidia,audio-routing =
676*4882a593Smuzhiyun			"Headphone Jack", "HPOUTR",
677*4882a593Smuzhiyun			"Headphone Jack", "HPOUTL",
678*4882a593Smuzhiyun			"Int Spk", "ROP",
679*4882a593Smuzhiyun			"Int Spk", "RON",
680*4882a593Smuzhiyun			"Int Spk", "LOP",
681*4882a593Smuzhiyun			"Int Spk", "LON",
682*4882a593Smuzhiyun			"Mic Jack", "MICBIAS",
683*4882a593Smuzhiyun			"IN1L", "Mic Jack";
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun		nvidia,i2s-controller = <&tegra_i2s1>;
686*4882a593Smuzhiyun		nvidia,audio-codec = <&wm8903>;
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
689*4882a593Smuzhiyun		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
690*4882a593Smuzhiyun		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
691*4882a593Smuzhiyun			GPIO_ACTIVE_HIGH>;
692*4882a593Smuzhiyun		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
693*4882a593Smuzhiyun			GPIO_ACTIVE_HIGH>;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
696*4882a593Smuzhiyun			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
697*4882a593Smuzhiyun			 <&tegra_car TEGRA20_CLK_CDEV1>;
698*4882a593Smuzhiyun		clock-names = "pll_a", "pll_a_out0", "mclk";
699*4882a593Smuzhiyun	};
700*4882a593Smuzhiyun};
701