xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun#include <dt-bindings/mfd/max77620.h>
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun#include "tegra210.dtsi"
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/ {
7*4882a593Smuzhiyun	model = "NVIDIA Jetson TX1";
8*4882a593Smuzhiyun	compatible = "nvidia,p2180", "nvidia,tegra210";
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	aliases {
11*4882a593Smuzhiyun		rtc0 = "/i2c@7000d000/pmic@3c";
12*4882a593Smuzhiyun		rtc1 = "/rtc@7000e000";
13*4882a593Smuzhiyun		serial0 = &uarta;
14*4882a593Smuzhiyun	};
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	chosen {
17*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	memory@80000000 {
21*4882a593Smuzhiyun		device_type = "memory";
22*4882a593Smuzhiyun		reg = <0x0 0x80000000 0x1 0x0>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	gpu@57000000 {
26*4882a593Smuzhiyun		vdd-supply = <&vdd_gpu>;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	/* debug port */
30*4882a593Smuzhiyun	serial@70006000 {
31*4882a593Smuzhiyun		status = "okay";
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	i2c@7000d000 {
35*4882a593Smuzhiyun		status = "okay";
36*4882a593Smuzhiyun		clock-frequency = <400000>;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		pmic: pmic@3c {
39*4882a593Smuzhiyun			compatible = "maxim,max77620";
40*4882a593Smuzhiyun			reg = <0x3c>;
41*4882a593Smuzhiyun			interrupt-parent = <&tegra_pmc>;
42*4882a593Smuzhiyun			interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun			#interrupt-cells = <2>;
45*4882a593Smuzhiyun			interrupt-controller;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun			#gpio-cells = <2>;
48*4882a593Smuzhiyun			gpio-controller;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun			pinctrl-names = "default";
51*4882a593Smuzhiyun			pinctrl-0 = <&max77620_default>;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun			max77620_default: pinmux {
54*4882a593Smuzhiyun				gpio0 {
55*4882a593Smuzhiyun					pins = "gpio0";
56*4882a593Smuzhiyun					function = "gpio";
57*4882a593Smuzhiyun				};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun				gpio1 {
60*4882a593Smuzhiyun					pins = "gpio1";
61*4882a593Smuzhiyun					function = "fps-out";
62*4882a593Smuzhiyun					drive-push-pull = <1>;
63*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
64*4882a593Smuzhiyun					maxim,active-fps-power-up-slot = <7>;
65*4882a593Smuzhiyun					maxim,active-fps-power-down-slot = <0>;
66*4882a593Smuzhiyun				};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun				gpio2_3 {
69*4882a593Smuzhiyun					pins = "gpio2", "gpio3";
70*4882a593Smuzhiyun					function = "fps-out";
71*4882a593Smuzhiyun					drive-open-drain = <1>;
72*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
73*4882a593Smuzhiyun				};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun				gpio4 {
76*4882a593Smuzhiyun					pins = "gpio4";
77*4882a593Smuzhiyun					function = "32k-out1";
78*4882a593Smuzhiyun				};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun				gpio5_6_7 {
81*4882a593Smuzhiyun					pins = "gpio5", "gpio6", "gpio7";
82*4882a593Smuzhiyun					function = "gpio";
83*4882a593Smuzhiyun					drive-push-pull = <1>;
84*4882a593Smuzhiyun				};
85*4882a593Smuzhiyun			};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun			fps {
88*4882a593Smuzhiyun				fps0 {
89*4882a593Smuzhiyun					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
90*4882a593Smuzhiyun					maxim,suspend-fps-time-period-us = <1280>;
91*4882a593Smuzhiyun				};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun				fps1 {
94*4882a593Smuzhiyun					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
95*4882a593Smuzhiyun					maxim,suspend-fps-time-period-us = <1280>;
96*4882a593Smuzhiyun				};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun				fps2 {
99*4882a593Smuzhiyun					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
100*4882a593Smuzhiyun				};
101*4882a593Smuzhiyun			};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun			regulators {
104*4882a593Smuzhiyun				in-ldo0-1-supply = <&vdd_pre>;
105*4882a593Smuzhiyun				in-ldo7-8-supply = <&vdd_pre>;
106*4882a593Smuzhiyun				in-sd3-supply = <&vdd_5v0_sys>;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun				vdd_soc: sd0 {
109*4882a593Smuzhiyun					regulator-name = "VDD_SOC";
110*4882a593Smuzhiyun					regulator-min-microvolt = <600000>;
111*4882a593Smuzhiyun					regulator-max-microvolt = <1400000>;
112*4882a593Smuzhiyun					regulator-always-on;
113*4882a593Smuzhiyun					regulator-boot-on;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun					regulator-enable-ramp-delay = <146>;
116*4882a593Smuzhiyun					regulator-ramp-delay = <27500>;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
119*4882a593Smuzhiyun				};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun				vdd_ddr: sd1 {
122*4882a593Smuzhiyun					regulator-name = "VDD_DDR_1V1_PMIC";
123*4882a593Smuzhiyun					regulator-always-on;
124*4882a593Smuzhiyun					regulator-boot-on;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun					regulator-enable-ramp-delay = <130>;
127*4882a593Smuzhiyun					regulator-ramp-delay = <27500>;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
130*4882a593Smuzhiyun				};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun				vdd_pre: sd2 {
133*4882a593Smuzhiyun					regulator-name = "VDD_PRE_REG_1V35";
134*4882a593Smuzhiyun					regulator-min-microvolt = <1350000>;
135*4882a593Smuzhiyun					regulator-max-microvolt = <1350000>;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun					regulator-enable-ramp-delay = <176>;
138*4882a593Smuzhiyun					regulator-ramp-delay = <27500>;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
141*4882a593Smuzhiyun				};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun				vdd_1v8: sd3 {
144*4882a593Smuzhiyun					regulator-name = "VDD_1V8";
145*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
146*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
147*4882a593Smuzhiyun					regulator-always-on;
148*4882a593Smuzhiyun					regulator-boot-on;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun					regulator-enable-ramp-delay = <242>;
151*4882a593Smuzhiyun					regulator-ramp-delay = <27500>;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
154*4882a593Smuzhiyun				};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun				vdd_sys_1v2: ldo0 {
157*4882a593Smuzhiyun					regulator-name = "AVDD_SYS_1V2";
158*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
159*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
160*4882a593Smuzhiyun					regulator-always-on;
161*4882a593Smuzhiyun					regulator-boot-on;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun					regulator-enable-ramp-delay = <26>;
164*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
167*4882a593Smuzhiyun				};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun				vdd_pex_1v05: ldo1 {
170*4882a593Smuzhiyun					regulator-name = "VDD_PEX_1V05";
171*4882a593Smuzhiyun					regulator-min-microvolt = <1050000>;
172*4882a593Smuzhiyun					regulator-max-microvolt = <1050000>;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun					regulator-enable-ramp-delay = <22>;
175*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
178*4882a593Smuzhiyun				};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun				vddio_sdmmc: ldo2 {
181*4882a593Smuzhiyun					regulator-name = "VDDIO_SDMMC";
182*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
183*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
184*4882a593Smuzhiyun					regulator-always-on;
185*4882a593Smuzhiyun					regulator-boot-on;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun					regulator-enable-ramp-delay = <62>;
188*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
191*4882a593Smuzhiyun				};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun				vdd_cam_hv: ldo3 {
194*4882a593Smuzhiyun					regulator-name = "VDD_CAM_HV";
195*4882a593Smuzhiyun					regulator-min-microvolt = <2800000>;
196*4882a593Smuzhiyun					regulator-max-microvolt = <2800000>;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun					regulator-enable-ramp-delay = <50>;
199*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
202*4882a593Smuzhiyun				};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun				vdd_rtc: ldo4 {
205*4882a593Smuzhiyun					regulator-name = "VDD_RTC";
206*4882a593Smuzhiyun					regulator-min-microvolt = <850000>;
207*4882a593Smuzhiyun					regulator-max-microvolt = <850000>;
208*4882a593Smuzhiyun					regulator-always-on;
209*4882a593Smuzhiyun					regulator-boot-on;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun					regulator-enable-ramp-delay = <22>;
212*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
215*4882a593Smuzhiyun				};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun				vdd_ts_hv: ldo5 {
218*4882a593Smuzhiyun					regulator-name = "VDD_TS_HV";
219*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
220*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun					regulator-enable-ramp-delay = <62>;
223*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
226*4882a593Smuzhiyun				};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun				vdd_ts: ldo6 {
229*4882a593Smuzhiyun					regulator-name = "VDD_TS_1V8";
230*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
231*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun					regulator-enable-ramp-delay = <36>;
234*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
237*4882a593Smuzhiyun					maxim,active-fps-power-up-slot = <7>;
238*4882a593Smuzhiyun					maxim,active-fps-power-down-slot = <0>;
239*4882a593Smuzhiyun				};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun				avdd_1v05_pll: ldo7 {
242*4882a593Smuzhiyun					regulator-name = "AVDD_1V05_PLL";
243*4882a593Smuzhiyun					regulator-min-microvolt = <1050000>;
244*4882a593Smuzhiyun					regulator-max-microvolt = <1050000>;
245*4882a593Smuzhiyun					regulator-always-on;
246*4882a593Smuzhiyun					regulator-boot-on;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun					regulator-enable-ramp-delay = <24>;
249*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
252*4882a593Smuzhiyun				};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun				avdd_1v05: ldo8 {
255*4882a593Smuzhiyun					regulator-name = "AVDD_SATA_HDMI_DP_1V05";
256*4882a593Smuzhiyun					regulator-min-microvolt = <1050000>;
257*4882a593Smuzhiyun					regulator-max-microvolt = <1050000>;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun					regulator-enable-ramp-delay = <22>;
260*4882a593Smuzhiyun					regulator-ramp-delay = <100000>;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
263*4882a593Smuzhiyun				};
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun	};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun	i2c@7000c500 {
269*4882a593Smuzhiyun		status = "okay";
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun		/* module ID EEPROM */
272*4882a593Smuzhiyun		eeprom@50 {
273*4882a593Smuzhiyun			compatible = "atmel,24c02";
274*4882a593Smuzhiyun			reg = <0x50>;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun			label = "module";
277*4882a593Smuzhiyun			vcc-supply = <&vdd_1v8>;
278*4882a593Smuzhiyun			address-width = <8>;
279*4882a593Smuzhiyun			pagesize = <8>;
280*4882a593Smuzhiyun			size = <256>;
281*4882a593Smuzhiyun			read-only;
282*4882a593Smuzhiyun		};
283*4882a593Smuzhiyun	};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun	pmc@7000e400 {
286*4882a593Smuzhiyun		nvidia,invert-interrupt;
287*4882a593Smuzhiyun		nvidia,suspend-mode = <0>;
288*4882a593Smuzhiyun		nvidia,cpu-pwr-good-time = <0>;
289*4882a593Smuzhiyun		nvidia,cpu-pwr-off-time = <0>;
290*4882a593Smuzhiyun		nvidia,core-pwr-good-time = <4587 3876>;
291*4882a593Smuzhiyun		nvidia,core-pwr-off-time = <39065>;
292*4882a593Smuzhiyun		nvidia,core-power-req-active-high;
293*4882a593Smuzhiyun		nvidia,sys-clock-req-active-high;
294*4882a593Smuzhiyun	};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	/* eMMC */
297*4882a593Smuzhiyun	mmc@700b0600 {
298*4882a593Smuzhiyun		status = "okay";
299*4882a593Smuzhiyun		bus-width = <8>;
300*4882a593Smuzhiyun		non-removable;
301*4882a593Smuzhiyun		vqmmc-supply = <&vdd_1v8>;
302*4882a593Smuzhiyun	};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun	clk32k_in: clock@0 {
305*4882a593Smuzhiyun		compatible = "fixed-clock";
306*4882a593Smuzhiyun		clock-frequency = <32768>;
307*4882a593Smuzhiyun		#clock-cells = <0>;
308*4882a593Smuzhiyun	};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun	cpus {
311*4882a593Smuzhiyun		cpu@0 {
312*4882a593Smuzhiyun			enable-method = "psci";
313*4882a593Smuzhiyun		};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun		cpu@1 {
316*4882a593Smuzhiyun			enable-method = "psci";
317*4882a593Smuzhiyun		};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun		cpu@2 {
320*4882a593Smuzhiyun			enable-method = "psci";
321*4882a593Smuzhiyun		};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun		cpu@3 {
324*4882a593Smuzhiyun			enable-method = "psci";
325*4882a593Smuzhiyun		};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun		idle-states {
328*4882a593Smuzhiyun			cpu-sleep {
329*4882a593Smuzhiyun				status = "okay";
330*4882a593Smuzhiyun			};
331*4882a593Smuzhiyun		};
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	psci {
335*4882a593Smuzhiyun		compatible = "arm,psci-0.2";
336*4882a593Smuzhiyun		method = "smc";
337*4882a593Smuzhiyun	};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun	vdd_gpu: regulator@100 {
340*4882a593Smuzhiyun		compatible = "pwm-regulator";
341*4882a593Smuzhiyun		pwms = <&pwm 1 8000>;
342*4882a593Smuzhiyun		regulator-name = "VDD_GPU";
343*4882a593Smuzhiyun		regulator-min-microvolt = <710000>;
344*4882a593Smuzhiyun		regulator-max-microvolt = <1320000>;
345*4882a593Smuzhiyun		enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
346*4882a593Smuzhiyun		regulator-ramp-delay = <80>;
347*4882a593Smuzhiyun		regulator-enable-ramp-delay = <2000>;
348*4882a593Smuzhiyun		regulator-settling-time-us = <160>;
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun};
351