xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/tegra30-cardhu.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
3*4882a593Smuzhiyun#include "tegra30.dtsi"
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/**
6*4882a593Smuzhiyun * This file contains common DT entry for all fab version of Cardhu.
7*4882a593Smuzhiyun * There is multiple fab version of Cardhu starting from A01 to A07.
8*4882a593Smuzhiyun * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
9*4882a593Smuzhiyun * A02 will have different sets of GPIOs for fixed regulator compare to
10*4882a593Smuzhiyun * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
11*4882a593Smuzhiyun * compatible with fab version A04. Based on Cardhu fab version, the
12*4882a593Smuzhiyun * related dts file need to be chosen like for Cardhu fab version A02,
13*4882a593Smuzhiyun * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
14*4882a593Smuzhiyun * tegra30-cardhu-a04.dts.
15*4882a593Smuzhiyun * The identification of board is done in two ways, by looking the sticker
16*4882a593Smuzhiyun * on PCB and by reading board id eeprom.
17*4882a593Smuzhiyun * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
18*4882a593Smuzhiyun * number is the fab version like here it is 002 and hence fab version A02.
19*4882a593Smuzhiyun * The (downstream internal) U-Boot of Cardhu display the board-id as
20*4882a593Smuzhiyun * follows:
21*4882a593Smuzhiyun * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
22*4882a593Smuzhiyun * In this Fab version is 02 i.e. A02.
23*4882a593Smuzhiyun * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
24*4882a593Smuzhiyun * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
25*4882a593Smuzhiyun * wide.
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun/ {
29*4882a593Smuzhiyun	model = "NVIDIA Tegra30 Cardhu evaluation board";
30*4882a593Smuzhiyun	compatible = "nvidia,cardhu", "nvidia,tegra30";
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	aliases {
33*4882a593Smuzhiyun		rtc0 = "/i2c@7000d000/tps65911@2d";
34*4882a593Smuzhiyun		rtc1 = "/rtc@7000e000";
35*4882a593Smuzhiyun		serial0 = &uarta;
36*4882a593Smuzhiyun		serial1 = &uartc;
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	chosen {
40*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	memory@80000000 {
44*4882a593Smuzhiyun		reg = <0x80000000 0x40000000>;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	pcie@3000 {
48*4882a593Smuzhiyun		status = "okay";
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
51*4882a593Smuzhiyun		avdd-pexb-supply = <&ldo1_reg>;
52*4882a593Smuzhiyun		vdd-pexb-supply = <&ldo1_reg>;
53*4882a593Smuzhiyun		avdd-pex-pll-supply = <&ldo1_reg>;
54*4882a593Smuzhiyun		hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
55*4882a593Smuzhiyun		vddio-pex-ctl-supply = <&sys_3v3_reg>;
56*4882a593Smuzhiyun		avdd-plle-supply = <&ldo2_reg>;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun		pci@1,0 {
59*4882a593Smuzhiyun			nvidia,num-lanes = <4>;
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		pci@2,0 {
63*4882a593Smuzhiyun			nvidia,num-lanes = <1>;
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		pci@3,0 {
67*4882a593Smuzhiyun			status = "okay";
68*4882a593Smuzhiyun			nvidia,num-lanes = <1>;
69*4882a593Smuzhiyun		};
70*4882a593Smuzhiyun	};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun	host1x@50000000 {
73*4882a593Smuzhiyun		dc@54200000 {
74*4882a593Smuzhiyun			rgb {
75*4882a593Smuzhiyun				status = "okay";
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun				nvidia,panel = <&panel>;
78*4882a593Smuzhiyun			};
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	pinmux@70000868 {
83*4882a593Smuzhiyun		pinctrl-names = "default";
84*4882a593Smuzhiyun		pinctrl-0 = <&state_default>;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun		state_default: pinmux {
87*4882a593Smuzhiyun			sdmmc1_clk_pz0 {
88*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_clk_pz0";
89*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
90*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
91*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun			sdmmc1_cmd_pz1 {
94*4882a593Smuzhiyun				nvidia,pins =	"sdmmc1_cmd_pz1",
95*4882a593Smuzhiyun						"sdmmc1_dat0_py7",
96*4882a593Smuzhiyun						"sdmmc1_dat1_py6",
97*4882a593Smuzhiyun						"sdmmc1_dat2_py5",
98*4882a593Smuzhiyun						"sdmmc1_dat3_py4";
99*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
100*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
101*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
102*4882a593Smuzhiyun			};
103*4882a593Smuzhiyun			sdmmc3_clk_pa6 {
104*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_clk_pa6";
105*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
106*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
107*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
108*4882a593Smuzhiyun			};
109*4882a593Smuzhiyun			sdmmc3_cmd_pa7 {
110*4882a593Smuzhiyun				nvidia,pins =	"sdmmc3_cmd_pa7",
111*4882a593Smuzhiyun						"sdmmc3_dat0_pb7",
112*4882a593Smuzhiyun						"sdmmc3_dat1_pb6",
113*4882a593Smuzhiyun						"sdmmc3_dat2_pb5",
114*4882a593Smuzhiyun						"sdmmc3_dat3_pb4";
115*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
116*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
117*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun			sdmmc4_clk_pcc4 {
120*4882a593Smuzhiyun				nvidia,pins =	"sdmmc4_clk_pcc4",
121*4882a593Smuzhiyun						"sdmmc4_rst_n_pcc3";
122*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
123*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
124*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
125*4882a593Smuzhiyun			};
126*4882a593Smuzhiyun			sdmmc4_dat0_paa0 {
127*4882a593Smuzhiyun				nvidia,pins =	"sdmmc4_dat0_paa0",
128*4882a593Smuzhiyun						"sdmmc4_dat1_paa1",
129*4882a593Smuzhiyun						"sdmmc4_dat2_paa2",
130*4882a593Smuzhiyun						"sdmmc4_dat3_paa3",
131*4882a593Smuzhiyun						"sdmmc4_dat4_paa4",
132*4882a593Smuzhiyun						"sdmmc4_dat5_paa5",
133*4882a593Smuzhiyun						"sdmmc4_dat6_paa6",
134*4882a593Smuzhiyun						"sdmmc4_dat7_paa7";
135*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
136*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
137*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun			dap2_fs_pa2 {
140*4882a593Smuzhiyun				nvidia,pins =	"dap2_fs_pa2",
141*4882a593Smuzhiyun						"dap2_sclk_pa3",
142*4882a593Smuzhiyun						"dap2_din_pa4",
143*4882a593Smuzhiyun						"dap2_dout_pa5";
144*4882a593Smuzhiyun				nvidia,function = "i2s1";
145*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
147*4882a593Smuzhiyun			};
148*4882a593Smuzhiyun			sdio3 {
149*4882a593Smuzhiyun				nvidia,pins = "drive_sdio3";
150*4882a593Smuzhiyun				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
151*4882a593Smuzhiyun				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
152*4882a593Smuzhiyun				nvidia,pull-down-strength = <46>;
153*4882a593Smuzhiyun				nvidia,pull-up-strength = <42>;
154*4882a593Smuzhiyun				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
155*4882a593Smuzhiyun				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
156*4882a593Smuzhiyun			};
157*4882a593Smuzhiyun			uart3_txd_pw6 {
158*4882a593Smuzhiyun				nvidia,pins =	"uart3_txd_pw6",
159*4882a593Smuzhiyun						"uart3_cts_n_pa1",
160*4882a593Smuzhiyun						"uart3_rts_n_pc0",
161*4882a593Smuzhiyun						"uart3_rxd_pw7";
162*4882a593Smuzhiyun				nvidia,function = "uartc";
163*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
164*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
165*4882a593Smuzhiyun			};
166*4882a593Smuzhiyun		};
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	serial@70006000 {
170*4882a593Smuzhiyun		status = "okay";
171*4882a593Smuzhiyun	};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun	serial@70006200 {
174*4882a593Smuzhiyun		compatible = "nvidia,tegra30-hsuart";
175*4882a593Smuzhiyun		status = "okay";
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun	pwm@7000a000 {
179*4882a593Smuzhiyun		status = "okay";
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	panelddc: i2c@7000c000 {
183*4882a593Smuzhiyun		status = "okay";
184*4882a593Smuzhiyun		clock-frequency = <100000>;
185*4882a593Smuzhiyun	};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun	i2c@7000c400 {
188*4882a593Smuzhiyun		status = "okay";
189*4882a593Smuzhiyun		clock-frequency = <100000>;
190*4882a593Smuzhiyun	};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun	i2c@7000c500 {
193*4882a593Smuzhiyun		status = "okay";
194*4882a593Smuzhiyun		clock-frequency = <100000>;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun		/* ALS and Proximity sensor */
197*4882a593Smuzhiyun		isl29028@44 {
198*4882a593Smuzhiyun			compatible = "isil,isl29028";
199*4882a593Smuzhiyun			reg = <0x44>;
200*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
201*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
202*4882a593Smuzhiyun		};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun		i2cmux@70 {
205*4882a593Smuzhiyun			compatible = "nxp,pca9546";
206*4882a593Smuzhiyun			#address-cells = <1>;
207*4882a593Smuzhiyun			#size-cells = <0>;
208*4882a593Smuzhiyun			reg = <0x70>;
209*4882a593Smuzhiyun			reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
210*4882a593Smuzhiyun		};
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun	i2c@7000c700 {
214*4882a593Smuzhiyun		status = "okay";
215*4882a593Smuzhiyun		clock-frequency = <100000>;
216*4882a593Smuzhiyun	};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun	i2c@7000d000 {
219*4882a593Smuzhiyun		status = "okay";
220*4882a593Smuzhiyun		clock-frequency = <100000>;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun		wm8903: wm8903@1a {
223*4882a593Smuzhiyun			compatible = "wlf,wm8903";
224*4882a593Smuzhiyun			reg = <0x1a>;
225*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
226*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun			gpio-controller;
229*4882a593Smuzhiyun			#gpio-cells = <2>;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun			micdet-cfg = <0>;
232*4882a593Smuzhiyun			micdet-delay = <100>;
233*4882a593Smuzhiyun			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
234*4882a593Smuzhiyun		};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun		pmic: tps65911@2d {
237*4882a593Smuzhiyun			compatible = "ti,tps65911";
238*4882a593Smuzhiyun			reg = <0x2d>;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
241*4882a593Smuzhiyun			#interrupt-cells = <2>;
242*4882a593Smuzhiyun			interrupt-controller;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun			ti,system-power-controller;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun			#gpio-cells = <2>;
247*4882a593Smuzhiyun			gpio-controller;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun			vcc1-supply = <&vdd_ac_bat_reg>;
250*4882a593Smuzhiyun			vcc2-supply = <&vdd_ac_bat_reg>;
251*4882a593Smuzhiyun			vcc3-supply = <&vio_reg>;
252*4882a593Smuzhiyun			vcc4-supply = <&vdd_5v0_reg>;
253*4882a593Smuzhiyun			vcc5-supply = <&vdd_ac_bat_reg>;
254*4882a593Smuzhiyun			vcc6-supply = <&vdd2_reg>;
255*4882a593Smuzhiyun			vcc7-supply = <&vdd_ac_bat_reg>;
256*4882a593Smuzhiyun			vccio-supply = <&vdd_ac_bat_reg>;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun			regulators {
259*4882a593Smuzhiyun				vdd1_reg: vdd1 {
260*4882a593Smuzhiyun					regulator-name = "vddio_ddr_1v2";
261*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
262*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
263*4882a593Smuzhiyun					regulator-always-on;
264*4882a593Smuzhiyun				};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun				vdd2_reg: vdd2 {
267*4882a593Smuzhiyun					regulator-name = "vdd_1v5_gen";
268*4882a593Smuzhiyun					regulator-min-microvolt = <1500000>;
269*4882a593Smuzhiyun					regulator-max-microvolt = <1500000>;
270*4882a593Smuzhiyun					regulator-always-on;
271*4882a593Smuzhiyun				};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun				vddctrl_reg: vddctrl {
274*4882a593Smuzhiyun					regulator-name = "vdd_cpu,vdd_sys";
275*4882a593Smuzhiyun					regulator-min-microvolt = <1000000>;
276*4882a593Smuzhiyun					regulator-max-microvolt = <1000000>;
277*4882a593Smuzhiyun					regulator-always-on;
278*4882a593Smuzhiyun				};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun				vio_reg: vio {
281*4882a593Smuzhiyun					regulator-name = "vdd_1v8_gen";
282*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
283*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
284*4882a593Smuzhiyun					regulator-always-on;
285*4882a593Smuzhiyun				};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun				ldo1_reg: ldo1 {
288*4882a593Smuzhiyun					regulator-name = "vdd_pexa,vdd_pexb";
289*4882a593Smuzhiyun					regulator-min-microvolt = <1050000>;
290*4882a593Smuzhiyun					regulator-max-microvolt = <1050000>;
291*4882a593Smuzhiyun				};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun				ldo2_reg: ldo2 {
294*4882a593Smuzhiyun					regulator-name = "vdd_sata,avdd_plle";
295*4882a593Smuzhiyun					regulator-min-microvolt = <1050000>;
296*4882a593Smuzhiyun					regulator-max-microvolt = <1050000>;
297*4882a593Smuzhiyun				};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun				/* LDO3 is not connected to anything */
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun				ldo4_reg: ldo4 {
302*4882a593Smuzhiyun					regulator-name = "vdd_rtc";
303*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
304*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
305*4882a593Smuzhiyun					regulator-always-on;
306*4882a593Smuzhiyun				};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun				ldo5_reg: ldo5 {
309*4882a593Smuzhiyun					regulator-name = "vddio_sdmmc,avdd_vdac";
310*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
311*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
312*4882a593Smuzhiyun					regulator-always-on;
313*4882a593Smuzhiyun				};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun				ldo6_reg: ldo6 {
316*4882a593Smuzhiyun					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
317*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
318*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
319*4882a593Smuzhiyun				};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun				ldo7_reg: ldo7 {
322*4882a593Smuzhiyun					regulator-name = "vdd_pllm,x,u,a_p_c_s";
323*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
324*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
325*4882a593Smuzhiyun					regulator-always-on;
326*4882a593Smuzhiyun				};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun				ldo8_reg: ldo8 {
329*4882a593Smuzhiyun					regulator-name = "vdd_ddr_hs";
330*4882a593Smuzhiyun					regulator-min-microvolt = <1000000>;
331*4882a593Smuzhiyun					regulator-max-microvolt = <1000000>;
332*4882a593Smuzhiyun					regulator-always-on;
333*4882a593Smuzhiyun				};
334*4882a593Smuzhiyun			};
335*4882a593Smuzhiyun		};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun		temperature-sensor@4c {
338*4882a593Smuzhiyun			compatible = "onnn,nct1008";
339*4882a593Smuzhiyun			reg = <0x4c>;
340*4882a593Smuzhiyun			vcc-supply = <&sys_3v3_reg>;
341*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
342*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
343*4882a593Smuzhiyun		};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun		tps62361@60 {
346*4882a593Smuzhiyun			compatible = "ti,tps62361";
347*4882a593Smuzhiyun			reg = <0x60>;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun			regulator-name = "tps62361-vout";
350*4882a593Smuzhiyun			regulator-min-microvolt = <500000>;
351*4882a593Smuzhiyun			regulator-max-microvolt = <1500000>;
352*4882a593Smuzhiyun			regulator-boot-on;
353*4882a593Smuzhiyun			regulator-always-on;
354*4882a593Smuzhiyun			ti,vsel0-state-high;
355*4882a593Smuzhiyun			ti,vsel1-state-high;
356*4882a593Smuzhiyun		};
357*4882a593Smuzhiyun	};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun	spi@7000da00 {
360*4882a593Smuzhiyun		status = "okay";
361*4882a593Smuzhiyun		spi-max-frequency = <25000000>;
362*4882a593Smuzhiyun		spi-flash@1 {
363*4882a593Smuzhiyun			compatible = "winbond,w25q32", "jedec,spi-nor";
364*4882a593Smuzhiyun			reg = <1>;
365*4882a593Smuzhiyun			spi-max-frequency = <20000000>;
366*4882a593Smuzhiyun		};
367*4882a593Smuzhiyun	};
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun	pmc@7000e400 {
370*4882a593Smuzhiyun		status = "okay";
371*4882a593Smuzhiyun		nvidia,invert-interrupt;
372*4882a593Smuzhiyun		nvidia,suspend-mode = <1>;
373*4882a593Smuzhiyun		nvidia,cpu-pwr-good-time = <2000>;
374*4882a593Smuzhiyun		nvidia,cpu-pwr-off-time = <200>;
375*4882a593Smuzhiyun		nvidia,core-pwr-good-time = <3845 3845>;
376*4882a593Smuzhiyun		nvidia,core-pwr-off-time = <0>;
377*4882a593Smuzhiyun		nvidia,core-power-req-active-high;
378*4882a593Smuzhiyun		nvidia,sys-clock-req-active-high;
379*4882a593Smuzhiyun	};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun	ahub@70080000 {
382*4882a593Smuzhiyun		i2s@70080400 {
383*4882a593Smuzhiyun			status = "okay";
384*4882a593Smuzhiyun		};
385*4882a593Smuzhiyun	};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun	mmc@78000000 {
388*4882a593Smuzhiyun		status = "okay";
389*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
390*4882a593Smuzhiyun		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
391*4882a593Smuzhiyun		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
392*4882a593Smuzhiyun		bus-width = <4>;
393*4882a593Smuzhiyun	};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun	mmc@78000600 {
396*4882a593Smuzhiyun		status = "okay";
397*4882a593Smuzhiyun		bus-width = <8>;
398*4882a593Smuzhiyun		non-removable;
399*4882a593Smuzhiyun	};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun	usb@7d008000 {
402*4882a593Smuzhiyun		status = "okay";
403*4882a593Smuzhiyun	};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun	usb-phy@7d008000 {
406*4882a593Smuzhiyun		vbus-supply = <&usb3_vbus_reg>;
407*4882a593Smuzhiyun		status = "okay";
408*4882a593Smuzhiyun	};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun	backlight: backlight {
411*4882a593Smuzhiyun		compatible = "pwm-backlight";
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
414*4882a593Smuzhiyun		power-supply = <&vdd_bl_reg>;
415*4882a593Smuzhiyun		pwms = <&pwm 0 5000000>;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
418*4882a593Smuzhiyun		default-brightness-level = <6>;
419*4882a593Smuzhiyun	};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun	clk32k_in: clock@0 {
422*4882a593Smuzhiyun		compatible = "fixed-clock";
423*4882a593Smuzhiyun		clock-frequency = <32768>;
424*4882a593Smuzhiyun		#clock-cells = <0>;
425*4882a593Smuzhiyun	};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun	panel: panel {
428*4882a593Smuzhiyun		compatible = "chunghwa,claa101wb01";
429*4882a593Smuzhiyun		ddc-i2c-bus = <&panelddc>;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun		power-supply = <&vdd_pnl1_reg>;
432*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun		backlight = <&backlight>;
435*4882a593Smuzhiyun	};
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun	vdd_ac_bat_reg: regulator@0 {
438*4882a593Smuzhiyun		compatible = "regulator-fixed";
439*4882a593Smuzhiyun		regulator-name = "vdd_ac_bat";
440*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
441*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
442*4882a593Smuzhiyun		regulator-always-on;
443*4882a593Smuzhiyun	};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun	cam_1v8_reg: regulator@1 {
446*4882a593Smuzhiyun		compatible = "regulator-fixed";
447*4882a593Smuzhiyun		regulator-name = "cam_1v8";
448*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
449*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
450*4882a593Smuzhiyun		enable-active-high;
451*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
452*4882a593Smuzhiyun		vin-supply = <&vio_reg>;
453*4882a593Smuzhiyun	};
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun	cp_5v_reg: regulator@2 {
456*4882a593Smuzhiyun		compatible = "regulator-fixed";
457*4882a593Smuzhiyun		regulator-name = "cp_5v";
458*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
459*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
460*4882a593Smuzhiyun		regulator-boot-on;
461*4882a593Smuzhiyun		regulator-always-on;
462*4882a593Smuzhiyun		enable-active-high;
463*4882a593Smuzhiyun		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
464*4882a593Smuzhiyun	};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun	emmc_3v3_reg: regulator@3 {
467*4882a593Smuzhiyun		compatible = "regulator-fixed";
468*4882a593Smuzhiyun		regulator-name = "emmc_3v3";
469*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
470*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
471*4882a593Smuzhiyun		regulator-always-on;
472*4882a593Smuzhiyun		regulator-boot-on;
473*4882a593Smuzhiyun		enable-active-high;
474*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
475*4882a593Smuzhiyun		vin-supply = <&sys_3v3_reg>;
476*4882a593Smuzhiyun	};
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun	modem_3v3_reg: regulator@4 {
479*4882a593Smuzhiyun		compatible = "regulator-fixed";
480*4882a593Smuzhiyun		regulator-name = "modem_3v3";
481*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
482*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
483*4882a593Smuzhiyun		enable-active-high;
484*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
485*4882a593Smuzhiyun	};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun	pex_hvdd_3v3_reg: regulator@5 {
488*4882a593Smuzhiyun		compatible = "regulator-fixed";
489*4882a593Smuzhiyun		regulator-name = "pex_hvdd_3v3";
490*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
491*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
492*4882a593Smuzhiyun		enable-active-high;
493*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
494*4882a593Smuzhiyun		vin-supply = <&sys_3v3_reg>;
495*4882a593Smuzhiyun	};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun	vdd_cam1_ldo_reg: regulator@6 {
498*4882a593Smuzhiyun		compatible = "regulator-fixed";
499*4882a593Smuzhiyun		regulator-name = "vdd_cam1_ldo";
500*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
501*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
502*4882a593Smuzhiyun		enable-active-high;
503*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
504*4882a593Smuzhiyun		vin-supply = <&sys_3v3_reg>;
505*4882a593Smuzhiyun	};
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun	vdd_cam2_ldo_reg: regulator@7 {
508*4882a593Smuzhiyun		compatible = "regulator-fixed";
509*4882a593Smuzhiyun		regulator-name = "vdd_cam2_ldo";
510*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
511*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
512*4882a593Smuzhiyun		enable-active-high;
513*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
514*4882a593Smuzhiyun		vin-supply = <&sys_3v3_reg>;
515*4882a593Smuzhiyun	};
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun	vdd_cam3_ldo_reg: regulator@8 {
518*4882a593Smuzhiyun		compatible = "regulator-fixed";
519*4882a593Smuzhiyun		regulator-name = "vdd_cam3_ldo";
520*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
521*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
522*4882a593Smuzhiyun		enable-active-high;
523*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
524*4882a593Smuzhiyun		vin-supply = <&sys_3v3_reg>;
525*4882a593Smuzhiyun	};
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun	vdd_com_reg: regulator@9 {
528*4882a593Smuzhiyun		compatible = "regulator-fixed";
529*4882a593Smuzhiyun		regulator-name = "vdd_com";
530*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
531*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
532*4882a593Smuzhiyun		regulator-always-on;
533*4882a593Smuzhiyun		regulator-boot-on;
534*4882a593Smuzhiyun		enable-active-high;
535*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
536*4882a593Smuzhiyun		vin-supply = <&sys_3v3_reg>;
537*4882a593Smuzhiyun	};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun	vdd_fuse_3v3_reg: regulator@10 {
540*4882a593Smuzhiyun		compatible = "regulator-fixed";
541*4882a593Smuzhiyun		regulator-name = "vdd_fuse_3v3";
542*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
543*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
544*4882a593Smuzhiyun		enable-active-high;
545*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
546*4882a593Smuzhiyun		vin-supply = <&sys_3v3_reg>;
547*4882a593Smuzhiyun	};
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun	vdd_pnl1_reg: regulator@11 {
550*4882a593Smuzhiyun		compatible = "regulator-fixed";
551*4882a593Smuzhiyun		regulator-name = "vdd_pnl1";
552*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
553*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
554*4882a593Smuzhiyun		regulator-always-on;
555*4882a593Smuzhiyun		regulator-boot-on;
556*4882a593Smuzhiyun		enable-active-high;
557*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
558*4882a593Smuzhiyun		vin-supply = <&sys_3v3_reg>;
559*4882a593Smuzhiyun	};
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun	vdd_vid_reg: regulator@12 {
562*4882a593Smuzhiyun		compatible = "regulator-fixed";
563*4882a593Smuzhiyun		regulator-name = "vddio_vid";
564*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
565*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
566*4882a593Smuzhiyun		enable-active-high;
567*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
568*4882a593Smuzhiyun		gpio-open-drain;
569*4882a593Smuzhiyun		vin-supply = <&vdd_5v0_reg>;
570*4882a593Smuzhiyun	};
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun	sound {
573*4882a593Smuzhiyun		compatible = "nvidia,tegra-audio-wm8903-cardhu",
574*4882a593Smuzhiyun			     "nvidia,tegra-audio-wm8903";
575*4882a593Smuzhiyun		nvidia,model = "NVIDIA Tegra Cardhu";
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun		nvidia,audio-routing =
578*4882a593Smuzhiyun			"Headphone Jack", "HPOUTR",
579*4882a593Smuzhiyun			"Headphone Jack", "HPOUTL",
580*4882a593Smuzhiyun			"Int Spk", "ROP",
581*4882a593Smuzhiyun			"Int Spk", "RON",
582*4882a593Smuzhiyun			"Int Spk", "LOP",
583*4882a593Smuzhiyun			"Int Spk", "LON",
584*4882a593Smuzhiyun			"Mic Jack", "MICBIAS",
585*4882a593Smuzhiyun			"IN1L", "Mic Jack";
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun		nvidia,i2s-controller = <&tegra_i2s1>;
588*4882a593Smuzhiyun		nvidia,audio-codec = <&wm8903>;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
591*4882a593Smuzhiyun		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
592*4882a593Smuzhiyun			GPIO_ACTIVE_LOW>;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
595*4882a593Smuzhiyun			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
596*4882a593Smuzhiyun			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
597*4882a593Smuzhiyun		clock-names = "pll_a", "pll_a_out0", "mclk";
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
600*4882a593Smuzhiyun				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
603*4882a593Smuzhiyun					 <&tegra_car TEGRA30_CLK_EXTERN1>;
604*4882a593Smuzhiyun	};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun	gpio-keys {
607*4882a593Smuzhiyun		compatible = "gpio-keys";
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun		power {
610*4882a593Smuzhiyun			label = "Power";
611*4882a593Smuzhiyun			interrupt-parent = <&pmic>;
612*4882a593Smuzhiyun			interrupts = <2 0>;
613*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
614*4882a593Smuzhiyun			debounce-interval = <100>;
615*4882a593Smuzhiyun			wakeup-source;
616*4882a593Smuzhiyun		};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun		volume-down {
619*4882a593Smuzhiyun			label = "Volume Down";
620*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
621*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
622*4882a593Smuzhiyun			debounce-interval = <10>;
623*4882a593Smuzhiyun		};
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun		volume-up {
626*4882a593Smuzhiyun			label = "Volume Up";
627*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
628*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
629*4882a593Smuzhiyun			debounce-interval = <10>;
630*4882a593Smuzhiyun		};
631*4882a593Smuzhiyun	};
632*4882a593Smuzhiyun};
633