1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 5*4882a593Smuzhiyun#include "tegra20.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "NVIDIA Tegra20 Harmony evaluation board"; 9*4882a593Smuzhiyun compatible = "nvidia,harmony", "nvidia,tegra20"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun aliases { 12*4882a593Smuzhiyun rtc0 = "/i2c@7000d000/tps6586x@34"; 13*4882a593Smuzhiyun rtc1 = "/rtc@7000e000"; 14*4882a593Smuzhiyun serial0 = &uartd; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun chosen { 18*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory@0 { 22*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun host1x@50000000 { 26*4882a593Smuzhiyun dc@54200000 { 27*4882a593Smuzhiyun rgb { 28*4882a593Smuzhiyun status = "okay"; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun nvidia,panel = <&panel>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun hdmi@54280000 { 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun hdmi-supply = <&vdd_5v0_hdmi>; 38*4882a593Smuzhiyun vdd-supply = <&hdmi_vdd_reg>; 39*4882a593Smuzhiyun pll-supply = <&hdmi_pll_reg>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun nvidia,ddc-i2c-bus = <&hdmi_ddc>; 42*4882a593Smuzhiyun nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 43*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun pinmux@70000014 { 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun state_default: pinmux { 52*4882a593Smuzhiyun ata { 53*4882a593Smuzhiyun nvidia,pins = "ata"; 54*4882a593Smuzhiyun nvidia,function = "ide"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun atb { 57*4882a593Smuzhiyun nvidia,pins = "atb", "gma", "gme"; 58*4882a593Smuzhiyun nvidia,function = "sdio4"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun atc { 61*4882a593Smuzhiyun nvidia,pins = "atc"; 62*4882a593Smuzhiyun nvidia,function = "nand"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun atd { 65*4882a593Smuzhiyun nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", 66*4882a593Smuzhiyun "spia", "spib", "spic"; 67*4882a593Smuzhiyun nvidia,function = "gmi"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun cdev1 { 70*4882a593Smuzhiyun nvidia,pins = "cdev1"; 71*4882a593Smuzhiyun nvidia,function = "plla_out"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun cdev2 { 74*4882a593Smuzhiyun nvidia,pins = "cdev2"; 75*4882a593Smuzhiyun nvidia,function = "pllp_out4"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun crtp { 78*4882a593Smuzhiyun nvidia,pins = "crtp"; 79*4882a593Smuzhiyun nvidia,function = "crt"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun csus { 82*4882a593Smuzhiyun nvidia,pins = "csus"; 83*4882a593Smuzhiyun nvidia,function = "vi_sensor_clk"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun dap1 { 86*4882a593Smuzhiyun nvidia,pins = "dap1"; 87*4882a593Smuzhiyun nvidia,function = "dap1"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun dap2 { 90*4882a593Smuzhiyun nvidia,pins = "dap2"; 91*4882a593Smuzhiyun nvidia,function = "dap2"; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun dap3 { 94*4882a593Smuzhiyun nvidia,pins = "dap3"; 95*4882a593Smuzhiyun nvidia,function = "dap3"; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun dap4 { 98*4882a593Smuzhiyun nvidia,pins = "dap4"; 99*4882a593Smuzhiyun nvidia,function = "dap4"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun ddc { 102*4882a593Smuzhiyun nvidia,pins = "ddc"; 103*4882a593Smuzhiyun nvidia,function = "i2c2"; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun dta { 106*4882a593Smuzhiyun nvidia,pins = "dta", "dtd"; 107*4882a593Smuzhiyun nvidia,function = "sdio2"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun dtb { 110*4882a593Smuzhiyun nvidia,pins = "dtb", "dtc", "dte"; 111*4882a593Smuzhiyun nvidia,function = "rsvd1"; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun dtf { 114*4882a593Smuzhiyun nvidia,pins = "dtf"; 115*4882a593Smuzhiyun nvidia,function = "i2c3"; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun gmc { 118*4882a593Smuzhiyun nvidia,pins = "gmc"; 119*4882a593Smuzhiyun nvidia,function = "uartd"; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun gpu7 { 122*4882a593Smuzhiyun nvidia,pins = "gpu7"; 123*4882a593Smuzhiyun nvidia,function = "rtck"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun gpv { 126*4882a593Smuzhiyun nvidia,pins = "gpv", "slxa", "slxk"; 127*4882a593Smuzhiyun nvidia,function = "pcie"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun hdint { 130*4882a593Smuzhiyun nvidia,pins = "hdint", "pta"; 131*4882a593Smuzhiyun nvidia,function = "hdmi"; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun i2cp { 134*4882a593Smuzhiyun nvidia,pins = "i2cp"; 135*4882a593Smuzhiyun nvidia,function = "i2cp"; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun irrx { 138*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx"; 139*4882a593Smuzhiyun nvidia,function = "uarta"; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun kbca { 142*4882a593Smuzhiyun nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 143*4882a593Smuzhiyun "kbce", "kbcf"; 144*4882a593Smuzhiyun nvidia,function = "kbc"; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun lcsn { 147*4882a593Smuzhiyun nvidia,pins = "lcsn", "ld0", "ld1", "ld2", 148*4882a593Smuzhiyun "ld3", "ld4", "ld5", "ld6", "ld7", 149*4882a593Smuzhiyun "ld8", "ld9", "ld10", "ld11", "ld12", 150*4882a593Smuzhiyun "ld13", "ld14", "ld15", "ld16", "ld17", 151*4882a593Smuzhiyun "ldc", "ldi", "lhp0", "lhp1", "lhp2", 152*4882a593Smuzhiyun "lhs", "lm0", "lm1", "lpp", "lpw0", 153*4882a593Smuzhiyun "lpw1", "lpw2", "lsc0", "lsc1", "lsck", 154*4882a593Smuzhiyun "lsda", "lsdi", "lspi", "lvp0", "lvp1", 155*4882a593Smuzhiyun "lvs"; 156*4882a593Smuzhiyun nvidia,function = "displaya"; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun owc { 159*4882a593Smuzhiyun nvidia,pins = "owc", "spdi", "spdo", "uac"; 160*4882a593Smuzhiyun nvidia,function = "rsvd2"; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun pmc { 163*4882a593Smuzhiyun nvidia,pins = "pmc"; 164*4882a593Smuzhiyun nvidia,function = "pwr_on"; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun rm { 167*4882a593Smuzhiyun nvidia,pins = "rm"; 168*4882a593Smuzhiyun nvidia,function = "i2c1"; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun sdb { 171*4882a593Smuzhiyun nvidia,pins = "sdb", "sdc", "sdd"; 172*4882a593Smuzhiyun nvidia,function = "pwm"; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun sdio1 { 175*4882a593Smuzhiyun nvidia,pins = "sdio1"; 176*4882a593Smuzhiyun nvidia,function = "sdio1"; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun slxc { 179*4882a593Smuzhiyun nvidia,pins = "slxc", "slxd"; 180*4882a593Smuzhiyun nvidia,function = "spdif"; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun spid { 183*4882a593Smuzhiyun nvidia,pins = "spid", "spie", "spif"; 184*4882a593Smuzhiyun nvidia,function = "spi1"; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun spig { 187*4882a593Smuzhiyun nvidia,pins = "spig", "spih"; 188*4882a593Smuzhiyun nvidia,function = "spi2_alt"; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun uaa { 191*4882a593Smuzhiyun nvidia,pins = "uaa", "uab", "uda"; 192*4882a593Smuzhiyun nvidia,function = "ulpi"; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun uad { 195*4882a593Smuzhiyun nvidia,pins = "uad"; 196*4882a593Smuzhiyun nvidia,function = "irda"; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun uca { 199*4882a593Smuzhiyun nvidia,pins = "uca", "ucb"; 200*4882a593Smuzhiyun nvidia,function = "uartc"; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun conf_ata { 203*4882a593Smuzhiyun nvidia,pins = "ata", "atb", "atc", "atd", "ate", 204*4882a593Smuzhiyun "cdev1", "cdev2", "dap1", "dtb", "gma", 205*4882a593Smuzhiyun "gmb", "gmc", "gmd", "gme", "gpu7", 206*4882a593Smuzhiyun "gpv", "i2cp", "pta", "rm", "slxa", 207*4882a593Smuzhiyun "slxk", "spia", "spib", "uac"; 208*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 209*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun conf_ck32 { 212*4882a593Smuzhiyun nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 213*4882a593Smuzhiyun "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 214*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun conf_csus { 217*4882a593Smuzhiyun nvidia,pins = "csus", "spid", "spif"; 218*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 219*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun conf_crtp { 222*4882a593Smuzhiyun nvidia,pins = "crtp", "dap2", "dap3", "dap4", 223*4882a593Smuzhiyun "dtc", "dte", "dtf", "gpu", "sdio1", 224*4882a593Smuzhiyun "slxc", "slxd", "spdi", "spdo", "spig", 225*4882a593Smuzhiyun "uda"; 226*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 227*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun conf_ddc { 230*4882a593Smuzhiyun nvidia,pins = "ddc", "dta", "dtd", "kbca", 231*4882a593Smuzhiyun "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 232*4882a593Smuzhiyun "sdc"; 233*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 234*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun conf_hdint { 237*4882a593Smuzhiyun nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 238*4882a593Smuzhiyun "lpw1", "lsc1", "lsck", "lsda", "lsdi", 239*4882a593Smuzhiyun "lvp0", "owc", "sdb"; 240*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun conf_irrx { 243*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx", "sdd", "spic", 244*4882a593Smuzhiyun "spie", "spih", "uaa", "uab", "uad", 245*4882a593Smuzhiyun "uca", "ucb"; 246*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 247*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun conf_lc { 250*4882a593Smuzhiyun nvidia,pins = "lc", "ls"; 251*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun conf_ld0 { 254*4882a593Smuzhiyun nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 255*4882a593Smuzhiyun "ld5", "ld6", "ld7", "ld8", "ld9", 256*4882a593Smuzhiyun "ld10", "ld11", "ld12", "ld13", "ld14", 257*4882a593Smuzhiyun "ld15", "ld16", "ld17", "ldi", "lhp0", 258*4882a593Smuzhiyun "lhp1", "lhp2", "lhs", "lm0", "lpp", 259*4882a593Smuzhiyun "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 260*4882a593Smuzhiyun "lvs", "pmc"; 261*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun conf_ld17_0 { 264*4882a593Smuzhiyun nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 265*4882a593Smuzhiyun "ld23_22"; 266*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun i2s@70002800 { 272*4882a593Smuzhiyun status = "okay"; 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun serial@70006300 { 276*4882a593Smuzhiyun status = "okay"; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun pwm: pwm@7000a000 { 280*4882a593Smuzhiyun status = "okay"; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun i2c@7000c000 { 284*4882a593Smuzhiyun status = "okay"; 285*4882a593Smuzhiyun clock-frequency = <400000>; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun wm8903: wm8903@1a { 288*4882a593Smuzhiyun compatible = "wlf,wm8903"; 289*4882a593Smuzhiyun reg = <0x1a>; 290*4882a593Smuzhiyun interrupt-parent = <&gpio>; 291*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun gpio-controller; 294*4882a593Smuzhiyun #gpio-cells = <2>; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun micdet-cfg = <0>; 297*4882a593Smuzhiyun micdet-delay = <100>; 298*4882a593Smuzhiyun gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun hdmi_ddc: i2c@7000c400 { 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun clock-frequency = <100000>; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun i2c@7000c500 { 308*4882a593Smuzhiyun status = "okay"; 309*4882a593Smuzhiyun clock-frequency = <400000>; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun i2c@7000d000 { 313*4882a593Smuzhiyun status = "okay"; 314*4882a593Smuzhiyun clock-frequency = <400000>; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun pmic: tps6586x@34 { 317*4882a593Smuzhiyun compatible = "ti,tps6586x"; 318*4882a593Smuzhiyun reg = <0x34>; 319*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun ti,system-power-controller; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun #gpio-cells = <2>; 324*4882a593Smuzhiyun gpio-controller; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun sys-supply = <&vdd_5v0_reg>; 327*4882a593Smuzhiyun vin-sm0-supply = <&sys_reg>; 328*4882a593Smuzhiyun vin-sm1-supply = <&sys_reg>; 329*4882a593Smuzhiyun vin-sm2-supply = <&sys_reg>; 330*4882a593Smuzhiyun vinldo01-supply = <&sm2_reg>; 331*4882a593Smuzhiyun vinldo23-supply = <&sm2_reg>; 332*4882a593Smuzhiyun vinldo4-supply = <&sm2_reg>; 333*4882a593Smuzhiyun vinldo678-supply = <&sm2_reg>; 334*4882a593Smuzhiyun vinldo9-supply = <&sm2_reg>; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun regulators { 337*4882a593Smuzhiyun sys_reg: sys { 338*4882a593Smuzhiyun regulator-name = "vdd_sys"; 339*4882a593Smuzhiyun regulator-always-on; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun sm0 { 343*4882a593Smuzhiyun regulator-name = "vdd_sm0,vdd_core"; 344*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 345*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 346*4882a593Smuzhiyun regulator-always-on; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun sm1 { 350*4882a593Smuzhiyun regulator-name = "vdd_sm1,vdd_cpu"; 351*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 352*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 353*4882a593Smuzhiyun regulator-always-on; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun sm2_reg: sm2 { 357*4882a593Smuzhiyun regulator-name = "vdd_sm2,vin_ldo*"; 358*4882a593Smuzhiyun regulator-min-microvolt = <3700000>; 359*4882a593Smuzhiyun regulator-max-microvolt = <3700000>; 360*4882a593Smuzhiyun regulator-always-on; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun pci_clk_reg: ldo0 { 364*4882a593Smuzhiyun regulator-name = "vdd_ldo0,vddio_pex_clk"; 365*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 366*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun ldo1 { 370*4882a593Smuzhiyun regulator-name = "vdd_ldo1,avdd_pll*"; 371*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 372*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 373*4882a593Smuzhiyun regulator-always-on; 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun ldo2 { 377*4882a593Smuzhiyun regulator-name = "vdd_ldo2,vdd_rtc"; 378*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 379*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun ldo3 { 383*4882a593Smuzhiyun regulator-name = "vdd_ldo3,avdd_usb*"; 384*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 385*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 386*4882a593Smuzhiyun regulator-always-on; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun ldo4 { 390*4882a593Smuzhiyun regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 391*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 392*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 393*4882a593Smuzhiyun regulator-always-on; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun ldo5 { 397*4882a593Smuzhiyun regulator-name = "vdd_ldo5,vcore_mmc"; 398*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 399*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 400*4882a593Smuzhiyun regulator-always-on; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun ldo6 { 404*4882a593Smuzhiyun regulator-name = "vdd_ldo6,avdd_vdac"; 405*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 406*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun hdmi_vdd_reg: ldo7 { 410*4882a593Smuzhiyun regulator-name = "vdd_ldo7,avdd_hdmi"; 411*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 412*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun hdmi_pll_reg: ldo8 { 416*4882a593Smuzhiyun regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 417*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 418*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun ldo9 { 422*4882a593Smuzhiyun regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 423*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 424*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 425*4882a593Smuzhiyun regulator-always-on; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun ldo_rtc { 429*4882a593Smuzhiyun regulator-name = "vdd_rtc_out,vdd_cell"; 430*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 431*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 432*4882a593Smuzhiyun regulator-always-on; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun temperature-sensor@4c { 438*4882a593Smuzhiyun compatible = "adi,adt7461"; 439*4882a593Smuzhiyun reg = <0x4c>; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun kbc@7000e200 { 444*4882a593Smuzhiyun status = "okay"; 445*4882a593Smuzhiyun nvidia,debounce-delay-ms = <2>; 446*4882a593Smuzhiyun nvidia,repeat-delay-ms = <160>; 447*4882a593Smuzhiyun nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; 448*4882a593Smuzhiyun nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; 449*4882a593Smuzhiyun linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) 450*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x03, KEY_S) 451*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x04, KEY_A) 452*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x05, KEY_Z) 453*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x07, KEY_FN) 454*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x07, KEY_MENU) 455*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x06, KEY_LEFTALT) 456*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT) 457*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x00, KEY_5) 458*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x01, KEY_4) 459*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x02, KEY_R) 460*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x03, KEY_E) 461*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x04, KEY_F) 462*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x05, KEY_D) 463*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x06, KEY_X) 464*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x00, KEY_7) 465*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x01, KEY_6) 466*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x02, KEY_T) 467*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x03, KEY_H) 468*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x04, KEY_G) 469*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x05, KEY_V) 470*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x06, KEY_C) 471*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x07, KEY_SPACE) 472*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x00, KEY_9) 473*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x01, KEY_8) 474*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x02, KEY_U) 475*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x03, KEY_Y) 476*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x04, KEY_J) 477*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x05, KEY_N) 478*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x06, KEY_B) 479*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) 480*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x00, KEY_MINUS) 481*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x01, KEY_0) 482*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x02, KEY_O) 483*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x03, KEY_I) 484*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x04, KEY_L) 485*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x05, KEY_K) 486*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x06, KEY_COMMA) 487*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x07, KEY_M) 488*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x01, KEY_EQUAL) 489*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) 490*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x03, KEY_ENTER) 491*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x07, KEY_MENU) 492*4882a593Smuzhiyun MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT) 493*4882a593Smuzhiyun MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT) 494*4882a593Smuzhiyun MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL) 495*4882a593Smuzhiyun MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL) 496*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) 497*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x01, KEY_P) 498*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) 499*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) 500*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x04, KEY_SLASH) 501*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x05, KEY_DOT) 502*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x00, KEY_F10) 503*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x01, KEY_F9) 504*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) 505*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x03, KEY_3) 506*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x04, KEY_2) 507*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x05, KEY_UP) 508*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x06, KEY_PRINT) 509*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) 510*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x00, KEY_INSERT) 511*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x01, KEY_DELETE) 512*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) 513*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) 514*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) 515*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x06, KEY_DOWN) 516*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x07, KEY_LEFT) 517*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x00, KEY_F11) 518*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x01, KEY_F12) 519*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x02, KEY_F8) 520*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x03, KEY_Q) 521*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x04, KEY_F4) 522*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x05, KEY_F3) 523*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x06, KEY_1) 524*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x07, KEY_F7) 525*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x00, KEY_ESC) 526*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) 527*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x02, KEY_F5) 528*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x03, KEY_TAB) 529*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x04, KEY_F1) 530*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x05, KEY_F2) 531*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) 532*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x07, KEY_F6) 533*4882a593Smuzhiyun MATRIX_KEY(0x14, 0x00, KEY_KP7) 534*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x00, KEY_KP9) 535*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x01, KEY_KP8) 536*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x02, KEY_KP4) 537*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x04, KEY_KP1) 538*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) 539*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x02, KEY_KP6) 540*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x03, KEY_KP5) 541*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x04, KEY_KP3) 542*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x05, KEY_KP2) 543*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x07, KEY_KP0) 544*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) 545*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) 546*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) 547*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) 548*4882a593Smuzhiyun MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) 549*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x03, KEY_HOME) 550*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x04, KEY_END) 551*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP) 552*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) 553*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN) 554*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) 555*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) 556*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x02, KEY_MUTE) 557*4882a593Smuzhiyun MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>; 558*4882a593Smuzhiyun }; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun pmc@7000e400 { 561*4882a593Smuzhiyun nvidia,invert-interrupt; 562*4882a593Smuzhiyun nvidia,suspend-mode = <1>; 563*4882a593Smuzhiyun nvidia,cpu-pwr-good-time = <5000>; 564*4882a593Smuzhiyun nvidia,cpu-pwr-off-time = <5000>; 565*4882a593Smuzhiyun nvidia,core-pwr-good-time = <3845 3845>; 566*4882a593Smuzhiyun nvidia,core-pwr-off-time = <3875>; 567*4882a593Smuzhiyun nvidia,sys-clock-req-active-high; 568*4882a593Smuzhiyun }; 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun pcie@80003000 { 571*4882a593Smuzhiyun status = "okay"; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun avdd-pex-supply = <&pci_vdd_reg>; 574*4882a593Smuzhiyun vdd-pex-supply = <&pci_vdd_reg>; 575*4882a593Smuzhiyun avdd-pex-pll-supply = <&pci_vdd_reg>; 576*4882a593Smuzhiyun avdd-plle-supply = <&pci_vdd_reg>; 577*4882a593Smuzhiyun vddio-pex-clk-supply = <&pci_clk_reg>; 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun pci@1,0 { 580*4882a593Smuzhiyun status = "okay"; 581*4882a593Smuzhiyun }; 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun pci@2,0 { 584*4882a593Smuzhiyun status = "okay"; 585*4882a593Smuzhiyun }; 586*4882a593Smuzhiyun }; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun usb@c5000000 { 589*4882a593Smuzhiyun status = "okay"; 590*4882a593Smuzhiyun }; 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun usb-phy@c5000000 { 593*4882a593Smuzhiyun status = "okay"; 594*4882a593Smuzhiyun }; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun usb@c5004000 { 597*4882a593Smuzhiyun status = "okay"; 598*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 599*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun usb-phy@c5004000 { 603*4882a593Smuzhiyun status = "okay"; 604*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 605*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 606*4882a593Smuzhiyun }; 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun usb@c5008000 { 609*4882a593Smuzhiyun status = "okay"; 610*4882a593Smuzhiyun }; 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun usb-phy@c5008000 { 613*4882a593Smuzhiyun status = "okay"; 614*4882a593Smuzhiyun }; 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun mmc@c8000200 { 617*4882a593Smuzhiyun status = "okay"; 618*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 619*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 620*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; 621*4882a593Smuzhiyun bus-width = <4>; 622*4882a593Smuzhiyun }; 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun mmc@c8000600 { 625*4882a593Smuzhiyun status = "okay"; 626*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; 627*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 628*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 629*4882a593Smuzhiyun bus-width = <8>; 630*4882a593Smuzhiyun }; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun backlight: backlight { 633*4882a593Smuzhiyun compatible = "pwm-backlight"; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; 636*4882a593Smuzhiyun power-supply = <&vdd_bl_reg>; 637*4882a593Smuzhiyun pwms = <&pwm 0 5000000>; 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 640*4882a593Smuzhiyun default-brightness-level = <6>; 641*4882a593Smuzhiyun }; 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun clk32k_in: clock@0 { 644*4882a593Smuzhiyun compatible = "fixed-clock"; 645*4882a593Smuzhiyun clock-frequency = <32768>; 646*4882a593Smuzhiyun #clock-cells = <0>; 647*4882a593Smuzhiyun }; 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun gpio-keys { 650*4882a593Smuzhiyun compatible = "gpio-keys"; 651*4882a593Smuzhiyun 652*4882a593Smuzhiyun power { 653*4882a593Smuzhiyun label = "Power"; 654*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 655*4882a593Smuzhiyun linux,code = <KEY_POWER>; 656*4882a593Smuzhiyun wakeup-source; 657*4882a593Smuzhiyun }; 658*4882a593Smuzhiyun }; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun panel: panel { 661*4882a593Smuzhiyun compatible = "auo,b101aw03"; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun power-supply = <&vdd_pnl_reg>; 664*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun backlight = <&backlight>; 667*4882a593Smuzhiyun }; 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun vdd_5v0_reg: regulator@0 { 670*4882a593Smuzhiyun compatible = "regulator-fixed"; 671*4882a593Smuzhiyun regulator-name = "vdd_5v0"; 672*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 673*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 674*4882a593Smuzhiyun regulator-always-on; 675*4882a593Smuzhiyun }; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun regulator@1 { 678*4882a593Smuzhiyun compatible = "regulator-fixed"; 679*4882a593Smuzhiyun regulator-name = "vdd_1v5"; 680*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 681*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 682*4882a593Smuzhiyun gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 683*4882a593Smuzhiyun }; 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun regulator@2 { 686*4882a593Smuzhiyun compatible = "regulator-fixed"; 687*4882a593Smuzhiyun regulator-name = "vdd_1v2"; 688*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 689*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 690*4882a593Smuzhiyun gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 691*4882a593Smuzhiyun enable-active-high; 692*4882a593Smuzhiyun }; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun pci_vdd_reg: regulator@3 { 695*4882a593Smuzhiyun compatible = "regulator-fixed"; 696*4882a593Smuzhiyun regulator-name = "vdd_1v05"; 697*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 698*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 699*4882a593Smuzhiyun gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 700*4882a593Smuzhiyun enable-active-high; 701*4882a593Smuzhiyun }; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun vdd_pnl_reg: regulator@4 { 704*4882a593Smuzhiyun compatible = "regulator-fixed"; 705*4882a593Smuzhiyun regulator-name = "vdd_pnl"; 706*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 707*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 708*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 709*4882a593Smuzhiyun enable-active-high; 710*4882a593Smuzhiyun }; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun vdd_bl_reg: regulator@5 { 713*4882a593Smuzhiyun compatible = "regulator-fixed"; 714*4882a593Smuzhiyun regulator-name = "vdd_bl"; 715*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 716*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 717*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; 718*4882a593Smuzhiyun enable-active-high; 719*4882a593Smuzhiyun }; 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun vdd_5v0_hdmi: regulator@6 { 722*4882a593Smuzhiyun compatible = "regulator-fixed"; 723*4882a593Smuzhiyun regulator-name = "VDDIO_HDMI"; 724*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 725*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 726*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; 727*4882a593Smuzhiyun enable-active-high; 728*4882a593Smuzhiyun vin-supply = <&vdd_5v0_reg>; 729*4882a593Smuzhiyun }; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun sound { 732*4882a593Smuzhiyun compatible = "nvidia,tegra-audio-wm8903-harmony", 733*4882a593Smuzhiyun "nvidia,tegra-audio-wm8903"; 734*4882a593Smuzhiyun nvidia,model = "NVIDIA Tegra Harmony"; 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun nvidia,audio-routing = 737*4882a593Smuzhiyun "Headphone Jack", "HPOUTR", 738*4882a593Smuzhiyun "Headphone Jack", "HPOUTL", 739*4882a593Smuzhiyun "Int Spk", "ROP", 740*4882a593Smuzhiyun "Int Spk", "RON", 741*4882a593Smuzhiyun "Int Spk", "LOP", 742*4882a593Smuzhiyun "Int Spk", "LON", 743*4882a593Smuzhiyun "Mic Jack", "MICBIAS", 744*4882a593Smuzhiyun "IN1L", "Mic Jack"; 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s1>; 747*4882a593Smuzhiyun nvidia,audio-codec = <&wm8903>; 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 750*4882a593Smuzhiyun nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 751*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 752*4882a593Smuzhiyun nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) 753*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 754*4882a593Smuzhiyun nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) 755*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 758*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 759*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_CDEV1>; 760*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 761*4882a593Smuzhiyun }; 762*4882a593Smuzhiyun}; 763