1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 4*4882a593Smuzhiyun#include "tegra20.dtsi" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun model = "NVIDIA Tegra20 Harmony evaluation board"; 8*4882a593Smuzhiyun compatible = "nvidia,harmony", "nvidia,tegra20"; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun chosen { 11*4882a593Smuzhiyun stdout-path = &uartd; 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun aliases { 15*4882a593Smuzhiyun rtc0 = "/i2c@7000d000/tps6586x@34"; 16*4882a593Smuzhiyun rtc1 = "/rtc@7000e000"; 17*4882a593Smuzhiyun serial0 = &uartd; 18*4882a593Smuzhiyun usb0 = "/usb@c5000000"; 19*4882a593Smuzhiyun usb1 = "/usb@c5004000"; 20*4882a593Smuzhiyun usb2 = "/usb@c5008000"; 21*4882a593Smuzhiyun mmc0 = "/sdhci@c8000600"; 22*4882a593Smuzhiyun mmc1 = "/sdhci@c8000200"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun memory { 26*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun host1x@50000000 { 30*4882a593Smuzhiyun status = "okay"; 31*4882a593Smuzhiyun dc@54200000 { 32*4882a593Smuzhiyun status = "okay"; 33*4882a593Smuzhiyun rgb { 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun nvidia,panel = <&panel>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun display-timings { 39*4882a593Smuzhiyun timing@0 { 40*4882a593Smuzhiyun /* Seaboard has 1366x768 */ 41*4882a593Smuzhiyun clock-frequency = <42430000>; 42*4882a593Smuzhiyun hactive = <1024>; 43*4882a593Smuzhiyun vactive = <600>; 44*4882a593Smuzhiyun hback-porch = <138>; 45*4882a593Smuzhiyun hfront-porch = <34>; 46*4882a593Smuzhiyun hsync-len = <136>; 47*4882a593Smuzhiyun vback-porch = <21>; 48*4882a593Smuzhiyun vfront-porch = <4>; 49*4882a593Smuzhiyun vsync-len = <4>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun hdmi@54280000 { 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun hdmi-supply = <&vdd_5v0_hdmi>; 59*4882a593Smuzhiyun vdd-supply = <&hdmi_vdd_reg>; 60*4882a593Smuzhiyun pll-supply = <&hdmi_pll_reg>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun nvidia,ddc-i2c-bus = <&hdmi_ddc>; 63*4882a593Smuzhiyun nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 64*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun pinmux@70000014 { 69*4882a593Smuzhiyun pinctrl-names = "default"; 70*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun state_default: pinmux { 73*4882a593Smuzhiyun ata { 74*4882a593Smuzhiyun nvidia,pins = "ata"; 75*4882a593Smuzhiyun nvidia,function = "ide"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun atb { 78*4882a593Smuzhiyun nvidia,pins = "atb", "gma", "gme"; 79*4882a593Smuzhiyun nvidia,function = "sdio4"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun atc { 82*4882a593Smuzhiyun nvidia,pins = "atc"; 83*4882a593Smuzhiyun nvidia,function = "nand"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun atd { 86*4882a593Smuzhiyun nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", 87*4882a593Smuzhiyun "spia", "spib", "spic"; 88*4882a593Smuzhiyun nvidia,function = "gmi"; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun cdev1 { 91*4882a593Smuzhiyun nvidia,pins = "cdev1"; 92*4882a593Smuzhiyun nvidia,function = "plla_out"; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun cdev2 { 95*4882a593Smuzhiyun nvidia,pins = "cdev2"; 96*4882a593Smuzhiyun nvidia,function = "pllp_out4"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun crtp { 99*4882a593Smuzhiyun nvidia,pins = "crtp"; 100*4882a593Smuzhiyun nvidia,function = "crt"; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun csus { 103*4882a593Smuzhiyun nvidia,pins = "csus"; 104*4882a593Smuzhiyun nvidia,function = "vi_sensor_clk"; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun dap1 { 107*4882a593Smuzhiyun nvidia,pins = "dap1"; 108*4882a593Smuzhiyun nvidia,function = "dap1"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun dap2 { 111*4882a593Smuzhiyun nvidia,pins = "dap2"; 112*4882a593Smuzhiyun nvidia,function = "dap2"; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun dap3 { 115*4882a593Smuzhiyun nvidia,pins = "dap3"; 116*4882a593Smuzhiyun nvidia,function = "dap3"; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun dap4 { 119*4882a593Smuzhiyun nvidia,pins = "dap4"; 120*4882a593Smuzhiyun nvidia,function = "dap4"; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun ddc { 123*4882a593Smuzhiyun nvidia,pins = "ddc"; 124*4882a593Smuzhiyun nvidia,function = "i2c2"; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun dta { 127*4882a593Smuzhiyun nvidia,pins = "dta", "dtd"; 128*4882a593Smuzhiyun nvidia,function = "sdio2"; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun dtb { 131*4882a593Smuzhiyun nvidia,pins = "dtb", "dtc", "dte"; 132*4882a593Smuzhiyun nvidia,function = "rsvd1"; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun dtf { 135*4882a593Smuzhiyun nvidia,pins = "dtf"; 136*4882a593Smuzhiyun nvidia,function = "i2c3"; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun gmc { 139*4882a593Smuzhiyun nvidia,pins = "gmc"; 140*4882a593Smuzhiyun nvidia,function = "uartd"; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun gpu7 { 143*4882a593Smuzhiyun nvidia,pins = "gpu7"; 144*4882a593Smuzhiyun nvidia,function = "rtck"; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun gpv { 147*4882a593Smuzhiyun nvidia,pins = "gpv", "slxa", "slxk"; 148*4882a593Smuzhiyun nvidia,function = "pcie"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun hdint { 151*4882a593Smuzhiyun nvidia,pins = "hdint", "pta"; 152*4882a593Smuzhiyun nvidia,function = "hdmi"; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun i2cp { 155*4882a593Smuzhiyun nvidia,pins = "i2cp"; 156*4882a593Smuzhiyun nvidia,function = "i2cp"; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun irrx { 159*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx"; 160*4882a593Smuzhiyun nvidia,function = "uarta"; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun kbca { 163*4882a593Smuzhiyun nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 164*4882a593Smuzhiyun "kbce", "kbcf"; 165*4882a593Smuzhiyun nvidia,function = "kbc"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun lcsn { 168*4882a593Smuzhiyun nvidia,pins = "lcsn", "ld0", "ld1", "ld2", 169*4882a593Smuzhiyun "ld3", "ld4", "ld5", "ld6", "ld7", 170*4882a593Smuzhiyun "ld8", "ld9", "ld10", "ld11", "ld12", 171*4882a593Smuzhiyun "ld13", "ld14", "ld15", "ld16", "ld17", 172*4882a593Smuzhiyun "ldc", "ldi", "lhp0", "lhp1", "lhp2", 173*4882a593Smuzhiyun "lhs", "lm0", "lm1", "lpp", "lpw0", 174*4882a593Smuzhiyun "lpw1", "lpw2", "lsc0", "lsc1", "lsck", 175*4882a593Smuzhiyun "lsda", "lsdi", "lspi", "lvp0", "lvp1", 176*4882a593Smuzhiyun "lvs"; 177*4882a593Smuzhiyun nvidia,function = "displaya"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun owc { 180*4882a593Smuzhiyun nvidia,pins = "owc", "spdi", "spdo", "uac"; 181*4882a593Smuzhiyun nvidia,function = "rsvd2"; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun pmc { 184*4882a593Smuzhiyun nvidia,pins = "pmc"; 185*4882a593Smuzhiyun nvidia,function = "pwr_on"; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun rm { 188*4882a593Smuzhiyun nvidia,pins = "rm"; 189*4882a593Smuzhiyun nvidia,function = "i2c1"; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun sdb { 192*4882a593Smuzhiyun nvidia,pins = "sdb", "sdc", "sdd"; 193*4882a593Smuzhiyun nvidia,function = "pwm"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun sdio1 { 196*4882a593Smuzhiyun nvidia,pins = "sdio1"; 197*4882a593Smuzhiyun nvidia,function = "sdio1"; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun slxc { 200*4882a593Smuzhiyun nvidia,pins = "slxc", "slxd"; 201*4882a593Smuzhiyun nvidia,function = "spdif"; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun spid { 204*4882a593Smuzhiyun nvidia,pins = "spid", "spie", "spif"; 205*4882a593Smuzhiyun nvidia,function = "spi1"; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun spig { 208*4882a593Smuzhiyun nvidia,pins = "spig", "spih"; 209*4882a593Smuzhiyun nvidia,function = "spi2_alt"; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun uaa { 212*4882a593Smuzhiyun nvidia,pins = "uaa", "uab", "uda"; 213*4882a593Smuzhiyun nvidia,function = "ulpi"; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun uad { 216*4882a593Smuzhiyun nvidia,pins = "uad"; 217*4882a593Smuzhiyun nvidia,function = "irda"; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun uca { 220*4882a593Smuzhiyun nvidia,pins = "uca", "ucb"; 221*4882a593Smuzhiyun nvidia,function = "uartc"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun conf_ata { 224*4882a593Smuzhiyun nvidia,pins = "ata", "atb", "atc", "atd", "ate", 225*4882a593Smuzhiyun "cdev1", "cdev2", "dap1", "dtb", "gma", 226*4882a593Smuzhiyun "gmb", "gmc", "gmd", "gme", "gpu7", 227*4882a593Smuzhiyun "gpv", "i2cp", "pta", "rm", "slxa", 228*4882a593Smuzhiyun "slxk", "spia", "spib", "uac"; 229*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 230*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun conf_ck32 { 233*4882a593Smuzhiyun nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 234*4882a593Smuzhiyun "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 235*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun conf_csus { 238*4882a593Smuzhiyun nvidia,pins = "csus", "spid", "spif"; 239*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 240*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun conf_crtp { 243*4882a593Smuzhiyun nvidia,pins = "crtp", "dap2", "dap3", "dap4", 244*4882a593Smuzhiyun "dtc", "dte", "dtf", "gpu", "sdio1", 245*4882a593Smuzhiyun "slxc", "slxd", "spdi", "spdo", "spig", 246*4882a593Smuzhiyun "uda"; 247*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 248*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun conf_ddc { 251*4882a593Smuzhiyun nvidia,pins = "ddc", "dta", "dtd", "kbca", 252*4882a593Smuzhiyun "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 253*4882a593Smuzhiyun "sdc"; 254*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 255*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun conf_hdint { 258*4882a593Smuzhiyun nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 259*4882a593Smuzhiyun "lpw1", "lsc1", "lsck", "lsda", "lsdi", 260*4882a593Smuzhiyun "lvp0", "owc", "sdb"; 261*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun conf_irrx { 264*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx", "sdd", "spic", 265*4882a593Smuzhiyun "spie", "spih", "uaa", "uab", "uad", 266*4882a593Smuzhiyun "uca", "ucb"; 267*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 268*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun conf_lc { 271*4882a593Smuzhiyun nvidia,pins = "lc", "ls"; 272*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun conf_ld0 { 275*4882a593Smuzhiyun nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 276*4882a593Smuzhiyun "ld5", "ld6", "ld7", "ld8", "ld9", 277*4882a593Smuzhiyun "ld10", "ld11", "ld12", "ld13", "ld14", 278*4882a593Smuzhiyun "ld15", "ld16", "ld17", "ldi", "lhp0", 279*4882a593Smuzhiyun "lhp1", "lhp2", "lhs", "lm0", "lpp", 280*4882a593Smuzhiyun "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 281*4882a593Smuzhiyun "lvs", "pmc"; 282*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun conf_ld17_0 { 285*4882a593Smuzhiyun nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 286*4882a593Smuzhiyun "ld23_22"; 287*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun i2s@70002800 { 293*4882a593Smuzhiyun status = "okay"; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun serial@70006300 { 297*4882a593Smuzhiyun status = "okay"; 298*4882a593Smuzhiyun clock-frequency = < 216000000 >; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun pwm: pwm@7000a000 { 302*4882a593Smuzhiyun status = "okay"; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun i2c@7000c000 { 306*4882a593Smuzhiyun status = "okay"; 307*4882a593Smuzhiyun clock-frequency = <400000>; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun wm8903: wm8903@1a { 310*4882a593Smuzhiyun compatible = "wlf,wm8903"; 311*4882a593Smuzhiyun reg = <0x1a>; 312*4882a593Smuzhiyun interrupt-parent = <&gpio>; 313*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun gpio-controller; 316*4882a593Smuzhiyun #gpio-cells = <2>; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun micdet-cfg = <0>; 319*4882a593Smuzhiyun micdet-delay = <100>; 320*4882a593Smuzhiyun gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun nand-controller@70008000 { 325*4882a593Smuzhiyun nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; 326*4882a593Smuzhiyun nvidia,width = <8>; 327*4882a593Smuzhiyun nvidia,timing = <26 100 20 80 20 10 12 10 70>; 328*4882a593Smuzhiyun nand@0 { 329*4882a593Smuzhiyun reg = <0>; 330*4882a593Smuzhiyun compatible = "hynix,hy27uf4g2b", "nand-flash"; 331*4882a593Smuzhiyun }; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun hdmi_ddc: i2c@7000c400 { 335*4882a593Smuzhiyun status = "okay"; 336*4882a593Smuzhiyun clock-frequency = <100000>; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun i2c@7000c500 { 340*4882a593Smuzhiyun status = "okay"; 341*4882a593Smuzhiyun clock-frequency = <400000>; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun i2c@7000d000 { 345*4882a593Smuzhiyun status = "okay"; 346*4882a593Smuzhiyun clock-frequency = <400000>; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun pmic: tps6586x@34 { 349*4882a593Smuzhiyun compatible = "ti,tps6586x"; 350*4882a593Smuzhiyun reg = <0x34>; 351*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun ti,system-power-controller; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun #gpio-cells = <2>; 356*4882a593Smuzhiyun gpio-controller; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun sys-supply = <&vdd_5v0_reg>; 359*4882a593Smuzhiyun vin-sm0-supply = <&sys_reg>; 360*4882a593Smuzhiyun vin-sm1-supply = <&sys_reg>; 361*4882a593Smuzhiyun vin-sm2-supply = <&sys_reg>; 362*4882a593Smuzhiyun vinldo01-supply = <&sm2_reg>; 363*4882a593Smuzhiyun vinldo23-supply = <&sm2_reg>; 364*4882a593Smuzhiyun vinldo4-supply = <&sm2_reg>; 365*4882a593Smuzhiyun vinldo678-supply = <&sm2_reg>; 366*4882a593Smuzhiyun vinldo9-supply = <&sm2_reg>; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun regulators { 369*4882a593Smuzhiyun sys_reg: sys { 370*4882a593Smuzhiyun regulator-name = "vdd_sys"; 371*4882a593Smuzhiyun regulator-always-on; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun sm0 { 375*4882a593Smuzhiyun regulator-name = "vdd_sm0,vdd_core"; 376*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 377*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 378*4882a593Smuzhiyun regulator-always-on; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun sm1 { 382*4882a593Smuzhiyun regulator-name = "vdd_sm1,vdd_cpu"; 383*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 384*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 385*4882a593Smuzhiyun regulator-always-on; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun sm2_reg: sm2 { 389*4882a593Smuzhiyun regulator-name = "vdd_sm2,vin_ldo*"; 390*4882a593Smuzhiyun regulator-min-microvolt = <3700000>; 391*4882a593Smuzhiyun regulator-max-microvolt = <3700000>; 392*4882a593Smuzhiyun regulator-always-on; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun pci_clk_reg: ldo0 { 396*4882a593Smuzhiyun regulator-name = "vdd_ldo0,vddio_pex_clk"; 397*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 398*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun ldo1 { 402*4882a593Smuzhiyun regulator-name = "vdd_ldo1,avdd_pll*"; 403*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 404*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 405*4882a593Smuzhiyun regulator-always-on; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun ldo2 { 409*4882a593Smuzhiyun regulator-name = "vdd_ldo2,vdd_rtc"; 410*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 411*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun ldo3 { 415*4882a593Smuzhiyun regulator-name = "vdd_ldo3,avdd_usb*"; 416*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 417*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 418*4882a593Smuzhiyun regulator-always-on; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun ldo4 { 422*4882a593Smuzhiyun regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 423*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 424*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 425*4882a593Smuzhiyun regulator-always-on; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun ldo5 { 429*4882a593Smuzhiyun regulator-name = "vdd_ldo5,vcore_mmc"; 430*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 431*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 432*4882a593Smuzhiyun regulator-always-on; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun ldo6 { 436*4882a593Smuzhiyun regulator-name = "vdd_ldo6,avdd_vdac"; 437*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 438*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 439*4882a593Smuzhiyun }; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun hdmi_vdd_reg: ldo7 { 442*4882a593Smuzhiyun regulator-name = "vdd_ldo7,avdd_hdmi"; 443*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 444*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun hdmi_pll_reg: ldo8 { 448*4882a593Smuzhiyun regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 449*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 450*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun ldo9 { 454*4882a593Smuzhiyun regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 455*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 456*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 457*4882a593Smuzhiyun regulator-always-on; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun ldo_rtc { 461*4882a593Smuzhiyun regulator-name = "vdd_rtc_out,vdd_cell"; 462*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 463*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 464*4882a593Smuzhiyun regulator-always-on; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun }; 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun temperature-sensor@4c { 470*4882a593Smuzhiyun compatible = "adi,adt7461"; 471*4882a593Smuzhiyun reg = <0x4c>; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun kbc@7000e200 { 476*4882a593Smuzhiyun status = "okay"; 477*4882a593Smuzhiyun nvidia,debounce-delay-ms = <2>; 478*4882a593Smuzhiyun nvidia,repeat-delay-ms = <160>; 479*4882a593Smuzhiyun nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; 480*4882a593Smuzhiyun nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; 481*4882a593Smuzhiyun linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) 482*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x03, KEY_S) 483*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x04, KEY_A) 484*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x05, KEY_Z) 485*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x07, KEY_FN) 486*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x07, KEY_MENU) 487*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x06, KEY_LEFTALT) 488*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT) 489*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x00, KEY_5) 490*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x01, KEY_4) 491*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x02, KEY_R) 492*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x03, KEY_E) 493*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x04, KEY_F) 494*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x05, KEY_D) 495*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x06, KEY_X) 496*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x00, KEY_7) 497*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x01, KEY_6) 498*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x02, KEY_T) 499*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x03, KEY_H) 500*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x04, KEY_G) 501*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x05, KEY_V) 502*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x06, KEY_C) 503*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x07, KEY_SPACE) 504*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x00, KEY_9) 505*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x01, KEY_8) 506*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x02, KEY_U) 507*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x03, KEY_Y) 508*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x04, KEY_J) 509*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x05, KEY_N) 510*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x06, KEY_B) 511*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) 512*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x00, KEY_MINUS) 513*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x01, KEY_0) 514*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x02, KEY_O) 515*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x03, KEY_I) 516*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x04, KEY_L) 517*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x05, KEY_K) 518*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x06, KEY_COMMA) 519*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x07, KEY_M) 520*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x01, KEY_EQUAL) 521*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) 522*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x03, KEY_ENTER) 523*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x07, KEY_MENU) 524*4882a593Smuzhiyun MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT) 525*4882a593Smuzhiyun MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT) 526*4882a593Smuzhiyun MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL) 527*4882a593Smuzhiyun MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL) 528*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) 529*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x01, KEY_P) 530*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) 531*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) 532*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x04, KEY_SLASH) 533*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x05, KEY_DOT) 534*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x00, KEY_F10) 535*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x01, KEY_F9) 536*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) 537*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x03, KEY_3) 538*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x04, KEY_2) 539*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x05, KEY_UP) 540*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x06, KEY_PRINT) 541*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) 542*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x00, KEY_INSERT) 543*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x01, KEY_DELETE) 544*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) 545*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) 546*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) 547*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x06, KEY_DOWN) 548*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x07, KEY_LEFT) 549*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x00, KEY_F11) 550*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x01, KEY_F12) 551*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x02, KEY_F8) 552*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x03, KEY_Q) 553*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x04, KEY_F4) 554*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x05, KEY_F3) 555*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x06, KEY_1) 556*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x07, KEY_F7) 557*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x00, KEY_ESC) 558*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) 559*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x02, KEY_F5) 560*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x03, KEY_TAB) 561*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x04, KEY_F1) 562*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x05, KEY_F2) 563*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) 564*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x07, KEY_F6) 565*4882a593Smuzhiyun MATRIX_KEY(0x14, 0x00, KEY_KP7) 566*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x00, KEY_KP9) 567*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x01, KEY_KP8) 568*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x02, KEY_KP4) 569*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x04, KEY_KP1) 570*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) 571*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x02, KEY_KP6) 572*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x03, KEY_KP5) 573*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x04, KEY_KP3) 574*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x05, KEY_KP2) 575*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x07, KEY_KP0) 576*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) 577*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) 578*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) 579*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) 580*4882a593Smuzhiyun MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) 581*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x03, KEY_HOME) 582*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x04, KEY_END) 583*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP) 584*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) 585*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN) 586*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) 587*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) 588*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x02, KEY_MUTE) 589*4882a593Smuzhiyun MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>; 590*4882a593Smuzhiyun }; 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun pmc@7000e400 { 593*4882a593Smuzhiyun nvidia,invert-interrupt; 594*4882a593Smuzhiyun nvidia,suspend-mode = <1>; 595*4882a593Smuzhiyun nvidia,cpu-pwr-good-time = <5000>; 596*4882a593Smuzhiyun nvidia,cpu-pwr-off-time = <5000>; 597*4882a593Smuzhiyun nvidia,core-pwr-good-time = <3845 3845>; 598*4882a593Smuzhiyun nvidia,core-pwr-off-time = <3875>; 599*4882a593Smuzhiyun nvidia,sys-clock-req-active-high; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun pcie-controller@80003000 { 603*4882a593Smuzhiyun status = "okay"; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun avdd-pex-supply = <&pci_vdd_reg>; 606*4882a593Smuzhiyun vdd-pex-supply = <&pci_vdd_reg>; 607*4882a593Smuzhiyun avdd-pex-pll-supply = <&pci_vdd_reg>; 608*4882a593Smuzhiyun avdd-plle-supply = <&pci_vdd_reg>; 609*4882a593Smuzhiyun vddio-pex-clk-supply = <&pci_clk_reg>; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun pci@1,0 { 612*4882a593Smuzhiyun status = "okay"; 613*4882a593Smuzhiyun }; 614*4882a593Smuzhiyun 615*4882a593Smuzhiyun pci@2,0 { 616*4882a593Smuzhiyun status = "okay"; 617*4882a593Smuzhiyun }; 618*4882a593Smuzhiyun }; 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun usb@c5000000 { 621*4882a593Smuzhiyun status = "okay"; 622*4882a593Smuzhiyun }; 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun usb-phy@c5000000 { 625*4882a593Smuzhiyun status = "okay"; 626*4882a593Smuzhiyun }; 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun usb@c5004000 { 629*4882a593Smuzhiyun status = "okay"; 630*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 631*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 632*4882a593Smuzhiyun }; 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun usb-phy@c5004000 { 635*4882a593Smuzhiyun status = "okay"; 636*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 637*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 638*4882a593Smuzhiyun }; 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun usb@c5008000 { 641*4882a593Smuzhiyun status = "okay"; 642*4882a593Smuzhiyun }; 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun usb-phy@c5008000 { 645*4882a593Smuzhiyun status = "okay"; 646*4882a593Smuzhiyun }; 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun sdhci@c8000200 { 649*4882a593Smuzhiyun status = "okay"; 650*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 651*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 652*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; 653*4882a593Smuzhiyun bus-width = <4>; 654*4882a593Smuzhiyun }; 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun sdhci@c8000600 { 657*4882a593Smuzhiyun status = "okay"; 658*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; 659*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 660*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 661*4882a593Smuzhiyun bus-width = <8>; 662*4882a593Smuzhiyun }; 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun backlight: backlight { 665*4882a593Smuzhiyun compatible = "pwm-backlight"; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; 668*4882a593Smuzhiyun power-supply = <&vdd_bl_reg>; 669*4882a593Smuzhiyun pwms = <&pwm 0 5000000>; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 672*4882a593Smuzhiyun default-brightness-level = <6>; 673*4882a593Smuzhiyun }; 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun clocks { 676*4882a593Smuzhiyun compatible = "simple-bus"; 677*4882a593Smuzhiyun #address-cells = <1>; 678*4882a593Smuzhiyun #size-cells = <0>; 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun clk32k_in: clock@0 { 681*4882a593Smuzhiyun compatible = "fixed-clock"; 682*4882a593Smuzhiyun reg=<0>; 683*4882a593Smuzhiyun #clock-cells = <0>; 684*4882a593Smuzhiyun clock-frequency = <32768>; 685*4882a593Smuzhiyun }; 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun gpio-keys { 689*4882a593Smuzhiyun compatible = "gpio-keys"; 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun power { 692*4882a593Smuzhiyun label = "Power"; 693*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 694*4882a593Smuzhiyun linux,code = <KEY_POWER>; 695*4882a593Smuzhiyun gpio-key,wakeup; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun }; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun panel: panel { 700*4882a593Smuzhiyun compatible = "auo,b101aw03", "simple-panel"; 701*4882a593Smuzhiyun 702*4882a593Smuzhiyun power-supply = <&vdd_pnl_reg>; 703*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; 704*4882a593Smuzhiyun 705*4882a593Smuzhiyun backlight = <&backlight>; 706*4882a593Smuzhiyun }; 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun regulators { 709*4882a593Smuzhiyun compatible = "simple-bus"; 710*4882a593Smuzhiyun #address-cells = <1>; 711*4882a593Smuzhiyun #size-cells = <0>; 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun vdd_5v0_reg: regulator@0 { 714*4882a593Smuzhiyun compatible = "regulator-fixed"; 715*4882a593Smuzhiyun reg = <0>; 716*4882a593Smuzhiyun regulator-name = "vdd_5v0"; 717*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 718*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 719*4882a593Smuzhiyun regulator-always-on; 720*4882a593Smuzhiyun }; 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun regulator@1 { 723*4882a593Smuzhiyun compatible = "regulator-fixed"; 724*4882a593Smuzhiyun reg = <1>; 725*4882a593Smuzhiyun regulator-name = "vdd_1v5"; 726*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 727*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 728*4882a593Smuzhiyun gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 729*4882a593Smuzhiyun }; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun regulator@2 { 732*4882a593Smuzhiyun compatible = "regulator-fixed"; 733*4882a593Smuzhiyun reg = <2>; 734*4882a593Smuzhiyun regulator-name = "vdd_1v2"; 735*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 736*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 737*4882a593Smuzhiyun gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 738*4882a593Smuzhiyun enable-active-high; 739*4882a593Smuzhiyun }; 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun pci_vdd_reg: regulator@3 { 742*4882a593Smuzhiyun compatible = "regulator-fixed"; 743*4882a593Smuzhiyun reg = <3>; 744*4882a593Smuzhiyun regulator-name = "vdd_1v05"; 745*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 746*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 747*4882a593Smuzhiyun gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 748*4882a593Smuzhiyun enable-active-high; 749*4882a593Smuzhiyun }; 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun vdd_pnl_reg: regulator@4 { 752*4882a593Smuzhiyun compatible = "regulator-fixed"; 753*4882a593Smuzhiyun reg = <4>; 754*4882a593Smuzhiyun regulator-name = "vdd_pnl"; 755*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 756*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 757*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 758*4882a593Smuzhiyun enable-active-high; 759*4882a593Smuzhiyun }; 760*4882a593Smuzhiyun 761*4882a593Smuzhiyun vdd_bl_reg: regulator@5 { 762*4882a593Smuzhiyun compatible = "regulator-fixed"; 763*4882a593Smuzhiyun reg = <5>; 764*4882a593Smuzhiyun regulator-name = "vdd_bl"; 765*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 766*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 767*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; 768*4882a593Smuzhiyun enable-active-high; 769*4882a593Smuzhiyun }; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun vdd_5v0_hdmi: regulator@6 { 772*4882a593Smuzhiyun compatible = "regulator-fixed"; 773*4882a593Smuzhiyun reg = <6>; 774*4882a593Smuzhiyun regulator-name = "VDDIO_HDMI"; 775*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 776*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 777*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; 778*4882a593Smuzhiyun enable-active-high; 779*4882a593Smuzhiyun vin-supply = <&vdd_5v0_reg>; 780*4882a593Smuzhiyun }; 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun sound { 784*4882a593Smuzhiyun compatible = "nvidia,tegra-audio-wm8903-harmony", 785*4882a593Smuzhiyun "nvidia,tegra-audio-wm8903"; 786*4882a593Smuzhiyun nvidia,model = "NVIDIA Tegra Harmony"; 787*4882a593Smuzhiyun 788*4882a593Smuzhiyun nvidia,audio-routing = 789*4882a593Smuzhiyun "Headphone Jack", "HPOUTR", 790*4882a593Smuzhiyun "Headphone Jack", "HPOUTL", 791*4882a593Smuzhiyun "Int Spk", "ROP", 792*4882a593Smuzhiyun "Int Spk", "RON", 793*4882a593Smuzhiyun "Int Spk", "LOP", 794*4882a593Smuzhiyun "Int Spk", "LON", 795*4882a593Smuzhiyun "Mic Jack", "MICBIAS", 796*4882a593Smuzhiyun "IN1L", "Mic Jack"; 797*4882a593Smuzhiyun 798*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s1>; 799*4882a593Smuzhiyun nvidia,audio-codec = <&wm8903>; 800*4882a593Smuzhiyun 801*4882a593Smuzhiyun nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 802*4882a593Smuzhiyun nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 803*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 804*4882a593Smuzhiyun nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) 805*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 806*4882a593Smuzhiyun nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) 807*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 810*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 811*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_CDEV1>; 812*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 813*4882a593Smuzhiyun }; 814*4882a593Smuzhiyun}; 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun&uartd { 817*4882a593Smuzhiyun status = "okay"; 818*4882a593Smuzhiyun}; 819