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Searched refs:TSP_HW_CFG4_PVR_FLUSH (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c3619 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
3620 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
3647 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
3648 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
H A DregTSP.h586 …#define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_mi… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DregTSP.h586 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
H A DhalTSP.c1258 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH)); in HAL_TSP_PVR_WaitFlush()
1260 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH)); in HAL_TSP_PVR_WaitFlush()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DregTSP.h586 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
H A DhalTSP.c1259 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH)); in HAL_TSP_PVR_WaitFlush()
1261 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH)); in HAL_TSP_PVR_WaitFlush()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DregTSP.h580 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
H A DhalTSP.c1262 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH)); in HAL_TSP_PVR_WaitFlush()
1264 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH)); in HAL_TSP_PVR_WaitFlush()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h681 …#define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_mi… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DhalTSP.c4669 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
4670 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
4720 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
4721 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
H A DregTSP.h622 …#define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_mi… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DregTSP.h689 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010 // 1: str2mi_wadr <- str2mi_mi… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c4855 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
4856 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
4901 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
4902 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c5180 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
5181 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
5231 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
5232 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h689 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h678 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h709 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h714 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h714 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h721 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h721 …#define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_… macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h624 …#define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_mi… macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h662 …#define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_mi… macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h654 …#define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_mi… macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h654 …#define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_mi… macro

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