1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halPVR.c
20 // @brief PVR HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "halCHIP.h"
25 #include "regTSP.h"
26 #include "halTSP.h"
27 #include "drvSYS.h"
28 #include "MsOS.h"
29
30 #ifdef CONFIG_MSTAR_CLKM
31 #include "drvCLKM.h"
32 #endif
33
34
35 #define K6U02 (MDrv_SYS_GetChipRev() >= 0x1) // This feature/behavior is supported after K6 U02
36
37 #define TSP_MIU_SEL_BITS_LEN 2
38
39 //--------------------------------------------------------------------------------------------------
40 // Driver Compiler Option
41 //--------------------------------------------------------------------------------------------------
42
43
44 //--------------------------------------------------------------------------------------------------
45 // TSP Hardware Abstraction Layer
46 //--------------------------------------------------------------------------------------------------
47 MS_VIRT _u32RegBase = 0;
48
49 static REG_Ctrl* _RegCtrl = NULL; // TSP0 and TSP1
50 static REG_Ctrl2* _RegCtrl2 = NULL; // TSP3
51 static REG_Ctrl3* _RegCtrl3 = NULL; // TSP4
52 static REG_Ctrl4* _RegCtrl4 = NULL; // TSP6
53 static REG_Ctrl5* _RegCtrl5 = NULL; // TSP7
54 static REG_Ctrl6* _RegCtrl6 = NULL; // TSP8
55 static REG_Ctrl7* _RegCtrl7 = NULL; // TSP9
56 static REG_Ctrl8* _RegCtrl8 = NULL; // TSP10
57 static REG_Ctrl8_1* _RegCtrl8_1 = NULL; // TSP10
58
59
60
61 // @F_TODO These parameters need to be combined with global variables in Utopia 2.0
62 static MS_U32 _u32PidFltReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
63 static MS_U32 _u32PidDstReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
64 static MS_U32 _u32SecReg[(TSP_SECFLT_NUM * ((sizeof(REG_SecFlt) - sizeof(((REG_SecFlt*)0)->_x50))/sizeof(TSP32)))];
65
66 //-------------------------------------------------------------------------------------------------
67 // Local Structures
68 //-------------------------------------------------------------------------------------------------
69
70 typedef struct // structure for PVR Buffer
71 {
72 MS_BOOL bOverWrite; // True : means the PVR buffer has been written already
73 // False : means the PVR buffer has not been written yet
74 MS_U32 u32Start; // PVR buffer physical start address
75 MS_U32 u32End; // PVR buffer physical end address
76 MS_BOOL bPA2KSEG1_Mapping; // True : means PA2KSEG1 mapping success
77
78 }PVR_Buf;
79
80 static PVR_Buf _stPvrBuf[PVR_NUM];
81
82 //-------------------------------------------------------------------------------------------------
83 // Local Functions
84 //-------------------------------------------------------------------------------------------------
85 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value);
86
_delay(MS_U32 usec)87 static void _delay(MS_U32 usec)
88 {
89 MsOS_DelayTaskUs_Poll(usec);
90 }
91
REG32_R(REG32 * reg)92 static MS_U32 REG32_R(REG32 *reg)
93 {
94 MS_U32 value = 0;
95 value = (reg)->low;
96 value |= (reg)->high << 16;
97 return value;
98 }
99
100
REG16_R(REG16 * reg)101 static MS_U16 REG16_R(REG16 *reg)
102 {
103 MS_U16 value = 0;
104 value = (reg)->data;
105 return value;
106 }
107
108 static MS_BOOL _u32RegDump = 0;
109 static void _REG32_DUMP(REG32 * reg, MS_U32 value );
110 static void _REG16_DUMP(REG16 * reg, MS_U16 value);
111
112 #if 0
113 #define REG32_W(reg, value); { (reg)->low = ((value) & 0x0000FFFF); \
114 (reg)->high = ((value) >> 16);\
115 if(_u32RegDump)\
116 {printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n", (((MS_U32)(&(reg)->low) - _u32RegBase)>>(1+8)), ((((MS_U32)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1,(value) & 0x0000FFFF);\
117 printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n\n", (((MS_U32)(&(reg)->high) - _u32RegBase)>>(1+8)),((((MS_U32)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1, (value) >> 16);}}
118
119 #define REG16_W(reg, value); {(reg)->data = ((value) & 0x0000FFFF);\
120 if(_u32RegDump)\
121 {printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n\n", (((MS_U32)reg) - _u32RegBase)>>(1+8), ((((MS_U32)reg - _u32RegBase)>>1)&0xFF)>>1, (value) & 0x0000FFFF);}}
122 #endif
123 #define REG32_W(reg, value) { (reg)->low = ((value) & 0x0000FFFF); \
124 (reg)->high = ((value) >> 16);\
125 if(_u32RegDump){_REG32_DUMP(reg, value);}}
126
127 #define REG16_W(reg, value) {(reg)->data = ((value) & 0x0000FFFF);\
128 if(_u32RegDump){_REG16_DUMP(reg, value);}}
129
130
131 #define _AND_(flag, bit) ((flag) & (bit) )
132
133 #define _SET_(flag, bit) ((flag) | (bit) )
134 #define _CLR_(flag, bit) ((flag) & (~(bit)))
135
136 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value))
137 #define REG32_SET(reg, value) REG32_W(reg, _SET_(REG32_R(reg), value))
138 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value))
139 #define REG32_CLR(reg, value) REG32_W(reg, _CLR_(REG32_R(reg), value))
140
141 #define REG16_MSK_W(reg, mask, value) REG16_W((reg), _CLR_(REG16_R(reg), (mask)) | _AND_((value), (mask)))
142 #define REG32_MSK_W(reg, mask, value) REG32_W((reg), _CLR_(REG32_R(reg), (mask)) | _AND_((value), (mask)))
143
144 #define MIU_BUS (4)
145
146
147 //-------------------------------------------------------------------------------------------------
148 // Debug Message
149 //-------------------------------------------------------------------------------------------------
150 typedef enum
151 {
152 E_HAL_TSP_DBG_LEVEL_NONE, // no debug message shown
153 E_HAL_TSP_DBG_LEVEL_ERR, // only shows error message that can't be recover
154 E_HAL_TSP_DBG_LEVEL_WARN, // error case can be recover, like retry
155 E_HAL_TSP_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
156 E_HAL_TSP_DBG_LEVEL_INFO, // information for internal parameter
157 E_HAL_TSP_DBG_LEVEL_FUNC, // Function trace and input parameter trace
158 E_HAL_TSP_DBG_LEVEL_TRACE, // debug trace
159 } EN_HAL_TSP_DBGMSG_LEVEL;
160
161 typedef enum
162 {
163 E_HAL_TSP_DBG_MODEL_NONE, // @temporarily , need to refine
164 E_HAL_TSP_DBG_MODEL_ALL,
165 } EN_HAL_TSP_DBGMSG_MODEL;
166
167 #define HAL_TSP_DBGMSG(_level,_model,_f) do {if(_u32TSPDbgLevel >= (_level)&&((_u32TSPDbgModel&_model)!=0)) (_f);} while(0)
168 static MS_U32 _u32TSPDbgLevel = E_HAL_TSP_DBG_LEVEL_ERR;
169 static MS_U32 _u32TSPDbgModel = E_HAL_TSP_DBG_MODEL_ALL;
170
171
172 //--------------------------------------------------------------------------------------------------
173 // Implementation
174 //--------------------------------------------------------------------------------------------------
TSP32_IdrW(TSP32 * preg,MS_U32 value)175 void TSP32_IdrW(TSP32 *preg, MS_U32 value)
176 {
177 MS_U32 tempDump = _u32RegDump;
178 if(_u32RegDump)
179 {
180 //test_chip_top.write_ind32('h00221004, 32'hffffffff); //indirect .... (address,data)
181 _u32RegDump = 0;
182 printf("test_chip_top.write_ind32(\'h%08lx, 32\'h%08lx);\n", (long unsigned int)preg, (long unsigned int)value);
183 }
184 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
185 REG32_W(&_RegCtrl->Idr_Write, value);
186 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE);
187 _u32RegDump = tempDump;
188 }
189
TSP32_IdrR(TSP32 * preg)190 MS_U32 TSP32_IdrR(TSP32 *preg)
191 {
192 MS_U32 tempDump = _u32RegDump;
193 if(_u32RegDump)
194 {
195 _u32RegDump = 0;
196 }
197 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
198 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ);
199 _u32RegDump = tempDump;
200 return REG32_R(&_RegCtrl->Idr_Read);
201 }
202
HAL_TSP_SetBank(MS_VIRT u32BankAddr)203 void HAL_TSP_SetBank(MS_VIRT u32BankAddr)
204 {
205 _u32RegBase = u32BankAddr;
206 _RegCtrl = (REG_Ctrl*)(u32BankAddr + 0x2A00UL); // TSP0 0x1015, TSP1 0x1016
207 _RegCtrl2 = (REG_Ctrl2*)(u32BankAddr + 0xE0400UL); // TSP3 0x1702,
208 _RegCtrl3 = (REG_Ctrl3*)(u32BankAddr + 0xE0600UL); // TSP4 0x1703
209 _RegCtrl4 = (REG_Ctrl4*)(u32BankAddr + 0xC2000UL); // TSP6 0x1610
210 _RegCtrl5 = (REG_Ctrl5*)(u32BankAddr + 0xC2200UL); // TSP7 0x1611
211 _RegCtrl6 = (REG_Ctrl6*)(u32BankAddr + 0xC4E00UL); // TSP8 0x1627
212 _RegCtrl7 = (REG_Ctrl7*)(u32BankAddr + 0xE1800UL); // TSP9 0x170C
213 _RegCtrl8 = (REG_Ctrl8*)(u32BankAddr + 0xE1A00UL); // TSP10 0x170D
214 _RegCtrl8_1 = (REG_Ctrl8_1*)(u32BankAddr + 0xE1B00UL); // TSP10 0x170D , offset(16-bits): 0x40
215 }
216
HAL_TSP_RegDump(MS_BOOL bEnable)217 void HAL_TSP_RegDump(MS_BOOL bEnable)
218 {
219 _u32RegDump = bEnable;
220 }
221 #if 1
_REG32_DUMP(REG32 * reg,MS_U32 value)222 static void _REG32_DUMP(REG32* reg, MS_U32 value )
223 {
224 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7h06 ....reg ,16h400a ......
225 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7h06 ....reg ,16h400a ......
226 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
227 MS_U32 bank = ((MS_VIRT)(&(reg)->low) - _u32RegBase)>>(1+8);
228 MS_U32 addr_low = ((((MS_VIRT)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1;
229 MS_U32 addr_high = ((((MS_VIRT)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1;
230 MS_U32 val_low = (value) & 0x0000FFFF;
231 MS_U32 val_high = ((value) & 0xFFFF0000 )>>16;
232
233 if(bank == 0x15)
234 {
235 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
236 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
237 }
238 else if(bank == 0x16)
239 {
240 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
241 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
242 }
243 else if(bank == 0x38)
244 {
245 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
246 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
247 }
248 }
_REG16_DUMP(REG16 * reg,MS_U16 value)249 static void _REG16_DUMP(REG16* reg, MS_U16 value )
250 {
251 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7h06 ....reg ,16h400a ......
252 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7h06 ....reg ,16h400a ......
253 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
254 MS_U32 bank = ((MS_VIRT)(&(reg)) - _u32RegBase)>>(1+8);
255 MS_U32 addr = ((((MS_VIRT)(&(reg)) - _u32RegBase)>>1)&0xFF)>>1;
256 MS_U32 val = (value) & 0x0000FFFF;
257
258 if(bank == 0x15)
259 {
260 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
261 }
262 else if(bank == 0x16)
263 {
264 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
265 }
266 else if(bank == 0x38)
267 {
268 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
269 }
270 }
271 #endif
272
273 // [HW Issue]
274 // The K3 series PVR write pointer's return value is different from K1 series chip.
275 // For example, if PVR MIU alignment is 16 bytes. Write 32 bytes to PVR buffer from PVR start address 0.
276 // The 32 bytes data would be allocated to PVR buffer(address 0~31).
277 // And then we get the write pointer. The K3 series write pointer will return the value 16(W).
278 // The last MIU alignment address of the written data.
279 // The K1 series write pointer will return the value 32(W').
280 // The next MIU alignment address for the next writting.
281 // PVR write pointer value has 1 MIU alignment difference between K3 and K1 series.
282 // To SW, the K1 series write pointer's return value is more meaningful than K3 series.
283 // Now we use _Adjust_PVR_WritePtr function to make K3 series write pointer's return value consistent with K1 series.
284 // --------------------------------->
285 // S W W' E
286 // ######################
287 // +----------+----------+----------+
288 // 0 16 32
289 // ----------------------------------
290
_Adjust_PVR_WritePtr(MS_U32 u32Eng,MS_U32 u32WritePtr)291 static MS_U32 _Adjust_PVR_WritePtr(MS_U32 u32Eng, MS_U32 u32WritePtr)
292 {
293 if(_stPvrBuf[u32Eng].bPA2KSEG1_Mapping != TRUE)
294 {
295 return u32WritePtr;
296 }
297
298 if (_stPvrBuf[u32Eng].u32Start == 0)
299 {
300 return u32WritePtr;
301 }
302
303 if (!((E_TSP_PVR_PVRENG_START <= u32Eng) && (E_TSP_PVR_PVRENG_END > u32Eng))) // PVR Eng number check
304 {
305 return u32WritePtr;
306 }
307
308 if( _stPvrBuf[u32Eng].bOverWrite ) // If PVR buffer in OverWrite state
309 {
310 u32WritePtr = u32WritePtr + (1 << MIU_BUS);
311 }
312 else // If PVR buffer in non-OverWrite state
313 {
314 MsOS_ReadMemory();
315
316 if(*((MS_U64*)(MsOS_PA2KSEG1(_stPvrBuf[u32Eng].u32Start)))!= PVR_NON_OVERWRITE)
317 {
318 _stPvrBuf[u32Eng].bOverWrite = TRUE; // Set PVR buffer to OverWrite state
319 u32WritePtr = u32WritePtr + (1 << MIU_BUS);
320 }
321 }
322
323 if( u32WritePtr >= _stPvrBuf[u32Eng].u32End )
324 {
325 //reset write address
326 u32WritePtr = _stPvrBuf[u32Eng].u32Start;
327 }
328
329 return u32WritePtr;
330 }
331
HAL_TSP_HwPatch(void)332 void HAL_TSP_HwPatch(void)
333 {
334 //For sram
335 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE);
336 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION);
337
338 // @F_TODO check these setting with Stephen
339 // TSP_HW_CFG4_WSTAT_CH_EN <--this is bit disable HW sync section buf id with section filter id
340 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WSTAT_CH_EN);
341
342 // Bad initial value of TSP_CTRL1
343 // Suppose Standby mode for TSP should NOT be enabled.
344 // Enabling TSP standby mode cause TSP section registers (SRAM in AEON) malfunction.
345 // Disable it by SW at this stage.
346 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY);
347
348 //enable PVR record to bypass header
349 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2);
350 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC);
351 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC);
352
353 // load lpcr1 for all pvr engines, HW default value may be wrong
354 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
355 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
356 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
357 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
358
359 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
360
361 //Disable TSP_RM_OVF_GLITCH to fix that section A would occur overflow when section B occured overflow at first.
362 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN*/);
363
364 //Disable all live pathes block mechanism
365 REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_VQTX3_BLOCK_DIS*/);
366 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH);
367
368 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode
369
370 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
371
372 //record null packets for record-all case
373 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD | TSP_REC_NULL);
374 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP);
375
376 //Disable pvr1 & pvr2 block mechanism
377 //DisableAV FIFO block mechanism for live path
378 //REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN|TSP_PVR1_BLOCK_DIS|TSP_PVR2_BLOCK_DIS|TSP_V_BLOCK_DIS|TSP_A_BLOCK_DIS|TSP_AD_BLOCK_DIS); // by angie
379
380 // Serial mode config
381 REG16_SET(&_RegCtrl->reg15b8, TSP_SERIAL_EXT_SYNC_1T);
382 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT);
383 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_VALID_FALLING_DETECT)
384
385 // Internal Sync Patch
386 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T);
387
388 // Chip after Kirin will lost data when byte timer enable and delay set to 0 setting this bit to fix this issue
389 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN);
390
391 // Fix load fw secure issue (dma_start = 1 , polling dma_done , dma_start = 0)
392 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW);
393
394 // Fix pass_pkt_timestamp will hang issue
395 REG16_SET(&_RegCtrl6->CFG6_60, TSP_INIT_TIMESTAMP_RESTART_EN);
396
397 // Merge stream through FIQ ECO config
398 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_TS_SYNC_OUT_DELAY);
399 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_TS_SYNC_OUT_REVERSE_BLOCK);
400
401 // Fix filter null packet
402 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_FIX_FILTER_NULL_PKT);
403
404 // Fixed miu_req & miu_last
405 REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_VQ_MIU_REG_FLUSH);
406
407 // File/Live in 130 bytes stream will reference
408 REG16_SET(&_RegCtrl3->CFG3_18, CFG3_18_HD_0000_TO_SECTION_RVU | CFG3_18_HD_0000_TO_SECTION_DIRECTV);
409
410
411 // Fix miu arbiter last_done_z
412 if(K6U02)
413 {
414 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_MIU_FIXED_LAST_DONE_Z_ABT_ALL);
415 REG16_SET(&_RegCtrl2->CFG_10, CFG_10_MIU_CHECK_MI2RDY_ABT_ALL);
416 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_OR_WRITE_FIX_FOR_NEW_MIU_ARBITER_DISABLE);
417 }
418 }
419
420 // ------------ initial config ------------
421 // Sync Byte: 0x47 , 0x48 .... , 0x4e
422 // Source id : 0 , 1 , ... , 7
423 // User can use "HAL_TSP_PktConverter_SetSyncByte()" to change Sync Byte configuration
424 // , and use "HAL_TSP_PktConverter_SetSrcId()" to change Source id configuration
HAL_TSP_PktConverter_Init(void)425 void HAL_TSP_PktConverter_Init(void)
426 {
427 MS_U8 u8Path, u8Idx;
428 MS_U8 u8SyncByte, u8SrcId;
429
430 for(u8Path = 0; u8Path < TSP_TSIF_NUM; ++u8Path)
431 {
432 HAL_TSP_PktConverter_ForceSync(u8Path,TRUE);//default: FALSE
433 HAL_TSP_PktConverter_SrcIdFlt(u8Path, TRUE); // default: FALSE
434 u8SyncByte = 0x47;
435 u8SrcId = 0;
436
437 for(u8Idx = 0; u8Idx < TSP_MERGESTREAM_NUM; ++u8Idx,++u8SyncByte,++u8SrcId)
438 {
439 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Idx, &u8SyncByte, TRUE);
440 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Idx, &u8SrcId, TRUE);
441 }
442 }
443
444 }
445
446
HAL_TSP_Reset(MS_BOOL bEn)447 void HAL_TSP_Reset(MS_BOOL bEn)
448 {
449 //MS_U16 reg;
450
451 if (bEn)
452 {
453 #if 0
454
455 // WB DMA source won't be reset by SW_RST bit so we use HWPATCH to make it's source to default
456 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);
457 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
458
459 #endif
460 // reset CMDQ for tsif 0~3
461 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
462 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
463 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
464 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
465 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
466 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
467 }
468 else
469 {
470 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
471
472 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
473 // set CMDQ for tsif 0~3
474 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
475 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
476 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
477 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
478 }
479 }
480
481
HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn)482 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn)
483 {
484 switch(tsIf)
485 {
486 case 0: if(bEn)
487 {
488 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET);
489 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0);
490 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0);
491 }
492 else
493 {
494 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0);
495 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0);
496 REG16_CLR(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET);
497 }
498 break;
499 case 1: if(bEn)
500 {
501 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1);
502 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1);
503 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1);
504 }
505 else
506 {
507 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1);
508 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1);
509 REG16_CLR(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1);
510 }
511 break;
512 case 2: if(bEn)
513 {
514 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2);
515 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2);
516 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2);
517 }
518 else
519 {
520 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2);
521 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2);
522 REG16_CLR(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2);
523 }
524 break;
525 case 3: if(bEn)
526 {
527 REG16_SET(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3);
528 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3);
529 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3);
530 }
531 else
532 {
533 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3);
534 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3);
535 REG16_CLR(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3);
536 }
537 break;
538 default: break;
539 }
540 }
541
HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType,MS_U8 u8Index,ST_TSP_HAL_CLK_STATUS * pstClkStatus)542 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus)
543 {
544 switch(eClkType)
545 {
546 case E_TSP_HAL_TSP_CLK:
547 pstClkStatus->bEnable = !(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_DISABLE);
548 pstClkStatus->bInvert = !!(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_INVERT);
549 pstClkStatus->u8ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_CLK_MASK) >> REG_CLKGEN0_TSP_SRC_SHIFT;
550 break;
551 default:
552 return FALSE;
553 }
554
555 return TRUE;
556 }
557
558
HAL_TSP_Power(MS_BOOL bEn)559 void HAL_TSP_Power(MS_BOOL bEn)
560 {
561 if(bEn)
562 {
563 #ifdef CONFIG_MSTAR_CLKM
564
565 MS_S32 s32Handle;
566
567 // Enable TSP Clk
568 s32Handle = Drv_Clkm_Get_Handle("g_clk_tsp");
569 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TSP_FAST");
570 // Enable STC1,2 Clk
571 // STC0
572 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc0");
573 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STC0_BUF");
574 // STC1
575 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc1");
576 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STC0_BUF");
577 // Stamp
578 s32Handle = Drv_Clkm_Get_Handle("g_clk_stamp");
579 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STAMP_NORMAL");
580 // Parser
581 s32Handle = Drv_Clkm_Get_Handle("g_clk_parser");
582 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_PARSER_NORMAL");
583 // Enable TSIF => Disable TSIF
584 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
585 //TS0
586 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
587 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
588 //TS1
589 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
590 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
591 //TS2
592 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
593 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
594 //TS3
595 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
596 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
597
598 //TSO0
599 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
600 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TSOIN0_PAD0");
601
602 #else
603
604 // Enable TSP Clk
605 TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & ~REG_CLKGEN0_TSP_CLK_MASK)
606 | (REG_CLKGEN0_TSP_SRC_192MHZ << REG_CLKGEN0_TSP_SRC_SHIFT);
607
608 // Enable STC 0,1,2,3 Clk
609 // STC0
610 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) & ~REG_CLKGEN0_STC0_MASK)
611 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT));
612 // STC1
613 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) & ~REG_CLKGEN0_STC1_MASK)
614 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT));
615 // STC2
616 TSP_CLKGEN2_REG(REG_CLKGEN2_STC2_CLK) = (TSP_CLKGEN2_REG(REG_CLKGEN2_STC2_CLK) & ~REG_CLKGEN2_STC2_MASK)
617 | (REG_CLKGEN2_STC_SRC_SYNTH << (REG_CLKGEN2_STC_SRC_SHIFT+REG_CLKGEN2_STC2_SHIFT));
618 // STC3
619 TSP_CLKGEN2_REG(REG_CLKGEN2_STC3_CLK) = (TSP_CLKGEN2_REG(REG_CLKGEN2_STC3_CLK) & ~REG_CLKGEN2_STC3_MASK)
620 | (REG_CLKGEN2_STC_SRC_SYNTH << (REG_CLKGEN2_STC_SRC_SHIFT+REG_CLKGEN2_STC3_SHIFT));
621
622 // Stamp
623 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) & ~REG_CLKGEN0_STAMP_MASK);
624
625 // Parser
626 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) & ~REG_CLKGEN0_PARSER_MASK);
627
628 // Enable TSIF => Disable TSIF
629 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
630 //TS0
631 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK);
632
633 //TS1
634 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS1_SHIFT));
635
636 //TS2
637 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS2_SHIFT));
638
639 //TS3
640 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS3_SHIFT));
641
642 //TSO0
643 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) & ~REG_CLKGEN0_TS_MASK);
644
645 #endif
646
647 // TSP Boot clk sel
648 TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) = (TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) & ~REG_TOP_TSP_BOOT_CLK_SEL_MASK) | REG_TOP_TSP_BOOT_CLK_SEL_TSP;
649
650 // TSP SRAM sel
651 TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) = TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) | REG_MMFI_TSP_SEL_SRAM_EN;
652
653 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION);
654
655 // Disable MCM
656 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP
657
658 }
659 else
660 {
661 // Enable MCM
662 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP
663
664 #ifdef CONFIG_MSTAR_CLKM
665
666 MS_S32 s32Handle;
667
668 // Disable TSP Clk
669 // [2016.10.14] Because AESDMA share clk with TSP. We can't disable TSP clk.
670 // s32Handle = Drv_Clkm_Get_Handle("g_clk_tsp");
671 // Drv_Clkm_Clk_Gate_Disable(s32Handle);
672
673 // Disable STC Clk
674 //STC0
675 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc0");
676 Drv_Clkm_Clk_Gate_Disable(s32Handle);
677 //STC0
678 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc1");
679 Drv_Clkm_Clk_Gate_Disable(s32Handle);
680 // Stamp
681 s32Handle = Drv_Clkm_Get_Handle("g_clk_stamp");
682 Drv_Clkm_Clk_Gate_Disable(s32Handle);
683 // Parser
684 s32Handle = Drv_Clkm_Get_Handle("g_clk_parser");
685 Drv_Clkm_Clk_Gate_Disable(s32Handle);
686 //TS0
687 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
688 Drv_Clkm_Clk_Gate_Disable(s32Handle);
689 //TS1
690 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
691 Drv_Clkm_Clk_Gate_Disable(s32Handle);
692 //TS2
693 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
694 Drv_Clkm_Clk_Gate_Disable(s32Handle);
695 //TS3
696 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
697 Drv_Clkm_Clk_Gate_Disable(s32Handle);
698
699 //TSO0
700 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
701 Drv_Clkm_Clk_Gate_Disable(s32Handle);
702
703 #else
704 // Disable TSP Clk
705 // [2016.10.11] Because AESDMA share clk with TSP. We can't disable TSP clk.
706 // TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK),(REG_CLKGEN0_TSP_DISABLE << REG_CLKGEN0_TSP_SHIFT));
707
708 // Disable STC Clk
709 //STC0
710 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC0_SHIFT));
711 //STC1
712 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC1_SHIFT));
713 //STC2
714 TSP_CLKGEN2_REG(REG_CLKGEN2_STC2_CLK) = _SET_(TSP_CLKGEN2_REG(REG_CLKGEN2_STC2_CLK),(REG_CLKGEN2_STC_DISABLE << REG_CLKGEN2_STC2_SHIFT));
715 //STC3
716 TSP_CLKGEN2_REG(REG_CLKGEN2_STC3_CLK) = _SET_(TSP_CLKGEN2_REG(REG_CLKGEN2_STC3_CLK),(REG_CLKGEN2_STC_DISABLE << REG_CLKGEN2_STC3_SHIFT));
717
718 // Stamp
719 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK),(REG_CLKGEN0_STAMP_DISABLE << REG_CLKGEN0_STAMP_SHIFT));
720
721 // Parser
722 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK),(REG_CLKGEN0_PARSER_DISABLE << REG_CLKGEN0_PARSER_SHIFT));
723
724 // Disable TSIF clk
725 //TS0
726 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS0_SHIFT));
727 //TS1
728 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS1_SHIFT));
729 //TS2
730 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS2_SHIFT));
731 //TS3
732 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS3_SHIFT));
733
734 //TSO0
735 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TSO0_SHIFT));
736
737 #endif
738
739 }
740 }
741
HAL_TSP_CPU(MS_BOOL bEn)742 void HAL_TSP_CPU(MS_BOOL bEn)
743 {
744 if (bEn)
745 {
746 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
747 }
748 else
749 {
750 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
751 }
752 }
HAL_TSP_ResetCPU(MS_BOOL bReset)753 void HAL_TSP_ResetCPU(MS_BOOL bReset)
754 {
755 // @NOTE TRUE for stop cpu clock
756 if (bReset)
757 {
758 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
759 }
760 else
761 {
762 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
763 }
764 }
765
766
HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr,MS_U32 u32FwSize)767 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize)
768 {
769
770 #define _TSP_QMEM_I_MASK 0xffffc000 //code: 0x2000, data: 0x1000, total: 0x3000
771 #define _TSP_QMEM_I_ADDR_HIT 0x00000000
772 #define _TSP_QMEM_I_ADDR_MISS 0xffffffff
773 #define _TSP_QMEM_D_MASK 0xffffc000
774 #define _TSP_QMEM_D_ADDR_HIT 0x00000000
775 #define _TSP_QMEM_D_ADDR_MISS 0xffffffff
776 #define _TSP_QMEM_SIZE 0x1000 // 16K bytes, 32bit aligment //0x4000 this is 4 byte address
777
778 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit
779
780 MS_U32 u32DnldCtrl = 0;
781 MS_U32 u32DnldCtrl1 = 0;
782
783 // Check MIU select
784 MS_U8 u8MiuSel = 0;
785 MS_PHY phyMiuOffsetFWBuf = 0;
786 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFWBuf, u32FwPhyAddr);
787 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN0_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN0_SHIFT) & REG_MIU_SEL_FILEIN0_MASK));
788
789 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT;
790 u32DnldCtrl1 = u32DnldCtrl >> 16;
791
792 REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register
793 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1);
794 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE);
795 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
796 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START);
797
798 //@TODO temprarily comment because of Secure Protect
799 #if 1
800 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE))
801 {
802 }
803 #endif
804
805
806 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
807
808 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK);
809 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT);
810 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK);
811 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT);
812
813 #undef _TSP_QMEM_I_MASK
814 #undef _TSP_QMEM_I_ADDR_HIT
815 #undef _TSP_QMEM_I_ADDR_MISS
816 #undef _TSP_QMEM_D_MASK
817 #undef _TSP_QMEM_D_ADDR_HIT
818 #undef _TSP_QMEM_D_ADDR_MISS
819 #undef _TSP_QMEM_SIZE
820
821 return TRUE;
822 }
823
HAL_TSP_RestoreFltState(void)824 void HAL_TSP_RestoreFltState(void)
825 {
826 MS_U32 u32Size;
827 TSP32 * pRegEnd;
828 TSP32 * pReg;
829 int i, j;
830
831 for (i = 0; i < TSP_PIDFLT_NUM; i++)
832 {
833 TSP32_IdrW(&(_REGPid0->Flt[i]), _u32PidFltReg[i]);
834 TSP32_IdrW(&(_REGPid1->Flt[i]), _u32PidDstReg[i]);
835 }
836
837 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x50))/sizeof(TSP32);
838
839 for (i = 0; i < TSP_SECFLT_NUM; i++)
840 {
841 pReg = (TSP32*)&(_REGSec->Flt[i]);
842 pRegEnd = pReg + u32Size;
843 j = 0;
844 for ( ; pReg < pRegEnd; pReg++)
845 {
846 TSP32_IdrW(pReg, _u32SecReg[i*u32Size+j]);
847 j++;
848 }
849 }
850
851 }
852
HAL_TSP_PktBuf_Reset(MS_U32 pktDmxId,MS_BOOL bEn)853 void HAL_TSP_PktBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn)
854 {
855 if(bEn)
856 {
857 switch(pktDmxId)
858 {
859 case 0:
860 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0);
861 break;
862 case 1:
863 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1);
864 break;
865 case 2:
866 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2);
867 break;
868 case 3:
869 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3);
870 break;
871 default:
872 break;
873 }
874 }
875 else
876 {
877 switch(pktDmxId)
878 {
879 case 0:
880 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0);
881 break;
882 case 1:
883 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1);
884 break;
885 case 2:
886 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2);
887 break;
888 case 3:
889 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3);
890 break;
891 default:
892 break;
893 }
894 }
895 }
896
HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId,MS_BOOL bEn)897 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn)
898 {
899 if(bEn)
900 {
901 switch(pktDmxId)
902 {
903 case 0:
904 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0);
905 break;
906 case 1:
907 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1);
908 break;
909 case 2:
910 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2);
911 break;
912 case 3:
913 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3);
914 break;
915 default:
916 break;
917 }
918 }
919 else
920 {
921 switch(pktDmxId)
922 {
923 case 0:
924 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0);
925 break;
926 case 1:
927 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1);
928 break;
929 case 2:
930 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2);
931 break;
932 case 3:
933 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3);
934 break;
935 default:
936 break;
937 }
938 }
939 }
940
HAL_TSP_SetTSIF(MS_U16 u16TSIF,TSP_TSIF_CFG u16Cfg,MS_BOOL bFileIn)941 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn)
942 {
943 if(bFileIn)
944 {
945 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, TRUE); // this returns true only we don't check the return value
946 HAL_TSP_TSIF_LiveEn(u16TSIF, FALSE); // this returns true only we don't check the return value
947 }
948 else
949 {
950 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, FALSE);
951 HAL_TSP_TSIF_LiveEn(u16TSIF, TRUE);
952 }
953
954 if(bFileIn != TRUE)
955 {
956 HAL_TSP_TSIF_BitSwap(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_BITSWAP)?TRUE:FALSE));
957 HAL_TSP_TSIF_ExtSync(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_EXTSYNC)?TRUE:FALSE));
958 HAL_TSP_TSIF_Parl (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_PARA )?TRUE:FALSE));
959 HAL_TSP_TSIF_3Wire (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_3WIRE )?TRUE:FALSE));
960 }
961
962 return TRUE;
963 }
964
HAL_TSP_TSIF_LiveEn(MS_U32 tsIf,MS_BOOL bEnable)965 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable)
966 {
967 if(bEnable)
968 {
969 switch(tsIf)
970 {
971 case 0:
972 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE);
973 break;
974 case 1:
975 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE);
976 break;
977 case 2:
978 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN);
979 break;
980 case 3:
981 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN);
982 break;
983 default:
984 return FALSE;
985 }
986 }
987 else
988 {
989 switch(tsIf)
990 {
991 case 0:
992 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE);
993 break;
994 case 1:
995 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE);
996 break;
997 case 2:
998 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN);
999 break;
1000 case 3:
1001 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN);
1002 break;
1003 default:
1004 return FALSE;
1005 }
1006 }
1007
1008 return TRUE;
1009 }
1010
HAL_TSP_TSIF_SelPad(MS_U32 tsIf,TSP_TS_PAD eTSPad)1011 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad) // @FIXME modify this parameter to enum plz
1012 {
1013 MS_U32 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
1014 MS_U32 pad_src = REG_TOP_TS_SRC_EXT0;
1015 #ifdef CONFIG_MSTAR_CLKM
1016 MS_S32 handle;
1017 MS_U8 u8NameIdx = 0;
1018 char* u8ClkSrcNames[] =
1019 {
1020 "CLK_TS0_PAD0",
1021 "CLK_TS0_PAD1",
1022 "CLK_TS0_PAD2",
1023 "CLK_TS0_PAD3",
1024 "CLK_TS0_PAD4",
1025 "CLK_TS0_PAD5",
1026 "CLK_TS0_PAD6",
1027 "CLK_TS0_PADTSO"
1028 "CLK_TS0_PADTSIO"
1029 };
1030 #endif
1031
1032 //@NOTE
1033 //EX3~6 are serial mode and ts2_padmax_mode must be 2 or 3.
1034
1035
1036 switch (eTSPad)
1037 {
1038 default:
1039 case E_TSP_TS_PAD_EXT0:
1040 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
1041 pad_src = REG_TOP_TS_SRC_EXT0;
1042 break;
1043 case E_TSP_TS_PAD_EXT1:
1044 clk_src = REG_CLKGEN0_TS_SRC_EXT1;
1045 pad_src = REG_TOP_TS_SRC_EXT1;
1046 break;
1047 case E_TSP_TS_PAD_EXT2:
1048 clk_src = REG_CLKGEN0_TS_SRC_EXT2;
1049 pad_src = REG_TOP_TS_SRC_EXT2;
1050 break;
1051 case E_TSP_TS_PAD_EXT3:
1052 clk_src = REG_CLKGEN0_TS_SRC_EXT3;
1053 pad_src = REG_TOP_TS_SRC_EXT3;
1054 break;
1055 case E_TSP_TS_PAD_EXT4:
1056 clk_src = REG_CLKGEN0_TS_SRC_EXT4;
1057 pad_src = REG_TOP_TS_SRC_EXT4;
1058 break;
1059 case E_TSP_TS_PAD_EXT5:
1060 clk_src = REG_CLKGEN0_TS_SRC_EXT5;
1061 pad_src = REG_TOP_TS_SRC_EXT5;
1062 break;
1063 case E_TSP_TS_PAD_EXT6:
1064 clk_src = REG_CLKGEN0_TS_SRC_EXT6;
1065 pad_src = REG_TOP_TS_SRC_EXT6;
1066 break;
1067 case E_TSP_TS_PAD_TSOUT0:
1068 clk_src = REG_CLKGEN0_TS_SRC_TSO0;
1069 pad_src = REG_TOP_TS_SRC_TSO0;
1070 break;
1071 case E_TSP_TS_PAD_TSIOOUT0:
1072 clk_src = REG_CLKGEN0_TS_SRC_TSIO0;
1073 pad_src = REG_TOP_TS_SRC_TSIO0;
1074 break;
1075 case E_TSP_TS_PAD_INTER0:
1076 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
1077 pad_src = REG_TOP_TS_SRC_EXT0;
1078 printf("[%s][%d]Warning KANO not support Internal Demod\n",__FUNCTION__,__LINE__);
1079 break;
1080 }
1081
1082 #ifdef CONFIG_MSTAR_CLKM
1083 switch(clk_src)
1084 {
1085 case REG_CLKGEN0_TS_SRC_EXT0:
1086 u8NameIdx = 0;
1087 break;
1088 case REG_CLKGEN0_TS_SRC_EXT1:
1089 u8NameIdx = 1;
1090 break;
1091 case REG_CLKGEN0_TS_SRC_EXT2:
1092 u8NameIdx = 2;
1093 break;
1094 case REG_CLKGEN0_TS_SRC_EXT3:
1095 u8NameIdx = 3;
1096 break;
1097 case REG_CLKGEN0_TS_SRC_EXT4:
1098 u8NameIdx = 4;
1099 break;
1100 case REG_CLKGEN0_TS_SRC_EXT5:
1101 u8NameIdx = 5;
1102 break;
1103 case REG_CLKGEN0_TS_SRC_EXT6:
1104 u8NameIdx = 6;
1105 break;
1106 case REG_CLKGEN0_TS_SRC_TSO0:
1107 u8NameIdx = 7;
1108 break;
1109 case REG_CLKGEN0_TS_SRC_TSIO0:
1110 u8NameIdx = 8;
1111 break;
1112 default:
1113 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1114 u8NameIdx = 0;
1115 break;
1116 }
1117 #endif
1118
1119 //@FIXME use enum instead of constant
1120 switch (tsIf)
1121 {
1122 case 0:
1123 TSP_TOP_REG(REG_TOP_TS0_MUX) = (TSP_TOP_REG(REG_TOP_TS0_MUX) & ~REG_TOP_TS_SRC_MASK) | (pad_src<<REG_TOP_TS0_SHIFT);
1124
1125 #ifdef CONFIG_MSTAR_CLKM
1126 handle = Drv_Clkm_Get_Handle("g_clk_ts");
1127 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1128 #else
1129 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK) | (clk_src<<(REG_CLKGEN0_TS0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1130 #endif
1131 break;
1132 case 1:
1133 TSP_TOP_REG(REG_TOP_TS1_MUX) = (TSP_TOP_REG(REG_TOP_TS1_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS1_SHIFT))
1134 | (pad_src<<REG_TOP_TS1_SHIFT);
1135 #ifdef CONFIG_MSTAR_CLKM
1136 handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1137 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1138 #else
1139 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT))
1140 | (clk_src<<(REG_CLKGEN0_TS1_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1141 #endif
1142 break;
1143 case 2:
1144 TSP_TOP_REG(REG_TOP_TS2_MUX) = (TSP_TOP_REG(REG_TOP_TS2_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS2_SHIFT))
1145 | (pad_src<<REG_TOP_TS2_SHIFT);
1146 #ifdef CONFIG_MSTAR_CLKM
1147 handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1148 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1149 #else
1150 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT))
1151 | (clk_src<<(REG_CLKGEN0_TS2_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1152 #endif
1153 break;
1154 case 3:
1155 TSP_TOP_REG(REG_TOP_TS3_MUX) = (TSP_TOP_REG(REG_TOP_TS3_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS3_SHIFT))
1156 | (pad_src<<REG_TOP_TS3_SHIFT);
1157 #ifdef CONFIG_MSTAR_CLKM
1158 handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1159 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1160 #else
1161 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT))
1162 | (clk_src<<(REG_CLKGEN0_TS3_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1163 #endif
1164 break;
1165
1166 default:
1167 return FALSE;
1168 }
1169 return TRUE;
1170 }
1171
_HAL_TSO_SetPad1OutMux(MS_BOOL bSet)1172 static void _HAL_TSO_SetPad1OutMux(MS_BOOL bSet)
1173 {
1174 if(bSet)
1175 {
1176 TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) = TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) & ~(REG_TOP_TS1MODE_MASK << REG_TOP_TS1MODE_SHIFT);
1177 }
1178 else
1179 {
1180 TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) = ((TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) & ~(REG_TOP_TS1MODE_MASK << REG_TOP_TS1MODE_SHIFT))
1181 | (REG_TOP_TS1MODE_INPUT << REG_TOP_TS1MODE_SHIFT));
1182 }
1183 }
1184
HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)1185 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)
1186 {
1187 _HAL_TSO_SetPad1OutMux(bSet);
1188 }
1189
HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad,TSP_TS_PAD_MUX_MODE eOutPadMode,TSP_TS_PAD eInPad,TSP_TS_PAD_MUX_MODE eInPadMode,MS_BOOL bEnable)1190 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable)
1191 {
1192 MS_U16 u16Temp = 0;
1193
1194 switch(eOutPad) // output pad
1195 {
1196 case E_TSP_TS_PAD_EXT1: // TS_pad #1
1197 if(eInPad == E_TSP_TS_PAD_EXT1) // output pad == input pad ?
1198 {
1199 return FALSE;
1200 }
1201
1202 _HAL_TSO_SetPad1OutMux(bEnable); // set pad mode (input or output)
1203
1204 switch(eOutPadMode) // set pad output mode
1205 {
1206 case E_TSP_TS_PAD_MUX_TSO:
1207 // input from TSO
1208 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT))
1209 | (REG_TOP_TS_OUT_MODE_TSO << REG_TOP_TS_OUT_MODE_SHIFT);
1210 break;
1211 case E_TSP_TS_PAD_MUX_S2P:
1212 // input from S2P
1213 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT))
1214 | (REG_TOP_TS_OUT_MODE_S2P << REG_TOP_TS_OUT_MODE_SHIFT);
1215
1216 u16Temp = REG_TSO_TSP_S2P_EN | REG_TSO_TSP_S2P_TS_SIN_C0 | REG_TSO_TSP_S2P_TS_SIN_C1; // S2P enable bit , serial bit count setting
1217 if(eInPadMode == E_TSP_TS_PAD_MUX_PARALLEL)
1218 {
1219 u16Temp |= REG_TSO_TSP_BYPASS_S2P; // bypass S2P: if input is parallel , set it
1220 }
1221 else if(eInPadMode == E_TSP_TS_PAD_MUX_3WIRED_SERIAL)
1222 {
1223 u16Temp |= REG_TSO_TSP_S2P_3WIRE; // input pad is 3-wire serial
1224 }
1225
1226 // S2P config
1227 TSP_TSO_REG(REG_TSO_TSP_CONFIG0) = (TSP_TSO_REG(REG_TSO_TSP_CONFIG0) & ~REG_TSO_TSP_S2P_MASK) | u16Temp;
1228 // select S2P input pad
1229 TSP_TOP_REG(REG_TOP_TSO4_5_MUX) = (TSP_TOP_REG(REG_TOP_TSO4_5_MUX) & ~REG_TOP_TSO4_MASK)
1230 | (eInPad << REG_TOP_TSO4_SHIFT);
1231 // select S2P input clk source
1232 #ifdef CONFIG_MSTAR_CLKM
1233 {
1234 MS_S32 handle;
1235 MS_U8 u8NameIdx = 0;
1236 char* u8ClkSrcNames[] =
1237 {
1238 "CLK_S2P0_PAD0",
1239 "CLK_S2P0_PAD1",
1240 "CLK_S2P0_PAD2",
1241 "CLK_S2P0_PAD3",
1242 "CLK_S2P0_PAD4",
1243 "CLK_S2P0_PAD5",
1244 "CLK_S2P0_PAD6"
1245 };
1246
1247 switch(eInPad)
1248 {
1249 case E_TSP_TS_PAD_EXT0:
1250 u8NameIdx = 0;
1251 break;
1252 case E_TSP_TS_PAD_EXT1:
1253 u8NameIdx = 1;
1254 break;
1255 case E_TSP_TS_PAD_EXT2:
1256 u8NameIdx = 2;
1257 break;
1258 case E_TSP_TS_PAD_EXT3:
1259 u8NameIdx = 3;
1260 break;
1261 case E_TSP_TS_PAD_EXT4:
1262 u8NameIdx = 4;
1263 break;
1264 case E_TSP_TS_PAD_EXT5:
1265 u8NameIdx = 5;
1266 break;
1267 case E_TSP_TS_PAD_EXT6:
1268 u8NameIdx = 6;
1269 break;
1270 default:
1271 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1272 u8NameIdx = 0;
1273 break;
1274 }
1275
1276 handle = Drv_Clkm_Get_Handle("g_clk_s2p_in");
1277 Drv_Clkm_Set_Clk_Source(handle, u8ClkSrcNames[u8NameIdx]);
1278 }
1279 #else
1280 TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) = (TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) & ~(REG_CLKGEN0_S2P_IN_CLK_MASK << REG_CLKGEN0_S2P_IN_CLK_SHIFT))
1281 | ((eInPad & REG_CLKGEN0_S2P_IN_CLK_SRC_MASK) << (REG_CLKGEN0_S2P_IN_CLK_SHIFT + REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT));
1282 #endif
1283 break;
1284 case E_TSP_TS_PAD_MUX_S2P1:
1285 // input from S2P1
1286 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT))
1287 | (REG_TOP_TS_OUT_MODE_S2P1 << REG_TOP_TS_OUT_MODE_SHIFT);
1288
1289 u16Temp = REG_TSO_TSP_S2P1_EN | REG_TSO_TSP_S2P1_TS_SIN_C0 | REG_TSO_TSP_S2P1_TS_SIN_C1;// S2P1 enable bit , serial bit count setting
1290 if(eInPadMode == E_TSP_TS_PAD_MUX_PARALLEL)
1291 {
1292 u16Temp |= REG_TSO_TSP_BYPASS_S2P1; // bypass S2P1: if input is parallel , set it
1293 }
1294 else if(eInPadMode == E_TSP_TS_PAD_MUX_3WIRED_SERIAL)
1295 {
1296 u16Temp |= REG_TSO_TSP_S2P1_3WIRE; // input pad is 3-wire serial
1297 }
1298 // S2P1 config
1299 TSP_TSO_REG(REG_TSO_TSP_CONFIG0) = (TSP_TSO_REG(REG_TSO_TSP_CONFIG0) & ~REG_TSO_TSP_S2P1_MASK) | u16Temp;
1300 // select S2P1 input pad
1301 TSP_TOP_REG(REG_TOP_TSO4_5_MUX) = (TSP_TOP_REG(REG_TOP_TSO4_5_MUX) & ~REG_TOP_TSO5_MASK)
1302 | (eInPad << REG_TOP_TSO5_SHIFT);
1303 #ifdef CONFIG_MSTAR_CLKM
1304 {
1305 MS_S32 handle;
1306 MS_U8 u8NameIdx = 0;
1307 char* u8ClkSrcNames[] =
1308 {
1309 "CLK_S2P1_PAD0",
1310 "CLK_S2P1_PAD1",
1311 "CLK_S2P1_PAD2",
1312 "CLK_S2P1_PAD3",
1313 "CLK_S2P1_PAD4",
1314 "CLK_S2P1_PAD5",
1315 "CLK_S2P1_PAD6"
1316 };
1317
1318 switch(eInPad)
1319 {
1320 case E_TSP_TS_PAD_EXT0:
1321 u8NameIdx = 0;
1322 break;
1323 case E_TSP_TS_PAD_EXT1:
1324 u8NameIdx = 1;
1325 break;
1326 case E_TSP_TS_PAD_EXT2:
1327 u8NameIdx = 2;
1328 break;
1329 case E_TSP_TS_PAD_EXT3:
1330 u8NameIdx = 3;
1331 break;
1332 case E_TSP_TS_PAD_EXT4:
1333 u8NameIdx = 4;
1334 break;
1335 case E_TSP_TS_PAD_EXT5:
1336 u8NameIdx = 5;
1337 break;
1338 case E_TSP_TS_PAD_EXT6:
1339 u8NameIdx = 6;
1340 break;
1341 default:
1342 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1343 u8NameIdx = 0;
1344 break;
1345 }
1346
1347 handle = Drv_Clkm_Get_Handle("g_clk_s2p1_in");
1348 Drv_Clkm_Set_Clk_Source(handle, u8ClkSrcNames[u8NameIdx]);
1349 }
1350 #else
1351 // select S2P1 input clk source
1352 TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) = (TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) & ~(REG_CLKGEN0_S2P_IN_CLK_MASK << REG_CLKGEN0_S2P1_IN_CLK_SHIFT))
1353 | ((eInPad & REG_CLKGEN0_S2P_IN_CLK_SRC_MASK) << (REG_CLKGEN0_S2P1_IN_CLK_SHIFT + REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT));
1354 #endif
1355
1356 break;
1357 default:
1358 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%d] Warining wrong output PAD Mode:%u\n",__FUNCTION__,__LINE__, eOutPadMode));
1359 return FALSE;
1360 }
1361 break;
1362 default:
1363 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1364 return FALSE;
1365 }
1366
1367 return TRUE;
1368 }
1369
_TSP_Hal_TSPAD2RelatedReg_Mapping(TSP_TS_PAD eTSPad,MS_U32 * pu32PADSrc,MS_U32 * pu32CLKSrc)1370 static MS_BOOL _TSP_Hal_TSPAD2RelatedReg_Mapping(TSP_TS_PAD eTSPad, MS_U32* pu32PADSrc, MS_U32* pu32CLKSrc)
1371 {
1372 switch (eTSPad)
1373 {
1374 case E_TSP_TS_PAD_EXT0:
1375 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_EXT0;
1376 *pu32PADSrc = REG_TOP_TS_SRC_EXT0;
1377 break;
1378 case E_TSP_TS_PAD_EXT1:
1379 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_EXT1;
1380 *pu32PADSrc = REG_TOP_TS_SRC_EXT1;
1381 break;
1382 case E_TSP_TS_PAD_INTER0:
1383 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_DMD0;
1384 *pu32PADSrc = REG_TOP_TS_SRC_DMD0;
1385 break;
1386 case E_TSP_TS_PAD_TSOUT0:
1387 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_TSO0;
1388 *pu32PADSrc = REG_TOP_TS_SRC_TSO0;
1389 break;
1390
1391 default:
1392 return FALSE;
1393 }
1394
1395 return TRUE;
1396 }
1397
HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng,TSP_TS_PAD eTSPad)1398 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad)
1399 {
1400 MS_U32 u32CLKSrc = REG_CLKGEN0_TS_SRC_EXT0;
1401 MS_U32 u32PADSrc = REG_TOP_TS_SRC_EXT0;
1402 _TSP_Hal_TSPAD2RelatedReg_Mapping(eTSPad, &u32PADSrc, &u32CLKSrc);
1403
1404 switch(u32TSOEng)
1405 {
1406 case 0:
1407 TSP_TOP_REG(REG_TOP_TSO0_MUX) = (TSP_TOP_REG(REG_TOP_TSO0_MUX) & ~REG_TOP_TS_SRC_MASK) | u32PADSrc;
1408 #ifdef CONFIG_MSTAR_CLKM
1409 {
1410 MS_S32 handle;
1411 MS_U8 u8NameIdx = 0;
1412 char* u8ClkSrcNames[] =
1413 {
1414 "CLK_TSOIN0_PAD0",
1415 "CLK_TSOIN0_PAD1",
1416 "CLK_TSOIN0_PAD2",
1417 "CLK_TSOIN0_PAD3",
1418 "CLK_TSOIN0_PAD4",
1419 "CLK_TSOIN0_PAD5",
1420 "CLK_TSOIN0_PAD6"
1421 };
1422
1423 switch(u32CLKSrc)
1424 {
1425 case REG_CLKGEN0_TS_SRC_EXT0:
1426 u8NameIdx = 0;
1427 break;
1428 case REG_CLKGEN0_TS_SRC_EXT1:
1429 u8NameIdx = 1;
1430 break;
1431 case REG_CLKGEN0_TS_SRC_EXT2:
1432 u8NameIdx = 2;
1433 break;
1434 case REG_CLKGEN0_TS_SRC_EXT3:
1435 u8NameIdx = 3;
1436 break;
1437 case REG_CLKGEN0_TS_SRC_EXT4:
1438 u8NameIdx = 4;
1439 break;
1440 case REG_CLKGEN0_TS_SRC_EXT5:
1441 u8NameIdx = 5;
1442 break;
1443 default:
1444 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1445 u8NameIdx = 0;
1446 break;
1447 }
1448
1449 handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
1450 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1451 }
1452 #else
1453 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) & ~REG_CLKGEN0_TS_MASK)
1454 | (u32CLKSrc << (REG_CLKGEN0_TSO0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1455 #endif
1456 return TRUE;
1457
1458 default:
1459 return FALSE;
1460 }
1461 }
1462
1463
HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf,MS_BOOL bClkInv)1464 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv)
1465 {
1466 if (bClkInv)
1467 {
1468 switch (tsIf)
1469 {
1470 case 0:
1471 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
1472 break;
1473 case 1:
1474 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
1475 break;
1476 case 2:
1477 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
1478 break;
1479 case 3:
1480 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT));
1481 break;
1482 default:
1483 return FALSE;
1484 }
1485 }
1486 else
1487 {
1488 switch (tsIf)
1489 {
1490 case 0:
1491 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
1492 break;
1493 case 1:
1494 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
1495 break;
1496 case 2:
1497 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
1498 break;
1499 case 3:
1500 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT));
1501 break;
1502 default:
1503 return FALSE;
1504 }
1505 }
1506 return TRUE;
1507 }
1508
HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf,MS_BOOL bClkDis)1509 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis)
1510 {
1511 if (bClkDis)
1512 {
1513 #ifdef CONFIG_MSTAR_CLKM
1514 MS_S32 s32Handle;
1515
1516 switch (tsIf)
1517 {
1518 case 0:
1519 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
1520 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1521 break;
1522 case 1:
1523 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1524 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1525 break;
1526 case 2:
1527 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1528 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1529 break;
1530 case 3:
1531 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1532 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1533 break;
1534 default:
1535 return FALSE;
1536 }
1537 #else
1538 switch (tsIf)
1539 {
1540 case 0:
1541 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
1542 break;
1543 case 1:
1544 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
1545 break;
1546 case 2:
1547 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
1548 break;
1549 case 3:
1550 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT));
1551 break;
1552 default:
1553 return FALSE;
1554 }
1555 #endif
1556 }
1557 else
1558 {
1559 #ifdef CONFIG_MSTAR_CLKM
1560 MS_S32 s32Handle;
1561 MS_U16 u16ClkSrc;
1562 MS_U8 u8NameIdx = 0;
1563 char* u8ClkSrcNames[] =
1564 {
1565 "CLK_TS0_PAD0",
1566 "CLK_TS0_PAD1",
1567 "CLK_TS0_PAD2",
1568 "CLK_TS0_PAD3",
1569 "CLK_TS0_PAD4",
1570 "CLK_TS0_PAD5",
1571 "CLK_TS0_PAD6",
1572 "CLK_TS0_PADTSO"
1573 };
1574
1575 switch (tsIf)
1576 {
1577 case 0:
1578 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
1579 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & REG_CLKGEN0_TS_MASK) >> (REG_CLKGEN0_TS0_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1580 break;
1581 case 1:
1582 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1583 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT)) >> (REG_CLKGEN0_TS1_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1584 break;
1585 case 2:
1586 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1587 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT)) >> (REG_CLKGEN0_TS2_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1588 break;
1589 case 3:
1590 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1591 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) >> (REG_CLKGEN0_TS3_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1592 break;
1593 default:
1594 return FALSE;
1595 }
1596
1597 switch(u16ClkSrc)
1598 {
1599 case REG_CLKGEN0_TS_SRC_EXT0:
1600 u8NameIdx = 0;
1601 break;
1602 case REG_CLKGEN0_TS_SRC_EXT1:
1603 u8NameIdx = 1;
1604 break;
1605 case REG_CLKGEN0_TS_SRC_EXT2:
1606 u8NameIdx = 2;
1607 break;
1608 case REG_CLKGEN0_TS_SRC_EXT3:
1609 u8NameIdx = 3;
1610 break;
1611 case REG_CLKGEN0_TS_SRC_EXT4:
1612 u8NameIdx = 4;
1613 break;
1614 case REG_CLKGEN0_TS_SRC_EXT5:
1615 u8NameIdx = 5;
1616 break;
1617 case REG_CLKGEN0_TS_SRC_EXT6:
1618 u8NameIdx = 6;
1619 break;
1620 case REG_CLKGEN0_TS_SRC_TSO0:
1621 u8NameIdx = 7;
1622 break;
1623 default:
1624 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1625 u8NameIdx = 0;
1626 break;
1627 }
1628
1629 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcNames[u8NameIdx]);
1630 #else
1631 switch (tsIf)
1632 {
1633 case 0:
1634 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
1635 break;
1636 case 1:
1637 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
1638 break;
1639 case 2:
1640 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
1641 break;
1642 case 3:
1643 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT));
1644 break;
1645 default:
1646 return FALSE;
1647 }
1648 #endif
1649 }
1650 return TRUE;
1651 }
1652
1653 // @NOTE tsif0 and tsif2 can do filein and livein simulatenously,so tsif0 tsif2's output are both live TS Data
HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1654 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1655 {
1656 if(bEnable)
1657 {
1658 switch(eFileEng)
1659 {
1660 case E_FILEENG_TSIF0:
1661 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firmware or playback)
1662 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS
1663 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable
1664 break;
1665 case E_FILEENG_TSIF1:
1666 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firmware or playback) we don't use this fileEng for FW
1667 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1);
1668 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1);
1669 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable
1670 break;
1671 case E_FILEENG_TSIF2:
1672 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2);
1673 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2);
1674 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2);
1675 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2);
1676 break;
1677 case E_FILEENG_TSIF3:
1678 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3);
1679 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3);
1680 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3);
1681 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3);
1682 break;
1683 default:
1684 return FALSE;
1685 }
1686 }
1687 else
1688 {
1689 switch(eFileEng)
1690 {
1691 case E_FILEENG_TSIF0:
1692 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);
1693 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL);
1694 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN);
1695 break;
1696 case E_FILEENG_TSIF1:
1697 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1);
1698 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1);
1699 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1);
1700 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN);
1701 break;
1702 case E_FILEENG_TSIF2:
1703 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2);
1704 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2);
1705 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2);
1706 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2);
1707 break;
1708 case E_FILEENG_TSIF3:
1709 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3);
1710 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3);
1711 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3);
1712 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3);
1713 break;
1714 default:
1715 return FALSE;
1716 }
1717 }
1718
1719 return TRUE;
1720 }
1721
HAL_TSP_TSIF_BitSwap(MS_U32 tsIf,MS_BOOL bEnable)1722 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable)
1723 {
1724 if(bEnable)
1725 {
1726 switch(tsIf)
1727 {
1728 case 0:
1729 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP);
1730 break;
1731 case 1:
1732 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP);
1733 break;
1734 case 2:
1735 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP);
1736 break;
1737 case 3:
1738 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP);
1739 break;
1740 default:
1741 return;
1742 }
1743 }
1744 else
1745 {
1746 switch(tsIf)
1747 {
1748 case 0:
1749 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP);
1750 break;
1751 case 1:
1752 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP);
1753 break;
1754 case 2:
1755 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP);
1756 break;
1757 case 3:
1758 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP);
1759 break;
1760 default:
1761 return;
1762 }
1763 }
1764 }
1765
HAL_TSP_TSIF_ExtSync(MS_U32 tsIf,MS_BOOL bEnable)1766 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable)
1767 {
1768 if(bEnable)
1769 {
1770 //printf("External Sync\n");
1771
1772 switch(tsIf)
1773 {
1774 case 0:
1775 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC);
1776 break;
1777 case 1:
1778 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC);
1779 break;
1780 case 2:
1781 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2);
1782 break;
1783 case 3:
1784 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3);
1785 break;
1786 default:
1787 return;
1788 }
1789 }
1790 else
1791 {
1792 //printf("Internal Sync\n");
1793
1794 switch(tsIf)
1795 {
1796 case 0:
1797 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC);
1798 break;
1799 case 1:
1800 REG16_CLR(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC);
1801 break;
1802 case 2:
1803 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2);
1804 break;
1805 case 3:
1806 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3);
1807 break;
1808 default:
1809 return;
1810 }
1811 }
1812 }
1813
HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng,MS_BOOL bBypass)1814 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bBypass)
1815 {
1816 if(bBypass)
1817 {
1818 switch (eFileEng)
1819 {
1820 case E_FILEENG_TSIF0:
1821 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP);
1822 break;
1823 case E_FILEENG_TSIF1:
1824 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP1);
1825 break;
1826 case E_FILEENG_TSIF2:
1827 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP2);
1828 break;
1829 case E_FILEENG_TSIF3:
1830 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP3);
1831 break;
1832 default:
1833 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng : %d !\n",__FILE__,__FUNCTION__,__LINE__,eFileEng));
1834 break;
1835 }
1836 //REG16_MSK_W(&_RegCtrl3->CFG3_10,CFG3_10_PS_MODE_SRC_MASK,(eFileEng << CFG3_10_PS_MODE_SRC_SHIFT));
1837 }
1838 else
1839 {
1840 switch (eFileEng)
1841 {
1842 case E_FILEENG_TSIF0:
1843 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP);
1844 break;
1845 case E_FILEENG_TSIF1:
1846 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP1);
1847 break;
1848 case E_FILEENG_TSIF2:
1849 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP2);
1850 break;
1851 case E_FILEENG_TSIF3:
1852 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP3);
1853 break;
1854 default:
1855 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng : %d !\n",__FILE__,__FUNCTION__,__LINE__,eFileEng));
1856 break;
1857 }
1858 }
1859 }
1860
1861
HAL_TSP_TSIF_Parl(MS_U32 tsIf,MS_BOOL bEnable)1862 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable)
1863 {
1864 if(bEnable)
1865 {
1866 switch(tsIf)
1867 {
1868 case 0:
1869 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL);
1870 break;
1871 case 1:
1872 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL);
1873 break;
1874 case 2:
1875 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2);
1876 break;
1877 case 3:
1878 REG16_SET(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3);
1879 break;
1880 default:
1881 return;
1882 }
1883 }
1884 else
1885 {
1886 switch(tsIf)
1887 {
1888 case 0:
1889 REG16_CLR(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL);
1890 break;
1891 case 1:
1892 REG16_CLR(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL);
1893 break;
1894 case 2:
1895 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2);
1896 break;
1897 case 3:
1898 REG16_CLR(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3);
1899 break;
1900 default:
1901 return;
1902 }
1903 }
1904 }
1905
HAL_TSP_PAD_3Wire(MS_U32 u32Pad,MS_BOOL bEnable)1906 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable)
1907 {
1908 #if 0 //@NOTE: Kano do NOT need to set
1909 if(bEnable)
1910 {
1911 switch(u32Pad)
1912 {
1913 case 0:
1914 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS0_3WIRE_EN;
1915 break;
1916 case 1:
1917 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS1_3WIRE_EN;
1918 break;
1919 case 2:
1920 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1)| REG_TOP_TSP_TS2_3WIRE_EN;
1921 break;
1922 case 3:
1923 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) | REG_TOP_TSP_TS3_3WIRE_EN;
1924 break;
1925
1926 default:
1927 return;
1928 }
1929 }
1930 else
1931 {
1932 switch(u32Pad)
1933 {
1934 case 0:
1935 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS0_3WIRE_EN;
1936 break;
1937 case 1:
1938 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS1_3WIRE_EN;
1939 break;
1940 case 2:
1941 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) & ~REG_TOP_TSP_TS2_3WIRE_EN;
1942 break;
1943 case 3:
1944 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) & ~REG_TOP_TSP_TS3_3WIRE_EN;
1945 break;
1946 default:
1947 return;
1948 }
1949 }
1950 #endif
1951 }
1952
HAL_TSP_TSIF_3Wire(MS_U32 tsIf,MS_BOOL bEnable)1953 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable)
1954 {
1955 if(bEnable)
1956 {
1957 switch(tsIf)
1958 {
1959 case 0:
1960 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0);
1961 break;
1962 case 1:
1963 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1);
1964 break;
1965 case 2:
1966 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2);
1967 break;
1968 case 3:
1969 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS3);
1970 break;
1971 default:
1972 return;
1973 }
1974 }
1975 else
1976 {
1977 switch(tsIf)
1978 {
1979 case 0:
1980 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0);
1981 break;
1982 case 1:
1983 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1);
1984 break;
1985 case 2:
1986 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2);
1987 break;
1988 case 3:
1989 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS3);
1990 break;
1991 default:
1992 return;
1993 }
1994 }
1995
1996 }
1997
HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId,MS_BOOL bEn)1998 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn)
1999 {
2000 if(bEn)
2001 {
2002 REG16_SET(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_CC_DROP_MSAK);
2003 }
2004 else
2005 {
2006 REG16_CLR(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_CC_DROP_MSAK);
2007 }
2008 }
2009
HAL_TSP_ReDirect_File(MS_U32 reDir,MS_U32 tsIf,MS_BOOL bEn)2010 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn)
2011 {
2012 //@NOTE Not support in KANO(K7)
2013 #if 0
2014 MS_U16 u16Src = 0;
2015
2016 if((reDir > 0) || (tsIf > 1))
2017 return;
2018
2019 if(bEn)
2020 {
2021 u16Src = (MS_U16)(tsIf + 1) << CFG_01_PDFLT2_FILE_SRC_SHIFT;
2022 }
2023
2024 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PDFLT2_FILE_SRC, u16Src);
2025 #endif
2026 }
2027
2028 // [ToDo]
HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn)2029 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn)
2030 {
2031 if(bEn)
2032 {
2033 switch(u32Tsif)
2034 {
2035 case 0:
2036 switch (eFltType)
2037 {
2038 case E_TSP_DST_FIFO_VIDEO:
2039 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN);
2040 break;
2041 case E_TSP_DST_FIFO_VIDEO3D:
2042 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN);
2043 break;
2044 case E_TSP_DST_FIFO_VIDEO3:
2045 REG16_SET(&_RegCtrl3->CFG3_2E, CFG3_2E_PKTDMX0_TRACE_MARK_V3_EN);
2046 break;
2047 case E_TSP_DST_FIFO_VIDEO4:
2048 REG16_SET(&_RegCtrl3->CFG3_2F, CFG3_2F_PKTDMX0_TRACE_MARK_V4_EN);
2049 break;
2050 case E_TSP_DST_FIFO_AUDIO:
2051 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN);
2052 break;
2053 case E_TSP_DST_FIFO_AUDIO2:
2054 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN);
2055 break;
2056 case E_TSP_DST_FIFO_AUDIO3:
2057 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AC_EN);
2058 break;
2059 case E_TSP_DST_FIFO_AUDIO4:
2060 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX0_TRACE_MARK_AD_EN);
2061 break;
2062 default:
2063 break;
2064 }
2065 break;
2066 case 1:
2067 switch (eFltType)
2068 {
2069 case E_TSP_DST_FIFO_VIDEO:
2070 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN);
2071 break;
2072 case E_TSP_DST_FIFO_VIDEO3D:
2073 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN);
2074 break;
2075 case E_TSP_DST_FIFO_VIDEO3:
2076 REG16_SET(&_RegCtrl3->CFG3_2E, CFG3_2E_PKTDMX1_TRACE_MARK_V3_EN);
2077 break;
2078 case E_TSP_DST_FIFO_VIDEO4:
2079 REG16_SET(&_RegCtrl3->CFG3_2F, CFG3_2F_PKTDMX1_TRACE_MARK_V4_EN);
2080 break;
2081 case E_TSP_DST_FIFO_AUDIO:
2082 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN);
2083 break;
2084 case E_TSP_DST_FIFO_AUDIO2:
2085 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN);
2086 break;
2087 case E_TSP_DST_FIFO_AUDIO3:
2088 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AC_EN);
2089 break;
2090 case E_TSP_DST_FIFO_AUDIO4:
2091 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX1_TRACE_MARK_AD_EN);
2092 break;
2093 default:
2094 break;
2095 }
2096 break;
2097 case 2:
2098 switch (eFltType)
2099 {
2100 case E_TSP_DST_FIFO_VIDEO:
2101 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN);
2102 break;
2103 case E_TSP_DST_FIFO_VIDEO3D:
2104 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN);
2105 break;
2106 case E_TSP_DST_FIFO_VIDEO3:
2107 REG16_SET(&_RegCtrl3->CFG3_2E, CFG3_2E_PKTDMX2_TRACE_MARK_V3_EN);
2108 break;
2109 case E_TSP_DST_FIFO_VIDEO4:
2110 REG16_SET(&_RegCtrl3->CFG3_2F, CFG3_2F_PKTDMX2_TRACE_MARK_V4_EN);
2111 break;
2112 case E_TSP_DST_FIFO_AUDIO:
2113 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN);
2114 break;
2115 case E_TSP_DST_FIFO_AUDIO2:
2116 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN);
2117 break;
2118 case E_TSP_DST_FIFO_AUDIO3:
2119 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AC_EN);
2120 break;
2121 case E_TSP_DST_FIFO_AUDIO4:
2122 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX2_TRACE_MARK_AD_EN);
2123 break;
2124 default:
2125 break;
2126 }
2127 break;
2128 case 3:
2129 switch (eFltType)
2130 {
2131 case E_TSP_DST_FIFO_VIDEO:
2132 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V_EN);
2133 break;
2134 case E_TSP_DST_FIFO_VIDEO3D:
2135 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN);
2136 break;
2137 case E_TSP_DST_FIFO_VIDEO3:
2138 REG16_SET(&_RegCtrl3->CFG3_2E, CFG3_2E_PKTDMX3_TRACE_MARK_V3_EN);
2139 break;
2140 case E_TSP_DST_FIFO_VIDEO4:
2141 REG16_SET(&_RegCtrl3->CFG3_2F, CFG3_2F_PKTDMX3_TRACE_MARK_V4_EN);
2142 break;
2143 case E_TSP_DST_FIFO_AUDIO:
2144 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_A_EN);
2145 break;
2146 case E_TSP_DST_FIFO_AUDIO2:
2147 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN);
2148 break;
2149 case E_TSP_DST_FIFO_AUDIO3:
2150 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AC_EN);
2151 break;
2152 case E_TSP_DST_FIFO_AUDIO4:
2153 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX3_TRACE_MARK_AD_EN);
2154 break;
2155 default:
2156 break;
2157 }
2158 break;
2159 default:
2160 break;
2161 }
2162 }
2163 else
2164 {
2165 switch(u32Tsif)
2166 {
2167 case 0:
2168 switch (eFltType)
2169 {
2170 case E_TSP_DST_FIFO_VIDEO:
2171 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN);
2172 break;
2173 case E_TSP_DST_FIFO_VIDEO3D:
2174 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN);
2175 break;
2176 case E_TSP_DST_FIFO_VIDEO3:
2177 REG16_CLR(&_RegCtrl3->CFG3_2E, CFG3_2E_PKTDMX0_TRACE_MARK_V3_EN);
2178 break;
2179 case E_TSP_DST_FIFO_VIDEO4:
2180 REG16_CLR(&_RegCtrl3->CFG3_2F, CFG3_2F_PKTDMX0_TRACE_MARK_V4_EN);
2181 break;
2182 case E_TSP_DST_FIFO_AUDIO:
2183 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN);
2184 break;
2185 case E_TSP_DST_FIFO_AUDIO2:
2186 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN);
2187 break;
2188 case E_TSP_DST_FIFO_AUDIO3:
2189 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AC_EN);
2190 break;
2191 case E_TSP_DST_FIFO_AUDIO4:
2192 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX0_TRACE_MARK_AD_EN);
2193 break;
2194 default:
2195 break;
2196 }
2197 break;
2198 case 1:
2199 switch (eFltType)
2200 {
2201 case E_TSP_DST_FIFO_VIDEO:
2202 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN);
2203 break;
2204 case E_TSP_DST_FIFO_VIDEO3D:
2205 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN);
2206 break;
2207 case E_TSP_DST_FIFO_VIDEO3:
2208 REG16_CLR(&_RegCtrl3->CFG3_2E, CFG3_2E_PKTDMX1_TRACE_MARK_V3_EN);
2209 break;
2210 case E_TSP_DST_FIFO_VIDEO4:
2211 REG16_CLR(&_RegCtrl3->CFG3_2F, CFG3_2F_PKTDMX1_TRACE_MARK_V4_EN);
2212 break;
2213 case E_TSP_DST_FIFO_AUDIO:
2214 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN);
2215 break;
2216 case E_TSP_DST_FIFO_AUDIO2:
2217 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN);
2218 break;
2219 case E_TSP_DST_FIFO_AUDIO3:
2220 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AC_EN);
2221 break;
2222 case E_TSP_DST_FIFO_AUDIO4:
2223 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX1_TRACE_MARK_AD_EN);
2224 break;
2225 default:
2226 break;
2227 }
2228 break;
2229 case 2:
2230 switch (eFltType)
2231 {
2232 case E_TSP_DST_FIFO_VIDEO:
2233 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN);
2234 break;
2235 case E_TSP_DST_FIFO_VIDEO3D:
2236 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN);
2237 break;
2238 case E_TSP_DST_FIFO_VIDEO3:
2239 REG16_CLR(&_RegCtrl3->CFG3_2E, CFG3_2E_PKTDMX2_TRACE_MARK_V3_EN);
2240 break;
2241 case E_TSP_DST_FIFO_VIDEO4:
2242 REG16_CLR(&_RegCtrl3->CFG3_2F, CFG3_2F_PKTDMX2_TRACE_MARK_V4_EN);
2243 break;
2244 case E_TSP_DST_FIFO_AUDIO:
2245 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN);
2246 break;
2247 case E_TSP_DST_FIFO_AUDIO2:
2248 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN);
2249 break;
2250 case E_TSP_DST_FIFO_AUDIO3:
2251 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AC_EN);
2252 break;
2253 case E_TSP_DST_FIFO_AUDIO4:
2254 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX2_TRACE_MARK_AD_EN);
2255 break;
2256 default:
2257 break;
2258 }
2259 break;
2260 case 3:
2261 switch (eFltType)
2262 {
2263 case E_TSP_DST_FIFO_VIDEO:
2264 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V_EN);
2265 break;
2266 case E_TSP_DST_FIFO_VIDEO3D:
2267 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN);
2268 break;
2269 case E_TSP_DST_FIFO_VIDEO3:
2270 REG16_CLR(&_RegCtrl3->CFG3_2E, CFG3_2E_PKTDMX3_TRACE_MARK_V3_EN);
2271 break;
2272 case E_TSP_DST_FIFO_VIDEO4:
2273 REG16_CLR(&_RegCtrl3->CFG3_2F, CFG3_2F_PKTDMX3_TRACE_MARK_V4_EN);
2274 break;
2275 case E_TSP_DST_FIFO_AUDIO:
2276 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_A_EN);
2277 break;
2278 case E_TSP_DST_FIFO_AUDIO2:
2279 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN);
2280 break;
2281 case E_TSP_DST_FIFO_AUDIO3:
2282 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AC_EN);
2283 break;
2284 case E_TSP_DST_FIFO_AUDIO4:
2285 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX3_TRACE_MARK_AD_EN);
2286 break;
2287 default:
2288 break;
2289 }
2290 break;
2291 default:
2292 break;
2293 }
2294 }
2295 }
2296
HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)2297 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)
2298 {
2299
2300 if(bEn == TRUE)
2301 {
2302 switch(u32BD)
2303 {
2304 case 0:
2305 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN);
2306 break;
2307 case 1:
2308 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN);
2309 break;
2310 default:
2311 printf("Not support !!\n");
2312 break;
2313 }
2314 }
2315 else
2316 {
2317 switch(u32BD)
2318 {
2319 case 0:
2320 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD_AUD_EN);
2321 break;
2322 case 1:
2323 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN);
2324 break;
2325 default:
2326 printf("Not support !!\n");
2327 break;
2328
2329 }
2330 }
2331
2332 }
2333
HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng,MS_U32 u32PktSize)2334 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize)
2335 {
2336 MS_U32 u32PktLen = u32PktSize;
2337 MS_U16 u16value = 0;
2338
2339 if(u32PktSize == 130)
2340 {
2341 u32PktLen = 188;
2342 }
2343 else if(u32PktSize == 134)
2344 {
2345 u32PktLen = 192;
2346 }
2347 switch(eFileEng)
2348 {
2349 case E_FILEENG_TSIF0:
2350 u16value = HW4_CFG36_RVU_PSI_EN0 | HW4_CFG36_RVU_EN0 | HW4_CFG36_RVU_TIMESTAMP_EN0;
2351 REG16_CLR(&_RegCtrl3->CFG3_36, u16value);
2352 break;
2353 case E_FILEENG_TSIF1:
2354 u16value = HW4_CFG36_RVU_PSI_EN1 | HW4_CFG36_RVU_EN1 | HW4_CFG36_RVU_TIMESTAMP_EN1;
2355 REG16_CLR(&_RegCtrl3->CFG3_36, u16value);
2356 break;
2357 case E_FILEENG_TSIF2:
2358 u16value = CFG4_54_RVU_PSI_EN2 | CFG4_54_RVU_EN2 | CFG4_54_RVU_TIMESTAMP_EN2;
2359 REG16_CLR(&_RegCtrl4->CFG4_54, u16value);
2360 break;
2361 case E_FILEENG_TSIF3:
2362 u16value = CFG4_54_RVU_PSI_EN3 | CFG4_54_RVU_EN3 | CFG4_54_RVU_TIMESTAMP_EN3;
2363 REG16_CLR(&_RegCtrl4->CFG4_54, u16value);
2364 break;
2365 default:
2366 printf("Not support !!\n");
2367 return;
2368 }
2369
2370 if(K6U02)
2371 {
2372 switch(eFileEng)
2373 {
2374 case E_FILEENG_TSIF0:
2375 REG16_CLR(&_RegCtrl3->CFG3_1A, CFG3_1A_RVU_DIRECTV_AFTER_CA_ENABLE_PATH0);
2376 REG16_CLR(&_RegCtrl3->CFG3_1C, CFG3_1C_PATH0_RVU_ALWAYS_PAYLOAD_128);
2377 break;
2378 case E_FILEENG_TSIF1:
2379 REG16_CLR(&_RegCtrl3->CFG3_1A, CFG3_1A_RVU_DIRECTV_AFTER_CA_ENABLE_PATH1);
2380 REG16_CLR(&_RegCtrl3->CFG3_1C, CFG3_1C_PATH1_RVU_ALWAYS_PAYLOAD_128);
2381 break;
2382 case E_FILEENG_TSIF2:
2383 REG16_CLR(&_RegCtrl3->CFG3_1A, CFG3_1A_RVU_DIRECTV_AFTER_CA_ENABLE_PATH2);
2384 REG16_CLR(&_RegCtrl3->CFG3_1C, CFG3_1C_PATH2_RVU_ALWAYS_PAYLOAD_128);
2385 break;
2386 case E_FILEENG_TSIF3:
2387 REG16_CLR(&_RegCtrl3->CFG3_1A, CFG3_1A_RVU_DIRECTV_AFTER_CA_ENABLE_PATH3);
2388 REG16_CLR(&_RegCtrl3->CFG3_1C, CFG3_1C_PATH3_RVU_ALWAYS_PAYLOAD_128);
2389 break;
2390 default:
2391 printf("Not support !!\n");
2392 return;
2393 }
2394 }
2395
2396 if(u32PktSize == 130 || u32PktSize == 134) //RVU
2397 {
2398 MS_U16 u16value = 0;
2399
2400 if(u32PktSize == 134)
2401 {
2402 switch(eFileEng)
2403 {
2404 case E_FILEENG_TSIF0:
2405 u16value = HW4_CFG36_RVU_TIMESTAMP_EN0;
2406 break;
2407 case E_FILEENG_TSIF1:
2408 u16value = HW4_CFG36_RVU_TIMESTAMP_EN1;
2409 break;
2410 case E_FILEENG_TSIF2:
2411 u16value = CFG4_54_RVU_TIMESTAMP_EN2;
2412 break;
2413 case E_FILEENG_TSIF3:
2414 u16value = CFG4_54_RVU_TIMESTAMP_EN3;
2415 break;
2416 default:
2417 printf("Not support !!\n");
2418 break;
2419 }
2420 }
2421
2422 switch(eFileEng)
2423 {
2424 case E_FILEENG_TSIF0:
2425 u16value |= (HW4_CFG36_RVU_PSI_EN0 | HW4_CFG36_RVU_EN0);
2426 REG16_SET(&_RegCtrl3->CFG3_36, u16value);
2427 break;
2428 case E_FILEENG_TSIF1:
2429 u16value |= (HW4_CFG36_RVU_PSI_EN1 | HW4_CFG36_RVU_EN1);
2430 REG16_SET(&_RegCtrl3->CFG3_36, u16value);
2431 break;
2432 case E_FILEENG_TSIF2:
2433 u16value |= (CFG4_54_RVU_PSI_EN2 | CFG4_54_RVU_EN2);
2434 REG16_SET(&_RegCtrl4->CFG4_54, u16value);
2435 break;
2436 case E_FILEENG_TSIF3:
2437 u16value |= (CFG4_54_RVU_PSI_EN3 | CFG4_54_RVU_EN3);
2438 REG16_SET(&_RegCtrl4->CFG4_54, u16value);
2439 break;
2440 default:
2441 printf("Not support !!\n");
2442 return;
2443 }
2444
2445 if(K6U02)
2446 {
2447 switch(eFileEng)
2448 {
2449 case E_FILEENG_TSIF0:
2450 REG16_SET(&_RegCtrl3->CFG3_1A, CFG3_1A_RVU_DIRECTV_AFTER_CA_ENABLE_PATH0);
2451 REG16_SET(&_RegCtrl3->CFG3_1C, CFG3_1C_PATH0_RVU_ALWAYS_PAYLOAD_128);
2452 break;
2453 case E_FILEENG_TSIF1:
2454 REG16_SET(&_RegCtrl3->CFG3_1A, CFG3_1A_RVU_DIRECTV_AFTER_CA_ENABLE_PATH1);
2455 REG16_SET(&_RegCtrl3->CFG3_1C, CFG3_1C_PATH1_RVU_ALWAYS_PAYLOAD_128);
2456 break;
2457 case E_FILEENG_TSIF2:
2458 REG16_SET(&_RegCtrl3->CFG3_1A, CFG3_1A_RVU_DIRECTV_AFTER_CA_ENABLE_PATH2);
2459 REG16_SET(&_RegCtrl3->CFG3_1C, CFG3_1C_PATH2_RVU_ALWAYS_PAYLOAD_128);
2460 break;
2461 case E_FILEENG_TSIF3:
2462 REG16_SET(&_RegCtrl3->CFG3_1A, CFG3_1A_RVU_DIRECTV_AFTER_CA_ENABLE_PATH3);
2463 REG16_SET(&_RegCtrl3->CFG3_1C, CFG3_1C_PATH3_RVU_ALWAYS_PAYLOAD_128);
2464 break;
2465 default:
2466 printf("Not support !!\n");
2467 return;
2468 }
2469 }
2470
2471 }
2472
2473 switch(eFileEng)
2474 {
2475 case E_FILEENG_TSIF0:
2476 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE);
2477 REG16_W(&_RegCtrl->PktChkSizeFilein, (REG16_R(&_RegCtrl->PktChkSizeFilein) & ~TSP_PKT_SIZE_MASK) | (TSP_PKT_SIZE_MASK & (u32PktLen-1)));
2478 break;
2479 case E_FILEENG_TSIF1:
2480 REG16_W(&_RegCtrl2->CFG_02, (REG16_R(&_RegCtrl2->CFG_02) & ~CFG_02_PKT_CHK_SIZE_FIN1) | (CFG_02_PKT_CHK_SIZE_FIN1 & (u32PktLen-1)));
2481 break;
2482 case E_FILEENG_TSIF2:
2483 REG16_W(&_RegCtrl2->CFG_07, (REG16_R(&_RegCtrl2->CFG_07) & ~CFG_07_PKT_CHK_SIZE_FIN2) | (CFG_07_PKT_CHK_SIZE_FIN2 & (u32PktLen-1)));
2484 break;
2485 case E_FILEENG_TSIF3:
2486 REG16_W(&_RegCtrl2->CFG_0C, (REG16_R(&_RegCtrl2->CFG_0C) & ~CFG_0C_PKT_CHK_SIZE_FIN3) | (CFG_0C_PKT_CHK_SIZE_FIN3 & (u32PktLen-1)));
2487 break;
2488 default:
2489 break;
2490 }
2491 }
2492
HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng,MS_U32 addr)2493 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr)
2494 {
2495 // Check MIU select
2496 MS_U8 u8MiuSel;
2497 MS_PHY phyMiuOffsetFileinAddr;
2498 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinAddr, addr);
2499
2500 switch(eFileEng)
2501 {
2502 case E_FILEENG_TSIF0:
2503 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN0_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN0_SHIFT) & REG_MIU_SEL_FILEIN0_MASK));
2504 REG32_W(&_RegCtrl->TsDma_Addr, phyMiuOffsetFileinAddr);
2505 break;
2506 case E_FILEENG_TSIF1:
2507 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN1_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN1_SHIFT) & REG_MIU_SEL_FILEIN1_MASK));
2508 REG32_W(&_RegCtrl2->CFG_30_31, phyMiuOffsetFileinAddr);
2509 break;
2510 case E_FILEENG_TSIF2:
2511 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN2_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN2_SHIFT) & REG_MIU_SEL_FILEIN2_MASK));
2512 REG32_W(&_RegCtrl2->CFG_35_36, phyMiuOffsetFileinAddr);
2513 break;
2514 case E_FILEENG_TSIF3:
2515 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN3_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN3_SHIFT) & REG_MIU_SEL_FILEIN3_MASK));
2516 REG32_W(&_RegCtrl2->CFG_3A_3B, phyMiuOffsetFileinAddr);
2517 break;
2518 default:
2519 break;
2520 }
2521 }
2522
HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng,MS_U32 size)2523 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size)
2524 {
2525 switch(eFileEng)
2526 {
2527 case E_FILEENG_TSIF0:
2528 REG32_W(&_RegCtrl->TsDma_Size, size);
2529 break;
2530 case E_FILEENG_TSIF1:
2531 REG32_W(&_RegCtrl2->CFG_32_33, size);
2532 break;
2533 case E_FILEENG_TSIF2:
2534 REG32_W(&_RegCtrl2->CFG_37_38, size);
2535 break;
2536 case E_FILEENG_TSIF3:
2537 REG32_W(&_RegCtrl2->CFG_3C_3D, size);
2538 break;
2539 default:
2540 break;
2541 }
2542 }
2543
HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)2544 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)
2545 {
2546 switch(eFileEng)
2547 {
2548 case E_FILEENG_TSIF0:
2549 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START);
2550 break;
2551 case E_FILEENG_TSIF1:
2552 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START);
2553 break;
2554 case E_FILEENG_TSIF2:
2555 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START);
2556 break;
2557 case E_FILEENG_TSIF3:
2558 REG16_SET(&_RegCtrl2->CFG_3E, CFG_3E_FILEIN_CTRL_TSIF3_START);
2559 break;
2560 default:
2561 break;
2562 }
2563 }
2564
HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)2565 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)
2566 {
2567 switch (eFileEng)
2568 {
2569 case E_FILEENG_TSIF0:
2570 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);
2571 return TRUE;
2572 case E_FILEENG_TSIF1:
2573 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE);
2574 return TRUE;
2575 case E_FILEENG_TSIF2:
2576 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE);
2577 return TRUE;
2578 case E_FILEENG_TSIF3:
2579 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF3_FILE_PAUSE);
2580 return TRUE;
2581 default:
2582 return FALSE;
2583 }
2584 }
2585
HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)2586 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)
2587 {
2588 switch (eFileEng)
2589 {
2590 case E_FILEENG_TSIF0:
2591 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);
2592 return TRUE;
2593 case E_FILEENG_TSIF1:
2594 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE);
2595 return TRUE;
2596 case E_FILEENG_TSIF2:
2597 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE);
2598 return TRUE;
2599 case E_FILEENG_TSIF3:
2600 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF3_FILE_PAUSE);
2601 return TRUE;
2602 default:
2603 return FALSE;
2604 }
2605 }
2606
HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)2607 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)
2608 {
2609 switch(eFileEng)
2610 {
2611 case E_FILEENG_TSIF0:
2612 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START));
2613 break;
2614 case E_FILEENG_TSIF1:
2615 REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START));
2616 break;
2617 case E_FILEENG_TSIF2:
2618 REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START));
2619 break;
2620 case E_FILEENG_TSIF3:
2621 REG16_SET(&_RegCtrl2->CFG_3E, (CFG_3E_FILEIN_INIT_TRUST_TSIF3 | CFG_3E_FILEIN_CTRL_TSIF3_START));
2622 break;
2623 default:
2624 break;
2625 }
2626 }
2627
HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng,MS_BOOL bEn)2628 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn)
2629 {
2630 if(bEn)
2631 {
2632 switch(eFileEng)
2633 {
2634 case E_FILEENG_TSIF0:
2635 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0);
2636 break;
2637 case E_FILEENG_TSIF1:
2638 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1);
2639 break;
2640 case E_FILEENG_TSIF2:
2641 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2);
2642 break;
2643 case E_FILEENG_TSIF3:
2644 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3);
2645 break;
2646 default:
2647 break;
2648 }
2649 }
2650 else
2651 {
2652 switch(eFileEng)
2653 {
2654 case E_FILEENG_TSIF0:
2655 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0);
2656 break;
2657 case E_FILEENG_TSIF1:
2658 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1);
2659 break;
2660 case E_FILEENG_TSIF2:
2661 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2);
2662 break;
2663 case E_FILEENG_TSIF3:
2664 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3);
2665 break;
2666 default:
2667 break;
2668 }
2669 }
2670 }
2671
HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)2672 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
2673 {
2674 if(bEnable)
2675 {
2676 switch(eFileEng)
2677 {
2678 case E_FILEENG_TSIF0:
2679 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
2680 break;
2681 case E_FILEENG_TSIF1:
2682 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
2683 break;
2684 case E_FILEENG_TSIF2:
2685 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
2686 break;
2687 case E_FILEENG_TSIF3:
2688 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
2689 break;
2690 default:
2691 break;
2692 }
2693 }
2694 else
2695 {
2696 switch(eFileEng)
2697 {
2698 case E_FILEENG_TSIF0:
2699 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
2700 break;
2701 case E_FILEENG_TSIF1:
2702 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
2703 break;
2704 case E_FILEENG_TSIF2:
2705 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
2706 break;
2707 case E_FILEENG_TSIF3:
2708 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
2709 break;
2710 default:
2711 break;
2712 }
2713 }
2714 }
2715
HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)2716 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)
2717 {
2718 switch(eFileEng)
2719 {
2720 case E_FILEENG_TSIF0:
2721 return (TSP_CMDQ_SIZE - ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT));
2722 case E_FILEENG_TSIF1:
2723 return (CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT));
2724 case E_FILEENG_TSIF2:
2725 return (CFG_40_REG_TSIF2_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT));
2726 case E_FILEENG_TSIF3:
2727 return (CFG_41_REG_TSIF3_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT));
2728
2729 default:
2730 return 0;
2731 }
2732 }
2733
HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)2734 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)
2735 {
2736 switch(eFileEng)
2737 {
2738 case E_FILEENG_TSIF0:
2739 return ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT);
2740 case E_FILEENG_TSIF1:
2741 return (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT);
2742 case E_FILEENG_TSIF2:
2743 return (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT);
2744 case E_FILEENG_TSIF3:
2745 return (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT);
2746 default:
2747 return 0;
2748 }
2749 }
2750
HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)2751 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)
2752 {
2753 switch(eFileEng)
2754 {
2755 case E_FILEENG_TSIF0:
2756 return ((REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT);
2757 case E_FILEENG_TSIF1:
2758 return ((REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2759 case E_FILEENG_TSIF2:
2760 return ((REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2761 case E_FILEENG_TSIF3:
2762 return ((REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2763 default:
2764 return 0;
2765 }
2766 }
2767
HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng,MS_U32 delay,MS_BOOL bEnable)2768 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable)
2769 {
2770 if(bEnable)
2771 {
2772 switch(eFileEng)
2773 {
2774 case E_FILEENG_TSIF0:
2775 REG32_W(&_RegCtrl->TsFileIn_Timer, delay & TSP_FILE_TIMER_MASK);
2776 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE);
2777 break;
2778 case E_FILEENG_TSIF1:
2779 REG16_W(&_RegCtrl2->CFG_03, delay & CFG_03_TSP_FILE_TIMER1);
2780 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1);
2781 break;
2782 case E_FILEENG_TSIF2:
2783 REG16_W(&_RegCtrl2->CFG_08, delay & CFG_08_TSP_FILE_TIMER2);
2784 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2);
2785 break;
2786 case E_FILEENG_TSIF3:
2787 REG16_W(&_RegCtrl2->CFG_0D, delay & CFG_0D_TSP_FILE_TIMER3);
2788 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3);
2789 break;
2790 default:
2791 break;
2792 }
2793 }
2794 else
2795 {
2796 switch(eFileEng)
2797 {
2798 case E_FILEENG_TSIF0:
2799 REG16_CLR(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE);
2800 REG32_W(&_RegCtrl->TsFileIn_Timer, 0x0000);
2801 break;
2802 case E_FILEENG_TSIF1:
2803 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1);
2804 REG16_W(&_RegCtrl2->CFG_03, 0x0000);
2805 break;
2806 case E_FILEENG_TSIF2:
2807 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2);
2808 REG16_W(&_RegCtrl2->CFG_08, 0x0000);
2809 break;
2810 case E_FILEENG_TSIF3:
2811 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3);
2812 REG16_W(&_RegCtrl2->CFG_0D, 0x0000);
2813 break;
2814 default:
2815 break;
2816 }
2817 }
2818 }
2819
HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)2820 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)
2821 {
2822 switch(eFileEng)
2823 {
2824 case E_FILEENG_TSIF0:
2825 return !(REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_TSDMA_FILEIN_DONE);
2826 case E_FILEENG_TSIF1:
2827 return !(REG16_R(&_RegCtrl2->CFG_34) & CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE);
2828 case E_FILEENG_TSIF2:
2829 return !(REG16_R(&_RegCtrl2->CFG_39) & CFG_39_FILEIN_CTRL_TSIF2_DONE);
2830 case E_FILEENG_TSIF3:
2831 return !(REG16_R(&_RegCtrl2->CFG_3E) & CFG_3E_FILEIN_CTRL_TSIF3_DONE);
2832 default:
2833 return 0;
2834 }
2835 }
2836
2837 // Only used by [HW test code]
2838 /*
2839 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng)
2840 {
2841 return !HAL_TSP_Filein_Status(eFileEng);
2842 }
2843 */
2844
2845 //To do : only tsif0 has pause functionality in Kaiser
HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)2846 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)
2847 {
2848 TSP_HAL_FileState state = E_TSP_HAL_FILE_STATE_INVALID;
2849 MS_U32 u32Status = HAL_TSP_Filein_Status(eFileEng);
2850
2851 // @FIXME in kaiser u01 only tsif0 file eng has pause function
2852 switch (eFileEng)
2853 {
2854 case E_FILEENG_TSIF0:
2855 if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE )
2856 {
2857 state = E_TSP_HAL_FILE_STATE_PAUSE;
2858 }
2859 else if (u32Status)
2860 {
2861 state = E_TSP_HAL_FILE_STATE_BUSY;
2862 }
2863 else
2864 {
2865 state = E_TSP_HAL_FILE_STATE_IDLE;
2866 }
2867 break;
2868 case E_FILEENG_TSIF1:
2869 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF1_FILE_PAUSE)
2870 {
2871 state = E_TSP_HAL_FILE_STATE_PAUSE;
2872 }
2873 else if (u32Status)
2874 {
2875 state = E_TSP_HAL_FILE_STATE_BUSY;
2876 }
2877 else
2878 {
2879 state = E_TSP_HAL_FILE_STATE_IDLE;
2880 }
2881 break;
2882 case E_FILEENG_TSIF2:
2883 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF2_FILE_PAUSE)
2884 {
2885 state = E_TSP_HAL_FILE_STATE_PAUSE;
2886 }
2887 else if (u32Status)
2888 {
2889 state = E_TSP_HAL_FILE_STATE_BUSY;
2890 }
2891 else
2892 {
2893 state = E_TSP_HAL_FILE_STATE_IDLE;
2894 }
2895 break;
2896 case E_FILEENG_TSIF3:
2897 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF3_FILE_PAUSE)
2898 {
2899 state = E_TSP_HAL_FILE_STATE_PAUSE;
2900 }
2901 else if (u32Status)
2902 {
2903 state = E_TSP_HAL_FILE_STATE_BUSY;
2904 }
2905 else
2906 {
2907 state = E_TSP_HAL_FILE_STATE_IDLE;
2908 }
2909 break;
2910 default:
2911 state = E_TSP_HAL_FILE_STATE_INVALID;
2912 break;
2913 }
2914 return state;
2915 }
2916
HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)2917 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)
2918 {
2919 if(bSet)
2920 {
2921 switch(eFileEng)
2922 {
2923 case E_FILEENG_TSIF0:
2924 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN);
2925 break;
2926 case E_FILEENG_TSIF1:
2927 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1);
2928 break;
2929 case E_FILEENG_TSIF2:
2930 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2);
2931 break;
2932 case E_FILEENG_TSIF3:
2933 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3);
2934 break;
2935 default:
2936 break;
2937 }
2938 }
2939 else
2940 {
2941 switch(eFileEng)
2942 {
2943 case E_FILEENG_TSIF0:
2944 REG16_CLR(&_RegCtrl->reg160C, TSP_FILEIN192_EN);
2945 break;
2946 case E_FILEENG_TSIF1:
2947 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1);
2948 break;
2949 case E_FILEENG_TSIF2:
2950 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2);
2951 break;
2952 case E_FILEENG_TSIF3:
2953 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3);
2954 break;
2955 default:
2956 break;
2957 }
2958 }
2959
2960 }
2961
HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng,MS_BOOL bEn)2962 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn)
2963 {
2964 if(bEn)
2965 {
2966 switch(eFileEng)
2967 {
2968 case E_FILEENG_TSIF0:
2969 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN);
2970 break;
2971 case E_FILEENG_TSIF1:
2972 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1);
2973 break;
2974 case E_FILEENG_TSIF2:
2975 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2);
2976 break;
2977 case E_FILEENG_TSIF3:
2978 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3);
2979 default:
2980 break;
2981 }
2982 }
2983 else
2984 {
2985 switch(eFileEng)
2986 {
2987 case E_FILEENG_TSIF0:
2988 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN);
2989 break;
2990 case E_FILEENG_TSIF1:
2991 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1);
2992 break;
2993 case E_FILEENG_TSIF2:
2994 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2);
2995 break;
2996 case E_FILEENG_TSIF3:
2997 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3);
2998 break;
2999 default:
3000 break;
3001 }
3002 }
3003 }
3004
3005 #if 0
3006 static void _HAL_TSP_FILEIN_ResetPktTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32InitTimeStamp)
3007 {
3008 switch(eFileEng)
3009 {
3010 case E_FILEENG_TSIF0:
3011 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0);
3012 REG32_W(&_RegCtrl6->CFG6_50_51, u32InitTimeStamp);
3013 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0);
3014 break;
3015 case E_FILEENG_TSIF1:
3016 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1);
3017 REG32_W(&_RegCtrl6->CFG6_52_53, u32InitTimeStamp);
3018 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1);
3019 break;
3020 case E_FILEENG_TSIF2:
3021 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2);
3022 REG32_W(&_RegCtrl6->CFG6_54_55, u32InitTimeStamp);
3023 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2);
3024 break;
3025 case E_FILEENG_TSIF3:
3026 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_3);
3027 REG32_W(&_RegCtrl6->CFG6_56_57, u32InitTimeStamp);
3028 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_3);
3029 break;
3030 default:
3031 break;
3032 }
3033 }
3034 #endif
3035
HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng,MS_U32 u32Stamp)3036 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp)
3037 {
3038 switch(eFileEng)
3039 {
3040 case E_FILEENG_TSIF0:
3041 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD);
3042 REG32_W(&_RegCtrl->LPcr2, u32Stamp);
3043 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_WLD);
3044 break;
3045 case E_FILEENG_TSIF1:
3046 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1);
3047 REG32_W(&_RegCtrl2->CFG_50_51, u32Stamp);
3048 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1);
3049 break;
3050 case E_FILEENG_TSIF2:
3051 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2);
3052 REG32_W(&_RegCtrl2->CFG_52_53, u32Stamp);
3053 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2);
3054 break;
3055 case E_FILEENG_TSIF3:
3056 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3);
3057 REG32_W(&_RegCtrl2->CFG_54_55, u32Stamp);
3058 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3);
3059 break;
3060 default:
3061 break;
3062 }
3063
3064 // Fix pass_pkt_timestamp will hang issue by TSP8,0x60[3] : reg_init_timestamp_restart_en
3065 // _HAL_TSP_FILEIN_ResetPktTimeStamp(eFileEng, 0);
3066 }
3067
HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng,TSP_HAL_TimeStamp_Clk eTimeStampClk)3068 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk)
3069 {
3070 switch(eFileEng)
3071 {
3072 case E_FILEENG_TSIF0:
3073 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
3074 {
3075 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M);
3076 }
3077 else
3078 {
3079 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M);
3080 }
3081 break;
3082 case E_FILEENG_TSIF1:
3083 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
3084 {
3085 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M);
3086 }
3087 else
3088 {
3089 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M);
3090 }
3091 break;
3092 case E_FILEENG_TSIF2:
3093 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
3094 {
3095 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M);
3096 }
3097 else
3098 {
3099 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M);
3100 }
3101 break;
3102 case E_FILEENG_TSIF3:
3103 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
3104 {
3105 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF3_C27M);
3106 }
3107 else
3108 {
3109 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF3_C27M);
3110 }
3111 break;
3112 default:
3113 break;
3114 }
3115 }
3116
HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)3117 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)
3118 {
3119 MS_U32 u32Stamp = 0;
3120 switch(eFileEng)
3121 {
3122 case E_FILEENG_TSIF0:
3123 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_RLD);
3124 u32Stamp = REG32_R(&_RegCtrl->LPcr2);
3125 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD);
3126 break;
3127 case E_FILEENG_TSIF1:
3128 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1);
3129 u32Stamp = REG32_R(&_RegCtrl2->CFG_50_51);
3130 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1);
3131 break;
3132 case E_FILEENG_TSIF2:
3133 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2);
3134 u32Stamp = REG32_R(&_RegCtrl2->CFG_52_53);
3135 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2);
3136 break;
3137 case E_FILEENG_TSIF3:
3138 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3);
3139 u32Stamp = REG32_R(&_RegCtrl2->CFG_54_55);
3140 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3);
3141 break;
3142 default:
3143 u32Stamp = 0;
3144 break;
3145 }
3146 return u32Stamp;
3147 }
3148
HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)3149 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)
3150 {
3151 switch(eFileEng)
3152 {
3153 case E_FILEENG_TSIF0:
3154 return REG32_R(&_RegCtrl->TimeStamp_FileIn);
3155 case E_FILEENG_TSIF1:
3156 return REG32_R(&_RegCtrl2->CFG_42_43);
3157 case E_FILEENG_TSIF2:
3158 return REG32_R(&_RegCtrl2->CFG_44_45);
3159 case E_FILEENG_TSIF3:
3160 return REG32_R(&_RegCtrl2->CFG_46_47);
3161 default:
3162 break;
3163 }
3164 return 0;
3165 }
3166
HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng,MS_PHY * pu32Addr)3167 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr)
3168 {
3169 switch(eFileEng)
3170 {
3171 case E_FILEENG_TSIF0:
3172 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl->TsFileIn_RPtr) & TSP_FILE_RPTR_MASK);
3173 break;
3174 case E_FILEENG_TSIF1:
3175 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6A_6B) & CFG_6A_6B_TSP2MI_RADDR_S_TSIF1);
3176 break;
3177 case E_FILEENG_TSIF2:
3178 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6C_6D) & CFG_6C_6D_TSP2MI_RADDR_S_TSIF2);
3179 break;
3180 case E_FILEENG_TSIF3:
3181 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6E_6F) & CFG_6E_6F_TSP2MI_RADDR_S_TSIF3);
3182 break;
3183 default:
3184 break;
3185 }
3186
3187 }
3188
HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)3189 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
3190 {
3191 if(bEnable)
3192 {
3193 switch(eFileEng)
3194 {
3195 case E_FILEENG_TSIF0:
3196 REG16_SET(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_RESET);
3197 break;
3198 case E_FILEENG_TSIF1:
3199 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1);
3200 break;
3201 case E_FILEENG_TSIF2:
3202 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2);
3203 break;
3204 case E_FILEENG_TSIF3:
3205 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3);
3206 break;
3207 default:
3208 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng: %uld !\n",__FILE__,__FUNCTION__,__LINE__,(MS_U32)eFileEng));
3209 break;
3210 }
3211 }
3212 else
3213 {
3214 switch(eFileEng)
3215 {
3216 case E_FILEENG_TSIF0:
3217 REG16_CLR(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_RESET);
3218 break;
3219 case E_FILEENG_TSIF1:
3220 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1);
3221 break;
3222 case E_FILEENG_TSIF2:
3223 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2);
3224 break;
3225 case E_FILEENG_TSIF3:
3226 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3);
3227 break;
3228 default:
3229 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng: %uld !\n",__FILE__,__FUNCTION__,__LINE__,(MS_U32)eFileEng));
3230 break;
3231 }
3232 }
3233 }
3234
HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng,MS_BOOL bEnable,MS_U32 u32Key)3235 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key)
3236 {
3237 if(bEnable)
3238 {
3239 switch(eFileEng)
3240 {
3241 case E_FILEENG_TSIF0:
3242 REG16_W(&_RegCtrl->Mobf_Filein_Idx, (u32Key & TSP_MOBF_FILEIN_MASK));
3243 break;
3244 case E_FILEENG_TSIF1:
3245 REG16_W(&_RegCtrl2->CFG_75, (u32Key & CFG_75_FI_MOBF_INDEC_TSIF1_MASK));
3246 break;
3247 case E_FILEENG_TSIF2:
3248 REG16_W(&_RegCtrl2->CFG_76, (u32Key & CFG_76_FI_MOBF_INDEC_TSIF2_MASK));
3249 break;
3250 case E_FILEENG_TSIF3:
3251 REG16_W(&_RegCtrl2->CFG_77, (u32Key & CFG_77_FI_MOBF_INDEC_TSIF3_MASK));
3252 break;
3253 default:
3254 break;
3255 }
3256 }
3257 else
3258 {
3259 switch(eFileEng)
3260 {
3261 case E_FILEENG_TSIF0:
3262 REG16_W(&_RegCtrl->Mobf_Filein_Idx, 0);
3263 break;
3264 case E_FILEENG_TSIF1:
3265 REG16_W(&_RegCtrl2->CFG_75, 0);
3266 break;
3267 case E_FILEENG_TSIF2:
3268 REG16_W(&_RegCtrl2->CFG_76, 0);
3269 break;
3270 case E_FILEENG_TSIF3:
3271 REG16_W(&_RegCtrl2->CFG_77, 0);
3272 break;
3273 default:
3274 break;
3275 }
3276 }
3277 }
3278
HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)3279 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
3280 {
3281 switch (ePidFltSrc)
3282 {
3283 case E_TSP_PIDFLT_LIVE0:
3284 return TSP_PIDFLT_TSIF0;
3285 case E_TSP_PIDFLT_LIVE1:
3286 return TSP_PIDFLT_TSIF2;
3287 case E_TSP_PIDFLT_LIVE2:
3288 return TSP_PIDFLT_TSIF3;
3289 case E_TSP_PIDFLT_LIVE3:
3290 return TSP_PIDFLT_TSIF1;
3291 case E_TSP_PIDFLT_FILE0:
3292 return TSP_PIDFLT_TSIF1;
3293 case E_TSP_PIDFLT_FILE1:
3294 return TSP_PIDFLT_TSIF3;
3295 case E_TSP_PIDFLT_FILE2:
3296 return TSP_PIDFLT_TSIF0;
3297 case E_TSP_PIDFLT_FILE3:
3298 return TSP_PIDFLT_TSIF2;
3299 default:
3300 printf("[TSP_ERR][%s][%d] Wrong filter source!!!\n",__FUNCTION__, __LINE__);
3301 break;
3302 }
3303
3304 return 0;
3305 }
3306
HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId,MS_U32 u32FltIn)3307 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn)
3308 {
3309 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
3310 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_IN_MASK) | ((u32FltIn << TSP_PIDFLT_TSIF_SHFT) & TSP_PIDFLT_IN_MASK));
3311 }
3312
HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId,MS_U32 u32FltOut)3313 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut)
3314 {
3315 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3316 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_OUT_MASK)) | (u32FltOut & TSP_PIDFLT_OUT_MASK)));
3317 }
3318
HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId,MS_U32 u32SrcID)3319 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID)
3320 {
3321 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3322 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcID << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
3323 }
3324
HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId,MS_U32 u32SecFltId)3325 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId)
3326 {
3327 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3328 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_SECFLT_MASK) | ((u32SecFltId << TSP_PIDFLT_SECFLT_SHFT) & TSP_PIDFLT_SECFLT_MASK));
3329 }
3330
HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId,MS_U32 u32PVREng,MS_BOOL bEn)3331 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn)
3332 {
3333 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3334 if(bEn)
3335 {
3336 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK) | (((1 << u32PVREng) << TSP_PIDFLT_PVRFLT_SHFT) & TSP_PIDFLT_PVRFLT_MASK));
3337 }
3338 else
3339 {
3340 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK));
3341 }
3342 }
3343
HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId,MS_U8 u8Enable)3344 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable)
3345 {
3346 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3347 if(u8Enable)
3348 TSP32_IdrW( pPidFlt, TSP32_IdrR(pPidFlt) | (TSP_PID_FLT_PKTPUSH_PASS));
3349 else
3350 TSP32_IdrW( pPidFlt, TSP32_IdrR(pPidFlt) & ~(TSP_PID_FLT_PKTPUSH_PASS));
3351 }
3352
HAL_TSP_PidFlt_SetPid(MS_U32 fltId,MS_U32 u32Pid)3353 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32Pid)
3354 {
3355 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
3356 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PID_MASK) | ((u32Pid << TSP_PIDFLT_PID_SHFT) & TSP_PIDFLT_PID_MASK));
3357 }
3358
3359 //-------------------------------------------------------------------------------------------------
3360 // For section filter part
3361 //-------------------------------------------------------------------------------------------------
3362
HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)3363 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)
3364 {
3365 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN);
3366 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT));
3367 }
3368
HAL_TSP_SecFlt_SetType(REG_SecFlt * pSecFlt,MS_U32 u32FltType)3369 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType)
3370 {
3371 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_USER_MASK) | (u32FltType << TSP_SECFLT_USER_SHFT));
3372 }
3373
3374
HAL_TSP_SecFlt_SetMode(REG_SecFlt * pSecFlt,MS_U32 u32SecFltMode)3375 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode)
3376 {
3377 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_MASK) | ((u32SecFltMode << TSP_SECFLT_MODE_SHFT) & TSP_SECFLT_MODE_MASK));
3378 }
3379
3380
3381 // match mask --> 0 will compare
HAL_TSP_SecFlt_SetMask(REG_SecFlt * pSecFlt,MS_U8 * pu8Mask)3382 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask)
3383 {
3384 MS_U32 i,j;
3385 MS_U32 u32Temp;
3386
3387 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3388 {
3389 j = (i<< 2);
3390 u32Temp = (pu8Mask[j]) | (pu8Mask[j+ 1] << 8 ) | (pu8Mask[j+ 2] << 16 )| (pu8Mask[j+ 3] << 24);
3391 TSP32_IdrW((TSP32 *)&pSecFlt->Mask[i], u32Temp);
3392 }
3393 }
3394
3395
3396 // not match mask --> 1 will compare
HAL_TSP_SecFlt_SetNMask(REG_SecFlt * pSecFlt,MS_U8 * pu8NMask)3397 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask)
3398 {
3399 MS_U32 i,j;
3400 MS_U32 u32Temp;
3401
3402 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3403 {
3404 j = (i<< 2);
3405 u32Temp = (pu8NMask[j]) | (pu8NMask[j+ 1] << 8 ) | (pu8NMask[j+ 2] << 16 )| (pu8NMask[j+ 3] << 24);
3406 TSP32_IdrW((TSP32 *)&pSecFlt->NMask[i], u32Temp);
3407 }
3408 }
3409
3410
HAL_TSP_SecFlt_SetMatch(REG_SecFlt * pSecFlt,MS_U8 * pu8Match)3411 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match)
3412 {
3413 MS_U32 i,j;
3414 MS_U32 u32Temp;
3415
3416 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3417 {
3418 j = (i<< 2);
3419 u32Temp = (pu8Match[j]) | (pu8Match[j+ 1] << 8 ) | (pu8Match[j+ 2] << 16 )| (pu8Match[j+ 3] << 24);
3420 TSP32_IdrW((TSP32 *)&pSecFlt->Match[i], u32Temp);
3421 }
3422 }
3423
3424
3425 //[LIMIT] Is impossible to identify the pidfilter is assigned a secfilter/buffer or not
HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt * pSecFlt,MS_U16 u16BufId)3426 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId)
3427 {
3428 TSP32_IdrW( &pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_SECBUF_MASK)
3429 | ((u16BufId << TSP_SECFLT_SECBUF_SHFT) & TSP_SECFLT_SECBUF_MASK) );
3430 }
3431
3432
HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt * pSecFlt)3433 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt)
3434 {
3435 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_SECBUF_MASK) >> TSP_SECFLT_SECBUF_SHFT);
3436 }
3437
HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt * pPidFlt)3438 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt)
3439 {
3440 return (TSP32_IdrR(pPidFlt) & TSP_PIDFLT_OUT_MASK);
3441 }
3442
HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)3443 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)
3444 {
3445 // don't have to implement no reference
3446 }
3447
3448
3449 // @FIXME: Is it secflt or secbuf?
HAL_TSP_SecFlt_ResetState(REG_SecFlt * pSecFlt)3450 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt)
3451 {
3452 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~(TSP_SECFLT_STATE_MASK));
3453 }
3454
3455
HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt * pSecFlt)3456 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt)
3457 {
3458 TSP32_IdrW(&pSecFlt->Ctrl, 0);
3459 }
3460
HAL_TSP_SecFlt_GetState(REG_SecFlt * pSecFlt)3461 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt)
3462 {
3463 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_STATE_MASK) >> TSP_SECFLT_STATE_SHFT);
3464 }
3465
3466
HAL_TSP_SecFlt_GetMode(REG_SecFlt * pSecFlt)3467 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFlt)
3468 {
3469 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_MODE_MASK) >> TSP_SECFLT_MODE_SHFT);
3470 }
3471
3472
HAL_TSP_SecFlt_PcrReset(REG_SecFlt * pSecFlt)3473 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFlt)
3474 {
3475 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_PCRRST);
3476 }
3477
3478
HAL_TSP_SecFlt_TryAlloc(REG_SecFlt * pSecFlt,MS_U16 u16TSPId)3479 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId)
3480 {
3481 MS_U32 reg;
3482
3483 //_TSP_HW_Lock();
3484
3485 // rmn counter doesn't need 32bit (check 13818) so we use some of it to store owner and alloc info
3486 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & (TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
3487 if (reg & TSP_SECFLT_ALLOC_MASK)
3488 {
3489 //_TSP_HW_Unlock();
3490 return FALSE;
3491 }
3492 reg |= TSP_SECFLT_ALLOC_MASK | ((u16TSPId<<TSP_SECFLT_OWNER_SHFT) & TSP_SECFLT_OWNER_MASK);
3493 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
3494
3495 //_TSP_HW_Unlock();
3496 return TRUE;
3497 }
3498
3499
HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt * pSecFlt,MS_BOOL bSet)3500 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet)
3501 {
3502 if(bSet)
3503 {
3504 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_MODE_AUTO_CRCCHK);
3505 }
3506 else
3507 {
3508 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_AUTO_CRCCHK);
3509 }
3510 }
3511
3512
HAL_TSP_SecFlt_Free(REG_SecFlt * pSecFlt)3513 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt)
3514 {
3515 MS_U32 reg;
3516
3517 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
3518 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
3519 }
3520
HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt * pSecFlt)3521 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt)
3522 {
3523 TSP32_IdrW(&pSecFlt->RmnCnt, TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECBUF_RMNCNT_MASK));
3524 }
3525
3526 //-------------------------------------------------------------------------------------------------
3527 // For section buffer part
3528 //-------------------------------------------------------------------------------------------------
HAL_TSP_SecBuf_SetBuf(REG_SecBuf * pSecBuf,MS_U32 u32StartAddr,MS_U32 u32BufSize)3529 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize)
3530 {
3531 // Check MIU select
3532 MS_U8 u8MiuSel;
3533 MS_PHY phyMiuOffsetSecBuf;
3534 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetSecBuf, u32StartAddr);
3535 REG16_W(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW, (REG16_R(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW) & (~REG_MIU_SEL_SECTION_MASK)) | ((u8MiuSel << REG_MIU_SEL_SECTION_SHIFT) & REG_MIU_SEL_SECTION_MASK));
3536
3537 MS_U32 owner;
3538 // To avoid SW read hidden HW byte enable information.
3539 owner = TSP32_IdrR(&pSecBuf->Start); // @FIXME local variable but not used?
3540
3541 TSP32_IdrW(&pSecBuf->Start, phyMiuOffsetSecBuf);
3542 TSP32_IdrW(&pSecBuf->End, phyMiuOffsetSecBuf + u32BufSize);
3543 }
3544
3545
HAL_TSP_SecBuf_SetRead(REG_SecBuf * pSecBuf,MS_U32 u32ReadAddr)3546 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr)
3547 {
3548 TSP32_IdrW(&pSecBuf->Read, u32ReadAddr);
3549 }
3550
3551
HAL_TSP_SecBuf_GetStart(REG_SecBuf * pSecBuf)3552 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf)
3553 {
3554 return TSP32_IdrR(&pSecBuf->Start);
3555 }
3556
3557
HAL_TSP_SecBuf_GetEnd(REG_SecBuf * pSecBuf)3558 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf)
3559 {
3560 return TSP32_IdrR(&pSecBuf->End);
3561 }
3562
3563
HAL_TSP_SecBuf_GetBufCur(REG_SecBuf * pSecBuf)3564 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf)
3565 {
3566 //BufCur is control by firmware
3567 //we use Cur pointer to receive the newest data
3568 //and use write pointer to guarantee that the data between
3569 //read and write pointer is correct, so that user won't get
3570 //unverified data.
3571 return TSP32_IdrR(&pSecBuf->Cur);
3572 }
3573
3574
HAL_TSP_SecBuf_Reset(REG_SecBuf * pSecBuf)3575 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf)
3576 {
3577 MS_U32 start;
3578
3579 start = TSP32_IdrR(&pSecBuf->Start);
3580
3581 TSP32_IdrW(&pSecBuf->Cur, start);
3582 TSP32_IdrW(&pSecBuf->Read, start);
3583 TSP32_IdrW(&pSecBuf->Write, start);
3584
3585 start = ( (MS_VIRT)pSecBuf - (MS_VIRT)REG_SECBUF_BASE ) / sizeof(REG_SecBuf) ;
3586 HAL_TSP_HCMD_BufRst(start); // @FIXME seems we don't need to do this
3587 }
3588
3589
HAL_TSP_SecBuf_GetRead(REG_SecBuf * pSecBuf)3590 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf)
3591 {
3592 return TSP32_IdrR((TSP32*)&pSecBuf->Read);
3593 }
3594
3595
HAL_TSP_SecBuf_GetWrite(REG_SecBuf * pSecBuf)3596 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf)
3597 {
3598 return TSP32_IdrR((TSP32*)&pSecBuf->Write);
3599 }
3600
3601
HAL_TSP_SecBuf_TryAlloc(REG_SecBuf * pSecBuf,MS_U16 u16TSPId)3602 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId)
3603 {
3604 // @TODO make sure the owner and alloc info is necessary or not.
3605 MS_U32 reg;
3606
3607 //_TSP_HW_Lock();
3608
3609 reg = TSP32_IdrR(&pSecBuf->Start) & (TSP_SECBUF_OWNER_MASK | TSP_SECBUF_ALLOC_MASK);
3610 //if (reg & TSP_SECBUF_ALLOC_MASK)
3611 //{
3612 // //_TSP_HW_Unlock();
3613 // return FALSE;
3614 //}
3615 reg |= TSP_SECBUF_ALLOC_MASK | ((u16TSPId<<TSP_SECBUF_OWNER_SHFT) & TSP_SECBUF_OWNER_MASK);
3616 //TSP32_IdrW(&pSecBuf->Start, reg);
3617
3618 //_TSP_HW_Unlock();
3619 return TRUE;
3620 }
3621
3622
HAL_TSP_SecBuf_Free(REG_SecBuf * pSecBuf)3623 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf)
3624 {
3625 // @TODO ref to HAL_TSP_SecBuf_TryAlloc
3626 TSP32_IdrW(&pSecBuf->Start, 0x0);
3627 }
3628
HAL_TSP_PidFlt_GetPid(REG_PidFlt * pPidFlt)3629 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt)
3630 {
3631 return ((TSP32_IdrR(pPidFlt) & TSP_PIDFLT_PID_MASK) >> TSP_PIDFLT_PID_SHFT);
3632 }
3633
HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId,MS_BOOL bEnable)3634 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable)
3635 {
3636 switch(pcrFltId)
3637 {
3638 case 0:
3639 if(bEnable)
3640 {
3641 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN);
3642 }
3643 else
3644 {
3645 REG16_CLR(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN);
3646 }
3647 break;
3648 case 1:
3649 if(bEnable)
3650 {
3651 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN);
3652 }
3653 else
3654 {
3655 REG16_CLR(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN);
3656 }
3657 break;
3658 case 2:
3659 if(bEnable)
3660 {
3661 REG16_SET(&_RegCtrl8_1->CFG8_44, CFG8_44_PIDFLT_PCR2_EN);
3662 }
3663 else
3664 {
3665 REG16_CLR(&_RegCtrl8_1->CFG8_44, CFG8_44_PIDFLT_PCR2_EN);
3666 }
3667 break;
3668 case 3:
3669 if(bEnable)
3670 {
3671 REG16_SET(&_RegCtrl8_1->CFG8_45, CFG8_45_PIDFLT_PCR3_EN);
3672 }
3673 else
3674 {
3675 REG16_CLR(&_RegCtrl8_1->CFG8_45, CFG8_45_PIDFLT_PCR3_EN);
3676 }
3677 break;
3678 default:
3679 break;
3680 }
3681 }
3682
HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId,MS_U32 u32Pid)3683 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid)
3684 {
3685 switch(pcrFltId)
3686 {
3687 case 0:
3688 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_PID_MASK, u32Pid);
3689 break;
3690 case 1:
3691 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_PID_MASK, u32Pid);
3692 break;
3693 case 2:
3694 REG16_MSK_W(&_RegCtrl8_1->CFG8_44, CFG8_44_PIDFLT_PCR2_PID_MASK, u32Pid);
3695 break;
3696 case 3:
3697 REG16_MSK_W(&_RegCtrl8_1->CFG8_45, CFG8_45_PIDFLT_PCR3_PID_MASK, u32Pid);
3698 break;
3699 default:
3700 break;
3701 }
3702
3703 }
3704
HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)3705 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)
3706 {
3707 switch(pcrFltId)
3708 {
3709 case 0:
3710 return (REG16_R(&_RegCtrl->PIDFLT_PCR0) & TSP_PIDFLT_PCR0_PID_MASK);
3711 case 1:
3712 return (REG16_R(&_RegCtrl->PIDFLT_PCR1) & TSP_PIDFLT_PCR1_PID_MASK);
3713 case 2:
3714 return (REG16_R(&_RegCtrl8_1->CFG8_44) & CFG8_44_PIDFLT_PCR2_PID_MASK);
3715 case 3:
3716 return (REG16_R(&_RegCtrl8_1->CFG8_45) & CFG8_45_PIDFLT_PCR3_PID_MASK);
3717 default:
3718 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] PCR flt id not support !!\n",__FUNCTION__,__LINE__));
3719 return PVR_PIDFLT_DEF;
3720 }
3721 }
3722
HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId,TSP_PCR_SRC src)3723 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src)
3724 {
3725 switch(pcrFltId)
3726 {
3727 case 0:
3728 //src 0
3729 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR0_SRC_MASK, src << CFG_01_PCR0_SRC_SHIFT);
3730 break;
3731 case 1:
3732 //src 1
3733 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR1_SRC_MASK, src << CFG_01_PCR1_SRC_SHIFT);
3734 break;
3735 case 2:
3736 //src 2
3737 REG16_MSK_W(&_RegCtrl8_1->CFG8_42, CFG8_42_PCR2_SRC_MASK, src << CFG8_42_PCR2_SRC_SHIFT);
3738 break;
3739 case 3:
3740 //src 3
3741 REG16_MSK_W(&_RegCtrl8_1->CFG8_43, CFG8_43_PCR3_SRC_MASK, src << CFG8_43_PCR3_SRC_SHIFT);
3742 break;
3743 default:
3744 break;
3745 }
3746 }
3747
HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId,MS_U32 u32SrcId)3748 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId)
3749 {
3750 switch(pcrFltId)
3751 {
3752 case 0:
3753 REG16_MSK_W(&_RegCtrl3->CFG3_72, CFG3_72_PIDFLT_PCR0_SRC_ID_MASK, u32SrcId<<CFG3_72_PIDFLT_PCR0_SRC_ID_SHIFT);
3754 break;
3755 case 1:
3756 REG16_MSK_W(&_RegCtrl3->CFG3_72, CFG3_72_PIDFLT_PCR1_SRC_ID_MASK, u32SrcId<<CFG3_72_PIDFLT_PCR1_SRC_ID_SHIFT);
3757 break;
3758 case 2:
3759 REG16_MSK_W(&_RegCtrl8_1->CFG8_46, CFG8_46_REG_PIDFLT_PCR2_SRC_ID_MASK, u32SrcId<<CFG8_46_REG_PIDFLT_PCR2_SRC_ID_SHIFT);
3760 break;
3761 case 3:
3762 REG16_MSK_W(&_RegCtrl8_1->CFG8_46, CFG8_46_REG_PIDFLT_PCR3_SRC_ID_MASK, u32SrcId<<CFG8_46_REG_PIDFLT_PCR3_SRC_ID_SHIFT);
3763 break;
3764 default:
3765 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
3766 break;
3767 }
3768 }
3769
HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId,TSP_PCR_SRC * pPcrSrc)3770 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc)
3771 {
3772 switch(pcrFltId)
3773 {
3774 case 0:
3775 //src 0
3776 *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR0_SRC_MASK) >> CFG_01_PCR0_SRC_SHIFT;
3777 break;
3778 case 1:
3779 //src 1
3780 *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR1_SRC_MASK) >> CFG_01_PCR1_SRC_SHIFT;
3781 break;
3782 case 2:
3783 //src 2
3784 *pPcrSrc = (REG16_R(&_RegCtrl8_1->CFG8_42) & CFG8_42_PCR2_SRC_MASK) >> CFG8_42_PCR2_SRC_SHIFT;
3785 break;
3786 case 3:
3787 //src 3
3788 *pPcrSrc = (REG16_R(&_RegCtrl8_1->CFG8_43) & CFG8_43_PCR3_SRC_MASK) >> CFG8_43_PCR3_SRC_SHIFT;
3789 break;
3790 default:
3791 break;
3792 }
3793 }
3794
HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)3795 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
3796 {
3797 TSP_PCR_SRC ePcrSrc = E_TSP_PCR_SRC_INVALID;
3798 switch(ePidFltSrc)
3799 {
3800 case E_TSP_PIDFLT_LIVE0:
3801 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
3802 break;
3803 case E_TSP_PIDFLT_LIVE1:
3804 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
3805 break;
3806 case E_TSP_PIDFLT_LIVE2:
3807 ePcrSrc = E_TSP_PCR_SRC_TSIF3;
3808 break;
3809 case E_TSP_PIDFLT_LIVE3:
3810 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
3811 break;
3812 case E_TSP_PIDFLT_FILE0:
3813 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
3814 break;
3815 case E_TSP_PIDFLT_FILE1:
3816 ePcrSrc = E_TSP_PCR_SRC_TSIF3;
3817 break;
3818 case E_TSP_PIDFLT_FILE2:
3819 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
3820 break;
3821 case E_TSP_PIDFLT_FILE3:
3822 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
3823 break;
3824 default:
3825 printf("[TSP_ERR][%s][%d] Wrong Flt Src type!!!\n",__FUNCTION__,__LINE__);
3826 break;
3827 }
3828 return ePcrSrc;
3829
3830 }
3831
3832
HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId,MS_U32 * pu32Pcr_H,MS_U32 * pu32Pcr)3833 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr)
3834 {
3835 switch(pcrFltId)
3836 {
3837 case 0:
3838 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ);
3839 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR0_L);
3840 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR0_H) & 0x1;
3841 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ);
3842 break;
3843 case 1:
3844 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ);
3845 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR1_L);
3846 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR1_H) & 0x1;
3847 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ);
3848 break;
3849 case 2:
3850 REG16_SET(&_RegCtrl8_1->CFG8_42, CFG8_42_REG_PCR2_READ);
3851 *pu32Pcr = REG32_R(&_RegCtrl8_1->CFG8_60_61);
3852 *pu32Pcr_H = (MS_U32)(REG16_R(&_RegCtrl8_1->CFG8_62) & 0x1);
3853 REG16_CLR(&_RegCtrl8_1->CFG8_42, CFG8_42_REG_PCR2_READ);
3854 break;
3855 case 3:
3856 REG16_SET(&_RegCtrl8_1->CFG8_43, CFG8_43_REG_PCR3_READ);
3857 *pu32Pcr = REG32_R(&_RegCtrl8_1->CFG8_63_64);
3858 *pu32Pcr_H = (MS_U32)(REG16_R(&_RegCtrl8_1->CFG8_65) & 0x1);
3859 REG16_CLR(&_RegCtrl8_1->CFG8_43, CFG8_43_REG_PCR3_READ);
3860 break;
3861
3862 default:
3863 break;
3864 }
3865 }
3866
HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)3867 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)
3868 {
3869 switch(pcrFltId)
3870 {
3871 case 0:
3872 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET);
3873 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET);
3874 break;
3875 case 1:
3876 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET);
3877 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET);
3878 break;
3879 case 2:
3880 REG16_CLR(&_RegCtrl8_1->CFG8_42, CFG8_42_REG_PCR2_RESET);
3881 REG16_SET(&_RegCtrl8_1->CFG8_42, CFG8_42_REG_PCR2_RESET);
3882 break;
3883 case 3:
3884 REG16_CLR(&_RegCtrl8_1->CFG8_43, CFG8_43_REG_PCR3_RESET);
3885 REG16_SET(&_RegCtrl8_1->CFG8_43, CFG8_43_REG_PCR3_RESET);
3886 break;
3887 default:
3888 break;
3889 }
3890 }
3891
3892
HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)3893 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)
3894 {
3895 switch(pcrFltId)
3896 {
3897 case 0:
3898 //REG16_CLR(&_RegCtrl->HwInt2_Stat,TSP_HWINT2_PCR0_UPDATE_END);
3899 REG16_W(&_RegCtrl->HwInt2_Stat,
3900 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) |
3901 (~TSP_HWINT2_PCR0_UPDATE_END & TSP_HWINT2_STATUS_MASK));
3902 break;
3903 case 1:
3904 //REG16_CLR(&_RegCtrl->HwInt2_Stat,TSP_HWINT2_PCR1_UPDATE_END);
3905 REG16_W(&_RegCtrl->HwInt2_Stat,
3906 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) |
3907 (~TSP_HWINT2_PCR1_UPDATE_END & TSP_HWINT2_STATUS_MASK));
3908 break;
3909 case 2:
3910 //REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT2_PCR2_UPDATE_END);
3911 REG16_W(&_RegCtrl->HwInt3_Stat,
3912 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) |
3913 (~TSP_HWINT3_PCR2_UPDATE_END & TSP_HWINT3_STATUS_MASK));
3914 break;
3915 case 3:
3916 //REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT2_PCR3_UPDATE_END);
3917 REG16_W(&_RegCtrl->HwInt3_Stat,
3918 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) |
3919 (~TSP_HWINT3_PCR3_UPDATE_END & TSP_HWINT3_STATUS_MASK));
3920 break;
3921 default:
3922 break;
3923 }
3924 }
3925
HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)3926 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)
3927 {
3928 switch(pcrFltId)
3929 {
3930 case 0:
3931 return (TSP_HWINT2_PCR0_UPDATE_END_EN << 8);
3932 case 1:
3933 return (TSP_HWINT2_PCR1_UPDATE_END_EN << 8);
3934 case 2:
3935 return (TSP_HWINT3_PCR2_UPDATE_END_EN << 16);
3936 case 3:
3937 return (TSP_HWINT3_PCR3_UPDATE_END_EN << 16);
3938 default:
3939 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP ERROR][%s][%d] PCR flt id not support !!\n",__FUNCTION__,__LINE__));
3940 return 0;
3941 }
3942 }
3943
HAL_TSP_STC_Init(void)3944 void HAL_TSP_STC_Init(void)
3945 {
3946 /////////////Set STC control by HK////////////////
3947 // select synth from chip top : bit 1 -> 0 -> controlled by HK
3948 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
3949 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
3950 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC2_CW_SEL;
3951 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC3_CW_SEL;
3952
3953 // set HK STC synth CW
3954 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
3955 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000;
3956 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800;
3957 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000;
3958 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = 0x2800;
3959 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = 0x0000;
3960 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = 0x2800;
3961 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = 0x0000;
3962 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = 0x2800;
3963
3964 // set STC synth
3965 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3966 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
3967 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3968 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3969 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
3970 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3971 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC2_CW_EN);
3972 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC2_CW_EN;
3973 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC2_CW_EN);
3974 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN);
3975 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC3_CW_EN;
3976 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN);
3977
3978 #if 0 // we don't use TSP CPU to control STC anymmore, so we don't have to do the following
3979 /////////////Set STC control by TSP////////////////
3980 // select synth from TSP : bit 1 -> 1 -> controlled by TSP
3981 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;
3982 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL;
3983
3984 // set TSP STC synth CW
3985 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
3986 TSP32_IdrW((TSP32 *)(0x0021024c<<1), 0x28000000);
3987 TSP32_IdrW((TSP32 *)(0x00210280<<1), 0x28000000); //STC1
3988
3989 // t2 , t3 had no 0x0021025c, it was add after t4, eanble synthesizer
3990 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x01);
3991 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x01);
3992 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x02); //STC1
3993 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x02);
3994 #endif
3995 }
3996
HAL_TSP_GetSTCSynth(MS_U32 Eng,MS_U32 * u32Sync)3997 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync)
3998 {
3999 switch (Eng)
4000 {
4001 case 0:
4002 // get HK STC synth CW
4003 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L);
4004 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ;
4005 break;
4006 case 1:
4007 // get HK STC synth CW
4008 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L);
4009 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) << 16 ;
4010 break;
4011 case 2:
4012 // get HK STC synth CW
4013 *u32Sync = TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L);
4014 *u32Sync |= TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) << 16 ;
4015 break;
4016 case 3:
4017 // get HK STC synth CW
4018 *u32Sync = TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L);
4019 *u32Sync |= TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) << 16 ;
4020 break;
4021 }
4022 }
4023
HAL_TSP_SetSTCSynth(MS_U32 Eng,MS_U32 u32Sync)4024 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync)
4025 {
4026 switch (Eng)
4027 {
4028 case 0:
4029 //set STC controller : HK or TSP CPU
4030 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
4031
4032 // set HK STC synth CW
4033 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF;
4034 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16;
4035
4036 // set STC synth : toggle update bit
4037 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
4038 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
4039 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
4040 break;
4041 case 1:
4042 //set STC controller : HK or TSP CPU
4043 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
4044
4045 // set HK STC synth CW
4046 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF;
4047 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = u32Sync >> 16;
4048
4049 // set STC synth : toggle update bit
4050 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
4051 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
4052 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
4053 break;
4054 case 2:
4055 //set STC controller : HK or TSP CPU
4056 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC2_CW_SEL;
4057
4058 // set HK STC synth CW
4059 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = u32Sync & 0xFFFF;
4060 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = u32Sync >> 16;
4061
4062 // set STC synth : toggle update bit
4063 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC2_CW_EN);
4064 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC2_CW_EN;
4065 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC2_CW_EN);
4066 break;
4067 case 3:
4068 //set STC controller : HK or TSP CPU
4069 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC3_CW_SEL;
4070
4071 // set HK STC synth CW
4072 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = u32Sync & 0xFFFF;
4073 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = u32Sync >> 16;
4074
4075 // set STC synth : toggle update bit
4076 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN);
4077 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC3_CW_EN;
4078 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN);
4079 break;
4080 }
4081 }
4082
HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)4083 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)
4084 {
4085 if (bEnable)
4086 {
4087 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
4088 }
4089 else
4090 {
4091 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
4092 }
4093 }
4094
HAL_TSP_STC64_Set(MS_U32 Eng,MS_U32 stcH,MS_U32 stcL)4095 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL)
4096 {
4097 switch (Eng)
4098 {
4099 case 0:
4100 REG32_W(&_RegCtrl->Pcr_L, stcL);
4101 REG32_W(&_RegCtrl->Pcr_H, stcH);
4102 break;
4103 case 1:
4104 REG32_W(&_RegCtrl->PCR64_2_L, stcL);
4105 REG32_W(&_RegCtrl->PCR64_2_H, stcH);
4106 break;
4107 case 2:
4108 REG32_W(&_RegCtrl8_1->CFG8_54_55, stcL);
4109 REG32_W(&_RegCtrl8_1->CFG8_56_57, stcH);
4110 REG16_SET(&_RegCtrl->STC_Config, TSP_STC_CFG_SET_TIME_BASE_64b_3);
4111 REG16_CLR(&_RegCtrl->STC_Config, TSP_STC_CFG_SET_TIME_BASE_64b_3);
4112 break;
4113 case 3:
4114 REG32_W(&_RegCtrl8_1->CFG8_5A_5B, stcL);
4115 REG32_W(&_RegCtrl8_1->CFG8_5C_5D, stcH);
4116 REG16_SET(&_RegCtrl->STC_Config, TSP_STC_CFG_SET_TIME_BASE_64b_4);
4117 REG16_CLR(&_RegCtrl->STC_Config, TSP_STC_CFG_SET_TIME_BASE_64b_4);
4118 break;
4119 }
4120 }
4121
HAL_TSP_STC64_Get(MS_U32 Eng,MS_U32 * pStcH,MS_U32 * pStcL)4122 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL)
4123 {
4124 switch (Eng)
4125 {
4126 case 0:
4127 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
4128 *pStcH = REG32_R(&_RegCtrl->Pcr_H);
4129 *pStcL = REG32_R(&_RegCtrl->Pcr_L);
4130 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
4131 break;
4132 case 1:
4133 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
4134 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H);
4135 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L);
4136 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
4137 break;
4138 case 2:
4139 REG16_CLR(&_RegCtrl->STC_Config, TSP_STC_CFG_CNT64b_3_LD);
4140 *pStcH = REG32_R(&_RegCtrl8_1->CFG8_56_57);
4141 *pStcL = REG32_R(&_RegCtrl8_1->CFG8_54_55);
4142 REG16_SET(&_RegCtrl->STC_Config, TSP_STC_CFG_CNT64b_3_LD);
4143 break;
4144 case 3:
4145 REG16_CLR(&_RegCtrl->STC_Config, TSP_STC_CFG_CNT64b_4_LD);
4146 *pStcH = REG32_R(&_RegCtrl8_1->CFG8_5C_5D);
4147 *pStcL = REG32_R(&_RegCtrl8_1->CFG8_5A_5B);
4148 REG16_SET(&_RegCtrl->STC_Config, TSP_STC_CFG_CNT64b_4_LD);
4149 break;
4150 }
4151 }
4152
HAL_TSP_STC33_CmdQSet(MS_U32 stcH,MS_U32 stcL)4153 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL)
4154 {
4155 // @TODO ask designer for the difference between 64bit STC and 33 Bit STC
4156 // and it's hw limit (like: cmdQ delay)
4157 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H);
4158 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL);
4159 }
4160
HAL_TSP_STC33_CmdQGet(MS_U32 * pStcH,MS_U32 * pStcL)4161 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL)
4162 {
4163 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
4164 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H;
4165 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ);
4166 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
4167 }
4168
HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType,MS_U32 pktDmxId)4169 void HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType, MS_U32 pktDmxId)
4170 {
4171 switch (eFltType)
4172 {
4173 case E_TSP_DST_FIFO_VIDEO :
4174 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID_SRC_SHIFT);
4175 break;
4176 case E_TSP_DST_FIFO_VIDEO3D :
4177 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID3D_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID3D_SRC_SHIFT);
4178 break;
4179 case E_TSP_DST_FIFO_VIDEO3:
4180 REG16_MSK_W(&_RegCtrl8_1->CFG8_40, CFG8_40_REG_VID3_SRC_MASK, ((MS_U16)pktDmxId) << CFG8_40_REG_VID3_SRC_SHIFT);
4181 break;
4182 case E_TSP_DST_FIFO_VIDEO4:
4183 REG16_MSK_W(&_RegCtrl8_1->CFG8_41, CFG8_41_REG_VID4_SRC_MASK, ((MS_U16)pktDmxId) << CFG8_41_REG_VID4_SRC_SHIFT);
4184 break;
4185 case E_TSP_DST_FIFO_AUDIO :
4186 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUD_SRC_SHIFT);
4187 break;
4188 case E_TSP_DST_FIFO_AUDIO2 :
4189 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUDB_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDB_SRC_SHIFT);
4190 break;
4191 case E_TSP_DST_FIFO_AUDIO3 :
4192 REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDC_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDC_SRC_SHIFT);
4193 break;
4194 case E_TSP_DST_FIFO_AUDIO4 :
4195 REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDD_SRC_SHIFT);
4196 break;
4197 default:
4198 break;
4199 }
4200 }
4201
HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType,TSP_SRC_SEQ * pktDmxId)4202 void HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId)
4203 {
4204 switch (eFltType)
4205 {
4206 case E_TSP_DST_FIFO_VIDEO :
4207 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID_SRC_MASK) >> TSP_VID_SRC_SHIFT;
4208 break;
4209 case E_TSP_DST_FIFO_VIDEO3D:
4210 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID3D_SRC_MASK) >> TSP_VID3D_SRC_SHIFT;
4211 break;
4212 case E_TSP_DST_FIFO_VIDEO3:
4213 *pktDmxId = ((REG16_R(&_RegCtrl8_1->CFG8_40)) & CFG8_40_REG_VID3_SRC_MASK) >> CFG8_40_REG_VID3_SRC_SHIFT;
4214 break;
4215 case E_TSP_DST_FIFO_VIDEO4:
4216 *pktDmxId = ((REG16_R(&_RegCtrl8_1->CFG8_41)) & CFG8_41_REG_VID4_SRC_MASK) >> CFG8_41_REG_VID4_SRC_SHIFT;
4217 break;
4218 case E_TSP_DST_FIFO_AUDIO :
4219 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUD_SRC_MASK) >> TSP_AUD_SRC_SHIFT;
4220 break;
4221 case E_TSP_DST_FIFO_AUDIO2 :
4222 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUDB_SRC_MASK) >> TSP_AUDB_SRC_SHIFT;
4223 break;
4224 case E_TSP_DST_FIFO_AUDIO3 :
4225 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDC_SRC_MASK) >> TSP_AUDC_SRC_SHIFT;
4226 break;
4227 case E_TSP_DST_FIFO_AUDIO4 :
4228 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDD_SRC_MASK) >> TSP_AUDD_SRC_SHIFT;
4229 break;
4230 default:
4231 break;
4232 }
4233 }
4234
HAL_TSP_FIFO_ClearAll()4235 void HAL_TSP_FIFO_ClearAll()
4236 {
4237 // clear ALL FIFO !!!
4238 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
4239 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
4240 REG16_CLR(&_RegCtrl8_1->CFG8_40, CFG8_40_PS_VID3_EN);
4241 REG16_CLR(&_RegCtrl8_1->CFG8_41, CFG8_41_PS_VID4_EN);
4242 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
4243 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
4244 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
4245 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
4246
4247 }
4248
4249
HAL_TSP_FIFO_ReadEn(MS_BOOL bEn)4250 void HAL_TSP_FIFO_ReadEn(MS_BOOL bEn)
4251 {
4252 if(bEn == TRUE)
4253 {
4254 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN);
4255 }
4256 else
4257 {
4258 REG16_CLR(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN);
4259 }
4260
4261 }
4262
HAL_TSP_FIFO_ReadPkt(void)4263 MS_U16 HAL_TSP_FIFO_ReadPkt(void)
4264 {
4265 return (REG16_R(&_RegCtrl->PKT_CNT) & TSP_PKT_CNT_MASK);
4266 }
4267
HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType)4268 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType)
4269 {
4270 switch (eFltType)
4271 {
4272 case E_TSP_DST_FIFO_VIDEO:
4273 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4274 break;
4275 case E_TSP_DST_FIFO_VIDEO3D:
4276 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V3D) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4277 break;
4278 case E_TSP_DST_FIFO_VIDEO3:
4279 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V3) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4280 break;
4281 case E_TSP_DST_FIFO_VIDEO4:
4282 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V4) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4283 break;
4284 case E_TSP_DST_FIFO_AUDIO:
4285 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_A) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4286 break;
4287 case E_TSP_DST_FIFO_AUDIO2:
4288 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AB) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4289 break;
4290 case E_TSP_DST_FIFO_AUDIO3:
4291 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AC) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4292 break;
4293 case E_TSP_DST_FIFO_AUDIO4:
4294 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AD) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4295 break;
4296 default:
4297 break;
4298 }
4299 }
4300
4301 //@NOTE for TS mode
4302 //@TODO need to rename (TS enable or PKTDMX_BYPASS)
HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)4303 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
4304 {
4305 if(bEn)
4306 {
4307 switch (eFltType)
4308 {
4309 case E_TSP_DST_FIFO_VIDEO:
4310 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS);
4311 break;
4312 case E_TSP_DST_FIFO_VIDEO3D:
4313 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS);
4314 break;
4315 case E_TSP_DST_FIFO_VIDEO3:
4316 REG16_SET(&_RegCtrl3->CFG3_2E, CFG3_2E_VPID_3_BYPASS);
4317 break;
4318 case E_TSP_DST_FIFO_VIDEO4:
4319 REG16_SET(&_RegCtrl3->CFG3_2F, CFG3_2F_VPID_4_BYPASS);
4320 break;
4321 case E_TSP_DST_FIFO_AUDIO:
4322 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS);
4323 break;
4324 case E_TSP_DST_FIFO_AUDIO2:
4325 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS);
4326 break;
4327 case E_TSP_DST_FIFO_AUDIO3:
4328 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_C_BYPASS);
4329 break;
4330 case E_TSP_DST_FIFO_AUDIO4:
4331 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_D_BYPASS);
4332 break;
4333 default:
4334 break;
4335 }
4336 }
4337 else
4338 {
4339 switch (eFltType)
4340 {
4341 case E_TSP_DST_FIFO_VIDEO:
4342 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS);
4343 break;
4344 case E_TSP_DST_FIFO_VIDEO3D:
4345 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS);
4346 break;
4347 case E_TSP_DST_FIFO_VIDEO3:
4348 REG16_CLR(&_RegCtrl3->CFG3_2E, CFG3_2E_VPID_3_BYPASS);
4349 break;
4350 case E_TSP_DST_FIFO_VIDEO4:
4351 REG16_CLR(&_RegCtrl3->CFG3_2F, CFG3_2F_VPID_4_BYPASS);
4352 break;
4353 case E_TSP_DST_FIFO_AUDIO:
4354 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS);
4355 break;
4356 case E_TSP_DST_FIFO_AUDIO2:
4357 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS);
4358 break;
4359 case E_TSP_DST_FIFO_AUDIO3:
4360 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_C_BYPASS);
4361 break;
4362 case E_TSP_DST_FIFO_AUDIO4:
4363 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_D_BYPASS);
4364 break;
4365 default:
4366 break;
4367
4368 }
4369 }
4370 }
4371
HAL_TSP_PS_SRC(MS_U32 tsIf)4372 void HAL_TSP_PS_SRC(MS_U32 tsIf)
4373 {
4374 REG16_MSK_W(&_RegCtrl3->CFG3_10, CFG3_10_PS_MODE_SRC_MASK,(((MS_U16)tsIf)<< CFG3_10_PS_MODE_SRC_SHIFT));
4375 }
4376
4377
4378
4379 //PS MODE
4380 //NEED TO rename
HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)4381 void HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
4382 {
4383 if(bEn)
4384 {
4385 switch (eFltType)
4386 {
4387 case E_TSP_DST_FIFO_VIDEO:
4388 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
4389 break;
4390 case E_TSP_DST_FIFO_VIDEO3D:
4391 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
4392 break;
4393 case E_TSP_DST_FIFO_VIDEO3:
4394 REG16_SET(&_RegCtrl8_1->CFG8_40, CFG8_40_PS_VID3_EN);
4395 break;
4396 case E_TSP_DST_FIFO_VIDEO4:
4397 REG16_SET(&_RegCtrl8_1->CFG8_41, CFG8_41_PS_VID4_EN);
4398 break;
4399 case E_TSP_DST_FIFO_AUDIO:
4400 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
4401 break;
4402 case E_TSP_DST_FIFO_AUDIO2:
4403 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
4404 break;
4405 case E_TSP_DST_FIFO_AUDIO3:
4406 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
4407 break;
4408 case E_TSP_DST_FIFO_AUDIO4:
4409 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
4410 break;
4411 default:
4412 break;
4413 }
4414 }
4415 else
4416 {
4417 switch (eFltType)
4418 {
4419 case E_TSP_DST_FIFO_VIDEO :
4420 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
4421 break;
4422 case E_TSP_DST_FIFO_VIDEO3D:
4423 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
4424 break;
4425 case E_TSP_DST_FIFO_VIDEO3:
4426 REG16_CLR(&_RegCtrl8_1->CFG8_40, CFG8_40_PS_VID3_EN);
4427 break;
4428 case E_TSP_DST_FIFO_VIDEO4:
4429 REG16_CLR(&_RegCtrl8_1->CFG8_41, CFG8_41_PS_VID4_EN);
4430 break;
4431 case E_TSP_DST_FIFO_AUDIO :
4432 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
4433 break;
4434 case E_TSP_DST_FIFO_AUDIO2 :
4435 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
4436 break;
4437 case E_TSP_DST_FIFO_AUDIO3 :
4438 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
4439 break;
4440 case E_TSP_DST_FIFO_AUDIO4 :
4441 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
4442 break;
4443 default:
4444 break;
4445 }
4446 }
4447 }
4448
HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng,TSP_DST_SEQ eFltType)4449 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType)
4450 {
4451 // (K6 HW CL)
4452 // PS mode source sel need to be independent
4453
4454 switch (eFltType)
4455 {
4456 case E_TSP_DST_FIFO_VIDEO:
4457 REG16_MSK_W(&_RegCtrl8_1->CFG8_48,CFG8_48_REG_PS_MODE_SRC_V_MASK, (eFileEng << CFG8_48_REG_PS_MODE_SRC_V_SHIFT));
4458 break;
4459 case E_TSP_DST_FIFO_VIDEO3D:
4460 REG16_MSK_W(&_RegCtrl8_1->CFG8_48,CFG8_48_REG_PS_MODE_SRC_V3D_MASK,(eFileEng << CFG8_48_REG_PS_MODE_SRC_V3D_SHIFT));
4461 break;
4462 case E_TSP_DST_FIFO_VIDEO3:
4463 REG16_MSK_W(&_RegCtrl8_1->CFG8_48,CFG8_48_REG_PS_MODE_SRC_V3_MASK, (eFileEng << CFG8_48_REG_PS_MODE_SRC_V3_SHIFT));
4464 break;
4465 case E_TSP_DST_FIFO_VIDEO4:
4466 REG16_MSK_W(&_RegCtrl8_1->CFG8_48,CFG8_48_REG_PS_MODE_SRC_V4_MASK, (eFileEng << CFG8_48_REG_PS_MODE_SRC_V4_SHIFT));
4467 break;
4468 case E_TSP_DST_FIFO_AUDIO:
4469 REG16_MSK_W(&_RegCtrl8_1->CFG8_47,CFG8_47_REG_PS_MODE_SRC_A_MASK, (eFileEng << CFG8_47_REG_PS_MODE_SRC_A_SHIFT));
4470 break;
4471 case E_TSP_DST_FIFO_AUDIO2:
4472 REG16_MSK_W(&_RegCtrl8_1->CFG8_47,CFG8_47_REG_PS_MODE_SRC_AD_MASK, (eFileEng << CFG8_47_REG_PS_MODE_SRC_AD_SHIFT));
4473 break;
4474 case E_TSP_DST_FIFO_AUDIO3:
4475 REG16_MSK_W(&_RegCtrl8_1->CFG8_47,CFG8_47_REG_PS_MODE_SRC_AC_MASK, (eFileEng << CFG8_47_REG_PS_MODE_SRC_AC_SHIFT));
4476 break;
4477 case E_TSP_DST_FIFO_AUDIO4:
4478 REG16_MSK_W(&_RegCtrl8_1->CFG8_47,CFG8_47_REG_PS_MODE_SRC_ADD_MASK,(eFileEng << CFG8_47_REG_PS_MODE_SRC_ADD_SHIFT));
4479 break;
4480 default:
4481 break;
4482 }
4483 }
4484
HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)4485 MS_U32 HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)
4486 {
4487 switch (eFltType)
4488 {
4489 case E_TSP_DST_FIFO_VIDEO :
4490 return REG16_R(&_RegCtrl->Vd_Pid_Hit) & TSP_VPID_MASK;
4491 case E_TSP_DST_FIFO_VIDEO3D :
4492 return REG16_R(&_RegCtrl2->CFG_70) & CFG_70_MATCHECED_VPID_3D_MASK;
4493 case E_TSP_DST_FIFO_VIDEO3 :
4494 return REG16_R(&_RegCtrl2->CFG_7D) & CFG_7D_MATCHECED_VPID_3_MASK;
4495 case E_TSP_DST_FIFO_VIDEO4 :
4496 return REG16_R(&_RegCtrl2->CFG_7E) & CFG_7E_MATCHECED_VPID_4_MASK;
4497 case E_TSP_DST_FIFO_AUDIO :
4498 return REG16_R(&_RegCtrl->Aud_Pid_Hit) & TSP_APID_MASK;
4499 case E_TSP_DST_FIFO_AUDIO2 :
4500 return REG16_R(&_RegCtrl2->CFG_71) & CFG_71_MATCHECED_APID_B_MASK;
4501 case E_TSP_DST_FIFO_AUDIO3 :
4502 return REG16_R(&_RegCtrl2->CFG_74) & CFG_74_MATCHECED_APID_C_MASK;
4503 case E_TSP_DST_FIFO_AUDIO4 :
4504 return REG16_R(&_RegCtrl2->CFG_7C) & CFG_7C_MATCHECED_APID_D_MASK;
4505 default:
4506 return PVR_PIDFLT_DEF;
4507 }
4508 }
4509
HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType,MS_BOOL bReset)4510 void HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType, MS_BOOL bReset)
4511 {
4512 if (bReset)
4513 {
4514 switch (eFltType)
4515 {
4516 case E_TSP_DST_FIFO_VIDEO :
4517 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO);
4518 break;
4519 case E_TSP_DST_FIFO_VIDEO3D:
4520 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D);
4521 break;
4522 case E_TSP_DST_FIFO_VIDEO3:
4523 REG16_SET(&_RegCtrl8_1->CFG8_40, CFG8_40_RESET_VFIFO_3);
4524 break;
4525 case E_TSP_DST_FIFO_VIDEO4:
4526 REG16_SET(&_RegCtrl8_1->CFG8_41, CFG8_41_RESET_VFIFO_4);
4527 break;
4528 case E_TSP_DST_FIFO_AUDIO :
4529 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO);
4530 break;
4531 case E_TSP_DST_FIFO_AUDIO2 :
4532 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2);
4533 break;
4534 case E_TSP_DST_FIFO_AUDIO3 :
4535 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO3);
4536 break;
4537 case E_TSP_DST_FIFO_AUDIO4 :
4538 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4);
4539 break;
4540 default :
4541 break;
4542 }
4543 }
4544 else
4545 {
4546 switch (eFltType)
4547 {
4548 case E_TSP_DST_FIFO_VIDEO :
4549 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO);
4550 break;
4551 case E_TSP_DST_FIFO_VIDEO3D:
4552 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D);
4553 break;
4554 case E_TSP_DST_FIFO_VIDEO3:
4555 REG16_CLR(&_RegCtrl8_1->CFG8_40, CFG8_40_RESET_VFIFO_3);
4556 break;
4557 case E_TSP_DST_FIFO_VIDEO4:
4558 REG16_CLR(&_RegCtrl8_1->CFG8_41, CFG8_41_RESET_VFIFO_4);
4559 break;
4560 case E_TSP_DST_FIFO_AUDIO :
4561 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO);
4562 break;
4563 case E_TSP_DST_FIFO_AUDIO2 :
4564 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO2);
4565 break;
4566 case E_TSP_DST_FIFO_AUDIO3 :
4567 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO3);
4568 break;
4569 case E_TSP_DST_FIFO_AUDIO4 :
4570 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4);
4571 break;
4572 default :
4573 break;
4574 }
4575 }
4576
4577 _delay(1);
4578 }
4579
HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)4580 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)
4581 {
4582 if(bSkip)
4583 {
4584 switch(eFltType)
4585 {
4586 case E_TSP_DST_FIFO_VIDEO:
4587 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN);
4588 break;
4589 case E_TSP_DST_FIFO_VIDEO3D:
4590 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN);
4591 break;
4592 case E_TSP_DST_FIFO_VIDEO3:
4593 REG16_SET(&_RegCtrl8_1->CFG8_40, CFG8_40_MASK_SCR_V3_EN);
4594 break;
4595 case E_TSP_DST_FIFO_VIDEO4:
4596 REG16_SET(&_RegCtrl8_1->CFG8_45, CFG8_41_MASK_SCR_V4_EN);
4597 break;
4598 case E_TSP_DST_FIFO_AUDIO:
4599 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN);
4600 break;
4601 case E_TSP_DST_FIFO_AUDIO2:
4602 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN);
4603 break;
4604 case E_TSP_DST_FIFO_AUDIO3:
4605 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AC_EN);
4606 break;
4607 case E_TSP_DST_FIFO_AUDIO4:
4608 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AD_EN);
4609 break;
4610 default:
4611 break;
4612 }
4613 }
4614 else
4615 {
4616 switch(eFltType)
4617 {
4618 case E_TSP_DST_FIFO_VIDEO:
4619 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN);
4620 break;
4621 case E_TSP_DST_FIFO_VIDEO3D:
4622 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN);
4623 break;
4624 case E_TSP_DST_FIFO_VIDEO3:
4625 REG16_CLR(&_RegCtrl8_1->CFG8_40, CFG8_40_MASK_SCR_V3_EN);
4626 break;
4627 case E_TSP_DST_FIFO_VIDEO4:
4628 REG16_CLR(&_RegCtrl8_1->CFG8_45, CFG8_41_MASK_SCR_V4_EN);
4629 break;
4630 case E_TSP_DST_FIFO_AUDIO:
4631 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN);
4632 break;
4633 case E_TSP_DST_FIFO_AUDIO2:
4634 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN);
4635 break;
4636 case E_TSP_DST_FIFO_AUDIO3:
4637 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AC_EN);
4638 break;
4639 case E_TSP_DST_FIFO_AUDIO4:
4640 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AD_EN);
4641 break;
4642 default:
4643 break;
4644 }
4645
4646 }
4647 }
4648
4649
HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType,MS_BOOL bDisable)4650 void HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType, MS_BOOL bDisable)
4651 {
4652 if(bDisable)
4653 {
4654 switch(eFltType)
4655 {
4656 case E_TSP_DST_FIFO_VIDEO:
4657 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS);
4658 break;
4659 case E_TSP_DST_FIFO_VIDEO3D:
4660 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS);
4661 break;
4662 case E_TSP_DST_FIFO_VIDEO3:
4663 REG16_SET(&_RegCtrl8_1->CFG8_40, CFG8_40_V3_BLOCK_DIS);
4664 break;
4665 case E_TSP_DST_FIFO_VIDEO4:
4666 REG16_SET(&_RegCtrl8_1->CFG8_41, CFG8_41_V4_BLOCK_DIS);
4667 break;
4668 case E_TSP_DST_FIFO_AUDIO :
4669 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS);
4670 break;
4671 case E_TSP_DST_FIFO_AUDIO2 :
4672 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS);
4673 break;
4674 case E_TSP_DST_FIFO_AUDIO3 :
4675 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS);
4676 break;
4677 case E_TSP_DST_FIFO_AUDIO4 :
4678 REG32_SET(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS);
4679 break;
4680 default:
4681 break;
4682 }
4683 }
4684 else
4685 {
4686 switch(eFltType)
4687 {
4688 case E_TSP_DST_FIFO_VIDEO:
4689 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS);
4690 break;
4691 case E_TSP_DST_FIFO_VIDEO3D:
4692 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS);
4693 break;
4694 case E_TSP_DST_FIFO_VIDEO3:
4695 REG16_CLR(&_RegCtrl8_1->CFG8_40, CFG8_40_V3_BLOCK_DIS);
4696 break;
4697 case E_TSP_DST_FIFO_VIDEO4:
4698 REG16_CLR(&_RegCtrl8_1->CFG8_41, CFG8_41_V4_BLOCK_DIS);
4699 break;
4700 case E_TSP_DST_FIFO_AUDIO :
4701 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS);
4702 break;
4703 case E_TSP_DST_FIFO_AUDIO2 :
4704 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS);
4705 break;
4706 case E_TSP_DST_FIFO_AUDIO3 :
4707 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS);
4708 break;
4709 case E_TSP_DST_FIFO_AUDIO4 :
4710 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS);
4711 break;
4712 default:
4713 break;
4714 }
4715 }
4716 }
4717
HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)4718 MS_BOOL HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)
4719 {
4720 MS_U32 u32Matched = 0;
4721 switch (eFltType)
4722 {
4723 case E_TSP_DST_FIFO_VIDEO :
4724 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO;
4725 break;
4726 case E_TSP_DST_FIFO_VIDEO3D:
4727 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO3D;
4728 break;
4729 case E_TSP_DST_FIFO_VIDEO3 :
4730 u32Matched = REG16_R(&_RegCtrl8_1->CFG8_40) & CFG8_40_RESET_VFIFO_3;
4731 break;
4732 case E_TSP_DST_FIFO_VIDEO4:
4733 u32Matched = REG16_R(&_RegCtrl8_1->CFG8_41) & CFG8_41_RESET_VFIFO_4;
4734 break;
4735 case E_TSP_DST_FIFO_AUDIO :
4736 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO;
4737 break;
4738 case E_TSP_DST_FIFO_AUDIO2 :
4739 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO2;
4740 break;
4741 case E_TSP_DST_FIFO_AUDIO3 :
4742 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO3;
4743 break;
4744 case E_TSP_DST_FIFO_AUDIO4 :
4745 u32Matched = REG16_R(&_RegCtrl->PktChkSizeFilein) & TSP_RESET_AFIFO4;
4746 break;
4747 default :
4748 return FALSE;
4749 }
4750 return (u32Matched) ? TRUE: FALSE;
4751 }
4752
HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)4753 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)
4754 {
4755 #define E_TSP_FIFO_STATUS_ISRESET 0x80000000
4756 #define E_TSP_FIFO_STATUS_EMPTY 0x00000001
4757 #define E_TSP_FIFO_STATUS_OVERFLOW 0x00000002
4758 #define E_TSP_FIFO_STATUS_LEVEL 0x0000000C
4759 #define TSP_FIFO_STATUS_LEVEL_SHFT 2 //shift the value get from HAL_TSP_FIFO_Level to the u32Status level position
4760 // @NOTE please follow K2 like series to return this value
4761 // since API layer didn't define for each column
4762 // we only defined that 0x80000000 stands for this fifo reset is High
4763 // 0x00000001 stands for this fifo is empty
4764 // 0x00000002 stands for this fifo is overflow
4765 // 0x0000000C is a mask for this fifo level
4766 // this is exclusive usage
4767 MS_U32 u32Status = 0;
4768 if (HAL_TSP_FIFO_IsReset(eFltType))
4769 {
4770 u32Status |= E_TSP_FIFO_STATUS_ISRESET;
4771 }
4772 if (HAL_TSP_FIFO_Empty(eFltType))
4773 {
4774 u32Status |= E_TSP_FIFO_STATUS_EMPTY;
4775 }
4776 if (HAL_TSP_FIFO_Overflow(eFltType))
4777 {
4778 u32Status |= E_TSP_FIFO_STATUS_OVERFLOW;
4779 }
4780
4781 u32Status |= ((HAL_TSP_FIFO_Level(eFltType)<<TSP_FIFO_STATUS_LEVEL_SHFT)&E_TSP_FIFO_STATUS_LEVEL);
4782
4783 return u32Status;
4784 }
4785
HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)4786 MS_U32 HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)
4787 {
4788 switch (eFltType)
4789 {
4790 case E_TSP_DST_FIFO_VIDEO :
4791 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_LEVEL) >> TSP_VFIFO_LEVEL_SHFT;
4792 case E_TSP_DST_FIFO_VIDEO3D :
4793 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_LEVEL) >> TSP_VFIFO3D_LEVEL_SHFT;
4794 case E_TSP_DST_FIFO_VIDEO3 :
4795 return (REG16_R(&_RegCtrl3->CFG3_4C) & CFG3_4C_TSP_VFIFO3_LEVEL) >> CFG3_4C_TSP_VFIFO3_LEVEL_SHFT;
4796 case E_TSP_DST_FIFO_VIDEO4 :
4797 return (REG16_R(&_RegCtrl3->CFG3_4D) & CFG3_4D_TSP_VFIFO4_LEVEL) >> CFG3_4D_TSP_VFIFO4_LEVEL_SHFT;
4798 case E_TSP_DST_FIFO_AUDIO :
4799 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_LEVEL) >> TSP_AFIFO_LEVEL_SHFT;
4800 case E_TSP_DST_FIFO_AUDIO2 :
4801 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_LEVEL) >> TSP_AFIFOB_LEVEL_SHFT;
4802 case E_TSP_DST_FIFO_AUDIO3 :
4803 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_LEVEL) >> TSP_AFIFOC_LEVEL_SHFT;
4804 case E_TSP_DST_FIFO_AUDIO4:
4805 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_LEVEL) >> TSP_AFIFOD_LEVEL_SHFT;
4806 default :
4807 return 0;
4808 }
4809 }
4810
HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)4811 MS_BOOL HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)
4812 {
4813 switch (eFltType)
4814 {
4815 case E_TSP_DST_FIFO_VIDEO :
4816 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_FULL) >> TSP_VFIFO_FULL_SHFT;
4817 case E_TSP_DST_FIFO_VIDEO3D :
4818 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_FULL) >> TSP_VFIFO3D_FULL_SHFT;
4819 case E_TSP_DST_FIFO_VIDEO3 :
4820 return (REG16_R(&_RegCtrl3->CFG3_4C) & CFG3_4C_TSP_VFIFO3_FULL) >> CFG3_4C_TSP_VFIFO3_FULL_SHFT;
4821 case E_TSP_DST_FIFO_VIDEO4 :
4822 return (REG16_R(&_RegCtrl3->CFG3_4C) & CFG3_4D_TSP_VFIFO4_FULL) >> CFG3_4D_TSP_VFIFO4_FULL_SHFT;
4823 case E_TSP_DST_FIFO_AUDIO :
4824 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_FULL) >> TSP_AFIFO_FULL_SHFT;
4825 case E_TSP_DST_FIFO_AUDIO2 :
4826 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_FULL) >> TSP_AFIFOB_FULL_SHFT;
4827 case E_TSP_DST_FIFO_AUDIO3 :
4828 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_FULL) >> TSP_AFIFOC_FULL_SHFT;
4829 case E_TSP_DST_FIFO_AUDIO4 :
4830 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_FULL) >> TSP_AFIFOD_FULL_SHFT;
4831 default :
4832 return FALSE;
4833 }
4834 }
4835
HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)4836 MS_BOOL HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)
4837 {
4838 switch (eFltType)
4839 {
4840 case E_TSP_DST_FIFO_VIDEO :
4841 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_EMPTY) >> TSP_VFIFO_EMPTY_SHFT;
4842 case E_TSP_DST_FIFO_VIDEO3D:
4843 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_EMPTY) >> TSP_VFIFO3D_EMPTY_SHFT;
4844 case E_TSP_DST_FIFO_VIDEO3 :
4845 return (REG16_R(&_RegCtrl3->CFG3_4C) & CFG3_4C_TSP_VFIFO3_EMPTY) >> CFG3_4C_TSP_VFIFO3_EMPTY_SHFT;
4846 case E_TSP_DST_FIFO_VIDEO4 :
4847 return (REG16_R(&_RegCtrl3->CFG3_4D) & CFG3_4D_TSP_VFIFO4_EMPTY) >> CFG3_4D_TSP_VFIFO4_EMPTY_SHFT;
4848 case E_TSP_DST_FIFO_AUDIO :
4849 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_EMPTY) >> TSP_AFIFO_EMPTY_SHFT;
4850 case E_TSP_DST_FIFO_AUDIO2 :
4851 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_EMPTY) >> TSP_AFIFOB_EMPTY_SHFT;
4852 case E_TSP_DST_FIFO_AUDIO3 :
4853 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_EMPTY) >> TSP_AFIFOC_EMPTY_SHFT;
4854 case E_TSP_DST_FIFO_AUDIO4 :
4855 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_EMPTY) >> TSP_AFIFOD_EMPTY_SHFT;
4856 default :
4857 return FALSE;
4858 }
4859 }
4860
_HAL_TSP_VQ_TxConfig(MS_U32 vqId)4861 static MS_BOOL _HAL_TSP_VQ_TxConfig(MS_U32 vqId)
4862 {
4863 // reg_vq_wr_threshold = 0x8
4864 // reg_vq_forcefire_cnt_1k= 0xC
4865
4866 switch(vqId)
4867 {
4868 case 0:
4869 REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ0_WR_THRESHOLD_SHIFT) & TSP_VQ0_WR_THRESHOLD_MASK));
4870 REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT) & TSP_VQ0_FORCE_FIRE_CNT_1K_MASK));
4871 break;
4872 case 1:
4873 REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ1_WR_THRESHOLD_SHIFT) & TSP_VQ1_WR_THRESHOLD_MASK));
4874 REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ1_FORCEFIRE_CNT_1K_MASK));
4875 break;
4876 case 2:
4877 REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ2_WR_THRESHOLD_SHIFT) & TSP_VQ2_WR_THRESHOLD_MASK));
4878 REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ2_FORCEFIRE_CNT_1K_MASK));
4879 break;
4880 case 3:
4881 REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ3_WR_THRESHOLD_SHIFT) & TSP_VQ3_WR_THRESHOLD_MASK));
4882 REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ3_FORCEFIRE_CNT_1K_MASK));
4883 break;
4884 default:
4885 return FALSE;
4886 }
4887 return TRUE;
4888 }
4889
HAL_TSP_SetVQ(MS_PHYADDR u32BaseAddr,MS_U32 u32BufLen)4890 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen)
4891 {
4892 MS_U32 vqId = 0;
4893 MS_U32 u32VQ_PktNum = 0;
4894 MS_U32 u32Addr = 0;
4895 MS_U32 u32OneBufSize = 0;
4896
4897 // Check MIU select
4898 MS_U8 u8MiuSel = 0;
4899 _phy_to_miu_offset(u8MiuSel, u32Addr, u32BaseAddr);
4900 REG16_W(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW, (REG16_R(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW) & (~REG_MIU_SEL_VQ_MASK)) | ((u8MiuSel << REG_MIU_SEL_VQ_SHIFT) & REG_MIU_SEL_VQ_MASK));
4901
4902 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment
4903 u32VQ_PktNum = u32OneBufSize / VQ_PACKET_UNIT_LEN;
4904
4905 for(vqId = 0; vqId < VQ_NUM; vqId ++)
4906 {
4907 if(TRUE != _HAL_TSP_VQ_TxConfig(vqId))
4908 {
4909 return FALSE;
4910 }
4911
4912 // in kaiser we needs to set 6 VQ and the base unit is 208 so total vq size should be N*208*6
4913 if (TRUE != HAL_TSP_VQ_Buffer(vqId, u32Addr, u32VQ_PktNum))
4914 {
4915 return FALSE;
4916 }
4917 u32Addr += u32OneBufSize;
4918 }
4919
4920 HAL_TSP_VQ_Enable(TRUE);
4921 return TRUE;
4922
4923 }
4924
HAL_TSP_VQ_Buffer(MS_U32 vqId,MS_PHYADDR u32BaseAddr,MS_U32 u32VQ_PktNum)4925 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32VQ_PktNum)
4926 {
4927 switch(vqId)
4928 {
4929 case 0:
4930 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS));
4931 REG16_W(&_RegCtrl->VQ0_SIZE, u32VQ_PktNum);
4932 break;
4933 case 1:
4934 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS));
4935 REG16_W(&_RegCtrl->VQ1_Size, u32VQ_PktNum);
4936 break;
4937 case 2:
4938 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS));
4939 REG16_W(&_RegCtrl->VQ2_Size, u32VQ_PktNum);
4940 break;
4941 case 3:
4942 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS));
4943 REG16_W(&_RegCtrl->VQ3_Size, u32VQ_PktNum);
4944 break;
4945 default:
4946 return FALSE;
4947 }
4948 return TRUE;
4949 }
4950
HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)4951 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)
4952 {
4953 if(bDis == TRUE)
4954 {
4955 switch(vqId)
4956 {
4957 case 0:
4958 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS);
4959 break;
4960 case 1:
4961 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS);
4962 break;
4963 case 2:
4964 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS);
4965 break;
4966 case 3:
4967 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS);
4968 break;
4969 default:
4970 return FALSE;
4971 }
4972 }
4973 else
4974 {
4975 switch(vqId)
4976 {
4977 case 0:
4978 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS);
4979 break;
4980 case 1:
4981 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS);
4982 break;
4983 case 2:
4984 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS);
4985 break;
4986 case 3:
4987 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS);
4988 break;
4989 default:
4990 return FALSE;
4991 }
4992 }
4993
4994 return TRUE;
4995 }
4996
HAL_TSP_VQ_Enable(MS_BOOL bEn)4997 void HAL_TSP_VQ_Enable(MS_BOOL bEn)
4998 {
4999 if (bEn)
5000 {
5001 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
5002 }
5003 else
5004 {
5005 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
5006 }
5007 }
HAL_TSP_VQ_Reset(MS_U32 vqId,MS_BOOL bEn)5008 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn)
5009 {
5010 if(bEn)
5011 {
5012 switch(vqId)
5013 {
5014 case 0:
5015 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET);
5016 break;
5017 case 1:
5018 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET);
5019 break;
5020 case 2:
5021 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET);
5022 break;
5023 case 3:
5024 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET);
5025 break;
5026 default:
5027 break;
5028 }
5029 }
5030 else
5031 {
5032 switch(vqId)
5033 {
5034 case 0:
5035 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET);
5036 break;
5037 case 1:
5038 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET);
5039 break;
5040 case 2:
5041 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET);
5042 break;
5043 case 3:
5044 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET);
5045 break;
5046 default:
5047 break;
5048 }
5049 }
5050 }
5051
HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId,MS_BOOL bEn)5052 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn)
5053 {
5054 if(bEn)
5055 {
5056 switch(vqId)
5057 {
5058 case 0:
5059 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN);
5060 break;
5061 case 1:
5062 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN);
5063 break;
5064 case 2:
5065 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN);
5066 break;
5067 case 3:
5068 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN);
5069 break;
5070 default:
5071 break;
5072 }
5073 }
5074 else
5075 {
5076 switch(vqId)
5077 {
5078 case 0:
5079 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN);
5080 break;
5081 case 1:
5082 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN);
5083 break;
5084 case 2:
5085 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN);
5086 break;
5087 case 3:
5088 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN);
5089 break;
5090 default:
5091 break;
5092 }
5093 }
5094 }
5095
HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId,MS_BOOL bEn)5096 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn)
5097 {
5098 if(bEn)
5099 {
5100 switch(vqId)
5101 {
5102 case 0:
5103 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT);
5104 break;
5105 case 1:
5106 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT);
5107 break;
5108 case 2:
5109 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT);
5110 break;
5111 case 3:
5112 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT);
5113 break;
5114 default:
5115 break;
5116 }
5117 }
5118 else
5119 {
5120 switch(vqId)
5121 {
5122 case 0:
5123 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT);
5124 break;
5125 case 1:
5126 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT);
5127 break;
5128 case 2:
5129 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT);
5130 break;
5131 case 3:
5132 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT);
5133 break;
5134 default:
5135 break;
5136 }
5137 }
5138 }
5139
HAL_PVR_Init(MS_U32 u32PVREng,MS_U32 pktDmxId)5140 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId)
5141 {
5142 switch(u32PVREng)
5143 {
5144 case 0:
5145 // PVR 1
5146 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG);
5147 REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR1_SRC_MASK) | (((MS_U16)pktDmxId) << TSP_PVR1_SRC_SHIFT));
5148 break;
5149 case 1:
5150 // PVR 2
5151 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN);
5152 REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR2_SRC_MASK_L) | ((((MS_U16)pktDmxId) & 0x01) << TSP_PVR2_SRC_SHIFT_L));
5153 REG16_W(&(_RegCtrl->PCR_Cfg), (REG16_R(&(_RegCtrl->PCR_Cfg)) & ~TSP_PVR2_SRC_MASK_H) | ((((MS_U16)pktDmxId) >> 1) << TSP_PVR2_SRC_SHIFT_H));
5154 break;
5155 case 2:
5156 // PVR 3
5157 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC, pktDmxId << CFG_15_PVR3_SRC_SHIFT);
5158 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN);
5159 break;
5160 case 3:
5161 // PVR 3
5162 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC, pktDmxId << CFG_15_PVR4_SRC_SHIFT);
5163 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN);
5164 break;
5165 default:
5166 break;
5167 }
5168 }
5169
HAL_PVR_Exit(MS_U32 u32PVREng)5170 void HAL_PVR_Exit(MS_U32 u32PVREng)
5171 {
5172 switch(u32PVREng)
5173 {
5174 case 0:
5175 //reset pvr control registers
5176 REG16_CLR(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG);
5177 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR1_SRC_MASK);
5178
5179 //reset write address
5180 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
5181 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
5182 break;
5183 case 1:
5184 //reset pvr control registers
5185 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN);
5186 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR2_SRC_MASK_L);
5187 REG16_CLR(&(_RegCtrl->PCR_Cfg), TSP_PVR2_SRC_MASK_H);
5188
5189 //reset write address
5190 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
5191 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
5192 break;
5193 case 2:
5194 //reset pvr control registers
5195 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC);
5196 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN);
5197
5198 //reset write address
5199 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
5200 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
5201 break;
5202 case 3:
5203 //reset pvr control registers
5204 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC);
5205 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN);
5206
5207 //reset write address
5208 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
5209 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
5210 break;
5211 default:
5212 break;
5213 }
5214
5215 if(_stPvrBuf[u32PVREng].bPA2KSEG1_Mapping== TRUE)
5216 {
5217 _stPvrBuf[u32PVREng].bOverWrite = FALSE;
5218 }
5219
5220 //reset time-stamp
5221 HAL_PVR_SetPVRTimeStamp(u32PVREng,0);
5222
5223 }
5224
HAL_PVR_Start(MS_U32 u32PVREng)5225 void HAL_PVR_Start(MS_U32 u32PVREng)
5226 {
5227 switch(u32PVREng)
5228 {
5229 case 0:
5230 //reset write address
5231 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
5232 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
5233
5234 //enable string to miu
5235 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE);
5236 break;
5237 case 1:
5238 //reset write address
5239 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
5240 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
5241
5242 //enable string to miu
5243 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN);
5244 break;
5245 case 2:
5246 //reset write address
5247 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
5248 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
5249
5250 //enable string to miu
5251 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN);
5252 break;
5253 case 3:
5254 //reset write address
5255 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
5256 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
5257
5258 //enable string to miu
5259 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN);
5260 break;
5261 default:
5262 break;
5263 }
5264 if(_stPvrBuf[u32PVREng].bPA2KSEG1_Mapping== TRUE)
5265 {
5266 if((E_TSP_PVR_PVRENG_START <= u32PVREng) && (E_TSP_PVR_PVRENG_END > u32PVREng)) // PVR Eng number check
5267 {
5268 _stPvrBuf[u32PVREng].bOverWrite = FALSE; // Set PVR buffer to non-OverWrite state
5269 }
5270 }
5271 }
5272
HAL_PVR_Stop(MS_U32 u32PVREng)5273 void HAL_PVR_Stop(MS_U32 u32PVREng)
5274 {
5275 switch(u32PVREng)
5276 {
5277 case 0:
5278 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE);
5279 break;
5280 case 1:
5281 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN);
5282 break;
5283 case 2:
5284 //clear string to miu
5285 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN);
5286 break;
5287 case 3:
5288 //clear string to miu
5289 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN);
5290 break;
5291 default:
5292 break;
5293 }
5294 }
5295
HAL_PVR_Pause(MS_U32 u32PVREng,MS_BOOL bPause)5296 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause)
5297 {
5298 if(bPause)
5299 {
5300 switch(u32PVREng)
5301 {
5302 case 0:
5303 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE);
5304 break;
5305 case 1:
5306 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE);
5307 break;
5308 case 2:
5309 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE);
5310 break;
5311 case 3:
5312 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE);
5313 break;
5314 default:
5315 break;
5316 }
5317 }
5318 else
5319 {
5320 switch(u32PVREng)
5321 {
5322 case 0:
5323 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE);
5324 break;
5325 case 1:
5326 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE);
5327 break;
5328 case 2:
5329 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE);
5330 break;
5331 case 3:
5332 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE);
5333 break;
5334 default:
5335 break;
5336 }
5337 }
5338 }
5339
HAL_PVR_RecPid(MS_U32 u32PVREng,MS_BOOL bSet)5340 void HAL_PVR_RecPid(MS_U32 u32PVREng , MS_BOOL bSet)
5341 {
5342 if(bSet)
5343 {
5344 switch(u32PVREng)
5345 {
5346 case 0:
5347 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS);
5348 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN);
5349 break;
5350 case 1:
5351 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2);
5352 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN);
5353 break;
5354 case 2:
5355 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC);
5356 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3);
5357 break;
5358 case 3:
5359 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC);
5360 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4);
5361 break;
5362 default:
5363 break;
5364 }
5365 }
5366 else
5367 {
5368 switch(u32PVREng)
5369 {
5370 case 0:
5371 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS);
5372 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN);
5373 break;
5374 case 1:
5375 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2);
5376 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN);
5377 break;
5378 case 2:
5379 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC);
5380 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3);
5381 break;
5382 case 3:
5383 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC);
5384 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4);
5385 break;
5386 default:
5387 break;
5388 }
5389 }
5390 }
5391
HAL_PVR_RecNull(MS_BOOL bSet)5392 void HAL_PVR_RecNull(MS_BOOL bSet)
5393 {
5394 if(bSet == TRUE)
5395 {
5396 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL);
5397 }
5398 else
5399 {
5400 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_REC_NULL);
5401 }
5402 }
5403
HAL_PVR_SetBuf(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32BufSize0,MS_U32 u32StartAddr1,MS_U32 u32BufSize1)5404 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1)
5405 {
5406 // Check MIU select
5407 MS_U8 u8MiuSel;
5408 MS_PHY phyMiuOffsetPvrBuf0, phyMiuOffsetPvrBuf1;
5409 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf0, u32StartAddr0);
5410 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf1, u32StartAddr1);
5411
5412 MS_U32 u32EndAddr0 = phyMiuOffsetPvrBuf0 + u32BufSize0;
5413 MS_U32 u32EndAddr1 = phyMiuOffsetPvrBuf1 + u32BufSize1;
5414 //MS_U32 u32Temp;
5415 switch(u32PVREng)
5416 {
5417 case 0:
5418 // Select MIU
5419 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR1_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR1_SHIFT) & REG_MIU_SEL_PVR1_MASK));
5420
5421 //head1
5422 REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5423 //end1
5424 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5425 //mid1
5426 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5427
5428 //head2
5429 REG32_W(&_RegCtrl->Str2mi_head2pvr1, (phyMiuOffsetPvrBuf1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK);
5430 //end2
5431 REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK);
5432 //mid2
5433 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK);
5434 break;
5435 case 1:
5436 // Select MIU
5437 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR2_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR2_SHIFT) & REG_MIU_SEL_PVR2_MASK));
5438
5439 //head1
5440 REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5441 //end1
5442 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5443 //mid1
5444 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5445
5446 //head2
5447 REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (phyMiuOffsetPvrBuf1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5448 //end2
5449 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5450 //mid2
5451 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (phyMiuOffsetPvrBuf1 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5452 break;
5453 case 2:
5454 // Select MIU
5455 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR3_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR3_SHIFT) & REG_MIU_SEL_PVR3_MASK));
5456
5457 //head1
5458 REG32_W(&(_RegCtrl2->CFG_17_18), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD);
5459 //end1
5460 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0 >> MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL);
5461 //mid1
5462 REG32_W(&(_RegCtrl2->CFG_19_1A), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_19_1A_PVR3_STR2MI_MID);
5463
5464 //head2
5465 REG32_W(&(_RegCtrl2->CFG_1D_1E), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2);
5466 //end2
5467 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1 >> MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2);
5468 //mid2
5469 REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2);
5470 break;
5471 case 3:
5472 // Select MIU
5473 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR4_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR4_SHIFT) & REG_MIU_SEL_PVR4_MASK));
5474
5475 //head1
5476 REG32_W(&(_RegCtrl2->CFG_24_25), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD);
5477 //end1
5478 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL);
5479 //mid1
5480 REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID);
5481
5482 //head2
5483 REG32_W(&(_RegCtrl2->CFG_2A_2B), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2);
5484 //end2
5485 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2);
5486 //mid2
5487 REG32_W(&(_RegCtrl2->CFG_2C_2D), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2C_2D_PVR4_STR2MI_MID2);
5488 break;
5489
5490 default:
5491 break;
5492 }
5493 }
5494
HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32StartAddr1)5495 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32StartAddr1)
5496 {
5497 //MS_U32 u32Temp;
5498 switch(u32PVREng)
5499 {
5500 case 0:
5501 //head1
5502 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5503
5504 //head2
5505 REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK);
5506 break;
5507 case 1:
5508 //head1
5509 REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5510
5511 //head2
5512 REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5513
5514 break;
5515 case 2:
5516 //head1
5517 REG32_W(&(_RegCtrl2->CFG_17_18), (u32StartAddr0>>MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD);
5518
5519 //head2
5520 REG32_W(&(_RegCtrl2->CFG_1D_1E), (u32StartAddr1>>MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2);
5521 break;
5522 case 3:
5523 //head1
5524 REG32_W(&(_RegCtrl2->CFG_24_25), (u32StartAddr0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD);
5525
5526 //head2
5527 REG32_W(&(_RegCtrl2->CFG_2A_2B), (u32StartAddr1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2);
5528 break;
5529 default:
5530 break;
5531 }
5532
5533 MS_VIRT virtStart = MsOS_PA2KSEG1(u32StartAddr0);
5534 //PA2KSEG1 mapping detection, 0 : not mapping.
5535 if(0 == virtStart)
5536 {
5537 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_INFO, E_HAL_TSP_DBG_MODEL_ALL, printf("[PA2KSEG1_Mapping][%s][%d] PA2KSEG1_Mapping fail !!\n",__FUNCTION__,__LINE__));
5538 _stPvrBuf[u32PVREng].bPA2KSEG1_Mapping= FALSE;
5539 }
5540 else
5541 {
5542 if((E_TSP_PVR_PVRENG_START <= u32PVREng) && (E_TSP_PVR_PVRENG_END > u32PVREng)) // PVR Eng number check
5543 {
5544 _stPvrBuf[u32PVREng].u32Start = u32StartAddr0;
5545
5546 if( (!_stPvrBuf[u32PVREng].bOverWrite) && (_stPvrBuf[u32PVREng].u32Start!= 0) )
5547 {
5548 *((MS_U64*)(MsOS_PA2KSEG1(_stPvrBuf[u32PVREng].u32Start)))= PVR_NON_OVERWRITE;
5549 }
5550 }
5551 _stPvrBuf[u32PVREng].bPA2KSEG1_Mapping= TRUE;
5552 }
5553 }
5554
HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng,MS_U32 u32MidAddr0,MS_U32 u32MidAddr1)5555 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng , MS_U32 u32MidAddr0, MS_U32 u32MidAddr1)
5556 {
5557 switch(u32PVREng)
5558 {
5559 case 0:
5560 //mid1
5561 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK);
5562
5563 //mid2
5564 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK);
5565 break;
5566 case 1:
5567 //mid1
5568 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK);
5569
5570 //mid2
5571 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32MidAddr1>>4) & TSP_STR2MI2_ADDR_MASK);
5572 break;
5573 case 2:
5574 //mid1
5575 REG32_W(&(_RegCtrl2->CFG_19_1A), (u32MidAddr0>>4) & CFG_19_1A_PVR3_STR2MI_MID);
5576
5577 //mid2
5578 REG32_W(&(_RegCtrl2->CFG_1F_20), (u32MidAddr1>>4) & CFG_1F_20_PVR3_STR2MI_MID2);
5579 break;
5580 case 3:
5581 //mid1
5582 REG32_W(&(_RegCtrl2->CFG_26_27), (u32MidAddr0>>4) & CFG_26_27_PVR4_STR2MI_MID);
5583
5584 //mid2
5585 REG32_W(&(_RegCtrl2->CFG_2C_2D), (u32MidAddr1>>4) & CFG_2C_2D_PVR4_STR2MI_MID2);
5586 break;
5587 default:
5588 break;
5589 }
5590 }
5591
HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng,MS_U32 u32EndAddr0,MS_U32 u32EndAddr1)5592 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng , MS_U32 u32EndAddr0, MS_U32 u32EndAddr1)
5593 {
5594 switch(u32PVREng)
5595 {
5596 case 0:
5597 //end1
5598 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5599
5600 //end2
5601 REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK);
5602 break;
5603 case 1:
5604 //end1
5605 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5606
5607 //end2
5608 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5609 break;
5610 case 2:
5611 //end1
5612 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0>>MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL);
5613
5614 //end2
5615 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1>>MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2);
5616 break;
5617 case 3:
5618 //end1
5619 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL);
5620
5621 //end2
5622 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2);
5623 break;
5624 default:
5625 break;
5626 }
5627 if(_stPvrBuf[u32PVREng].bPA2KSEG1_Mapping == TRUE)
5628 {
5629 if((E_TSP_PVR_PVRENG_START <= u32PVREng) && (E_TSP_PVR_PVRENG_END > u32PVREng)) // PVR Eng number check
5630 {
5631 _stPvrBuf[u32PVREng].u32End = u32EndAddr1;
5632 }
5633 }
5634 }
5635
HAL_PVR_GetWritePtr(MS_U32 u32PVREng)5636 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng)
5637 {
5638 MS_U32 WritePtr;
5639 switch(u32PVREng)
5640 {
5641 case 0:
5642 WritePtr = REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS;
5643 break;
5644 case 1:
5645 WritePtr = REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS;
5646 break;
5647 case 2:
5648 WritePtr = REG32_R(&(_RegCtrl2->CFG_66_67)) << MIU_BUS;
5649 break;
5650 case 3:
5651 WritePtr = REG32_R(&(_RegCtrl2->CFG_68_69)) << MIU_BUS;
5652 break;
5653 default:
5654 WritePtr = 0;
5655 break;
5656 }
5657 return _Adjust_PVR_WritePtr(u32PVREng, WritePtr);
5658 }
5659
5660
HAL_PVR_GetEngSrc(MS_U32 u32EngDst,TSP_SRC_SEQ * eSrc)5661 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc)
5662 {
5663 MS_U16 u16Value = 0;
5664
5665 switch(u32EngDst)
5666 {
5667 case 0:
5668 // PVR 1
5669 *eSrc = ((REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR1_SRC_MASK) >> TSP_PVR1_SRC_SHIFT);
5670 break;
5671 case 1:
5672 // PVR 2
5673 u16Value = (REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR2_SRC_MASK_L) >> TSP_PVR2_SRC_SHIFT_L;
5674 u16Value |= ((REG16_R(&(_RegCtrl->PCR_Cfg)) & TSP_PVR2_SRC_MASK_H) << 1);
5675 *eSrc = (TSP_SRC_SEQ)u16Value;
5676 break;
5677 case 2:
5678 // PVR 3
5679 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR3_SRC) >> CFG_15_PVR3_SRC_SHIFT);
5680 break;
5681 case 3:
5682 // PVR 4
5683 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR4_SRC) >> CFG_15_PVR4_SRC_SHIFT);
5684 break;
5685 default:
5686 break;
5687 }
5688 }
5689
5690
5691 // kaiser Only!!!
HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)5692 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)
5693 {
5694 switch (u32FileEng)
5695 {
5696 case 0: //File in Eng 0
5697 return E_FILEENG_TSIF1;
5698 case 1: //File in Eng 1
5699 return E_FILEENG_TSIF3;
5700 case 2: //File in Eng 2
5701 return E_FILEENG_TSIF0;
5702 case 3: //File in Eng 3
5703 return E_FILEENG_TSIF2;
5704 default:
5705 return E_FILEENG_INVALID;
5706 }
5707 }
5708
5709 // @NOTE for backward competible when calling flowset pvr
5710 // kaiser Only!!!
HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)5711 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)
5712 {
5713 switch(u32Eng)
5714 {
5715 case 0:
5716 return E_TSP_SRC_PKTDMX2;
5717 case 1:
5718 return E_TSP_SRC_PKTDMX3;
5719 case 2:
5720 return E_TSP_SRC_PKTDMX2;
5721 case 3:
5722 return E_TSP_SRC_PKTDMX3;
5723 default:
5724 return E_TSP_SRC_INVALID;
5725 }
5726 }
5727
5728 // kaiser Only!!!
HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF,MS_BOOL bFileIn)5729 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF, MS_BOOL bFileIn)
5730 {
5731 MS_U32 u32PhyTSIF = 0;
5732 switch (eTSIF)
5733 {
5734 case E_TSP_HAL_TSIF_0:
5735 if(bFileIn)
5736 u32PhyTSIF = TSP_TSIF1; // @NOTE tsif1 is used for playback0 file-in
5737 else
5738 u32PhyTSIF = TSP_TSIF0;
5739 break;
5740 case E_TSP_HAL_TSIF_1:
5741 if(bFileIn)
5742 u32PhyTSIF = TSP_TSIF3; // @NOTE tsif3 is used for playback0 file-in
5743 else
5744 u32PhyTSIF = TSP_TSIF2;
5745 break;
5746 case E_TSP_HAL_TSIF_2:
5747 if(bFileIn)
5748 u32PhyTSIF = TSP_TSIF0;
5749 else
5750 u32PhyTSIF = TSP_TSIF3;
5751 break;
5752 case E_TSP_HAL_TSIF_3:
5753 if(bFileIn)
5754 u32PhyTSIF = TSP_TSIF2;
5755 else
5756 u32PhyTSIF = TSP_TSIF1;
5757 break;
5758 case E_TSP_HAL_TSIF_PVR0:
5759 u32PhyTSIF = TSP_TSIF2;
5760 break;
5761 case E_TSP_HAL_TSIF_PVR1:
5762 u32PhyTSIF = TSP_TSIF3;
5763 break;
5764 case E_TSP_HAL_TSIF_PVR2:
5765 u32PhyTSIF = TSP_TSIF2;
5766 break;
5767 case E_TSP_HAL_TSIF_PVR3:
5768 u32PhyTSIF = TSP_TSIF3;
5769 break;
5770 default:
5771 printf("[PVR ERROR][%s][%d] mapping TSIF error\n",__FUNCTION__,__LINE__);
5772 break;
5773 }
5774
5775 return u32PhyTSIF;
5776 }
5777
5778
5779 // kaiser Only!!!
HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)5780 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)
5781 {
5782 // @NOTE we map hw pkt dmx setting to api layer flow at this function
5783
5784 TSP_PIDFLT_SRC ePidFltSrc = E_TSP_PIDFLT_INVALID;
5785
5786 switch (eSrc)
5787 {
5788 case E_TSP_SRC_PKTDMX0:
5789 ePidFltSrc = E_TSP_PIDFLT_LIVE0;
5790 break;
5791 case E_TSP_SRC_PKTDMX1:
5792 ePidFltSrc = E_TSP_PIDFLT_FILE0;
5793 break;
5794 case E_TSP_SRC_PKTDMX2:
5795 ePidFltSrc = E_TSP_PIDFLT_LIVE1;
5796 break;
5797 case E_TSP_SRC_PKTDMX3:
5798 ePidFltSrc = E_TSP_PIDFLT_FILE1;
5799 break;
5800 default:
5801 // @TODO add assert
5802 printf ("[TSP_ERR][%s][%d] Wrong Engine Source!!\n", __FUNCTION__,__LINE__);
5803 break;
5804 }
5805
5806 return ePidFltSrc;
5807 }
5808
HAL_TSP_GetDefaultFileinEng(void)5809 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void)
5810 {
5811 return E_FILEENG_TSIF1;
5812 }
5813
HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType,MS_U32 u32Eng)5814 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng)
5815 {
5816 if(eDstType == E_TSP_PIDFLT_DST_VIDEO)
5817 {
5818 switch(u32Eng)
5819 {
5820 case 0:
5821 return TSP_PIDFLT_OUT_VFIFO;
5822 case 1:
5823 return TSP_PIDFLT_OUT_VFIFO3D;
5824 case 2:
5825 return TSP_PIDFLT_OUT_VFIFO3;
5826 case 3:
5827 return TSP_PIDFLT_OUT_VFIFO4;
5828 default:
5829 printf("[TSP ERROR][%s][%d] mapping Vfifo eng error\n", __FUNCTION__, __LINE__);
5830 return 0;
5831 }
5832 }
5833 else if(eDstType == E_TSP_PIDFLT_DST_AUDIO)
5834 {
5835 switch(u32Eng)
5836 {
5837 case 0:
5838 return TSP_PIDFLT_OUT_AFIFO;
5839 case 1:
5840 return TSP_PIDFLT_OUT_AFIFO2;
5841 case 2:
5842 return TSP_PIDFLT_OUT_AFIFO3;
5843 case 3:
5844 return TSP_PIDFLT_OUT_AFIFO4;
5845 default:
5846 printf("[TSP ERROR][%s][%d] mapping Afifo eng error\n", __FUNCTION__, __LINE__);
5847 return 0;
5848 }
5849 }
5850 else if(eDstType == E_TSP_PIDFLT_DST_PVR)
5851 {
5852 switch(u32Eng)
5853 {
5854 case 0:
5855 return TSP_PIDFLT_OUT_PVR1;
5856 case 1:
5857 return TSP_PIDFLT_OUT_PVR2;
5858 case 2:
5859 return TSP_PIDFLT_OUT_PVR3;
5860 case 3:
5861 return TSP_PIDFLT_OUT_PVR4;
5862 default:
5863 printf("[TSP ERROR][%s][%d] mapping PVR eng error\n",__FUNCTION__,__LINE__);
5864 return 0;
5865 }
5866 }
5867 else
5868 {
5869 printf("[TSP ERROR][%s][%d] pid filter destination type error\n", __FUNCTION__, __LINE__);
5870 return 0;
5871 }
5872 }
5873
HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)5874 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)
5875 {
5876 MS_U32 u32Fq = 0;
5877
5878 switch (u32Tsif)
5879 {
5880 case 0:
5881 u32Fq = 0;
5882 break;
5883 case 1:
5884 u32Fq = 2;
5885 break;
5886 case 2:
5887 u32Fq = 3;
5888 break;
5889 case 3:
5890 u32Fq = 1;
5891 break;
5892 default:
5893 printf("[PVR ERROR][%s][%d] mapping TSIF:%u error\n",__FUNCTION__,__LINE__,(unsigned int)u32Tsif);
5894 break;
5895 }
5896
5897 return u32Fq;
5898 }
5899
HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)5900 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)
5901 {
5902 switch(u8Pad3WireId)
5903 {
5904 case 3:
5905 return E_TSP_TS_PAD_EXT3;
5906 case 4:
5907 return E_TSP_TS_PAD_EXT4;
5908 case 5:
5909 return E_TSP_TS_PAD_EXT5;
5910 case 6:
5911 return E_TSP_TS_PAD_EXT6;
5912 default:
5913 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] mapping 3WirePad:%u error\n",__FUNCTION__,__LINE__,u8Pad3WireId));
5914 return E_TSP_TS_PAD_INVALID;
5915 }
5916 }
5917
HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng,MS_BOOL bSet)5918 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng , MS_BOOL bSet)
5919 {
5920 if(bSet)
5921 {
5922 switch(u32PVREng)
5923 {
5924 case 0:
5925 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN);
5926 break;
5927 case 1:
5928 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN);
5929 break;
5930 case 2:
5931 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN);
5932 break;
5933 case 3:
5934 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN);
5935 break;
5936 default:
5937 break;
5938 }
5939 }
5940 else
5941 {
5942 switch(u32PVREng)
5943 {
5944 case 0:
5945 REG16_CLR(&_RegCtrl->reg160C, TSP_RECORD192_EN);
5946 break;
5947 case 1:
5948 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN);
5949 break;
5950 case 2:
5951 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN);
5952 break;
5953 case 3:
5954 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN);
5955 break;
5956 default:
5957 break;
5958 }
5959 }
5960 }
5961
HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)5962 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)
5963 {
5964 MS_U32 u32lpcr = 0;
5965 switch(u32PVREng)
5966 {
5967 case 0:
5968 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
5969
5970 u32lpcr = REG32_R(&_RegCtrl->PVR1_LPcr1);
5971
5972 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
5973
5974 return u32lpcr;
5975 case 1:
5976 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
5977
5978 u32lpcr = REG32_R(&_RegCtrl->PVR2_LPCR1);
5979
5980 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
5981 return u32lpcr;
5982 case 2:
5983 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
5984
5985 u32lpcr = REG32_R((&_RegCtrl2->CFG_62_63));
5986
5987 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
5988 return u32lpcr;
5989 case 3:
5990 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
5991
5992 u32lpcr = REG32_R((&_RegCtrl2->CFG_64_65));
5993
5994 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
5995 return u32lpcr;
5996 default:
5997 break;
5998 }
5999 return 0;
6000 }
6001
HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng,MS_U32 u32Stamp)6002 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng , MS_U32 u32Stamp)
6003 {
6004 switch(u32PVREng)
6005 {
6006 case 0:
6007 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD);
6008
6009 REG32_W(&_RegCtrl->PVR1_LPcr1, u32Stamp);
6010
6011 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD);
6012 break;
6013 case 1:
6014 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD);
6015
6016 REG32_W(&_RegCtrl->PVR2_LPCR1, u32Stamp);
6017
6018 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD);
6019 break;
6020 case 2:
6021 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD);
6022
6023 REG32_W((&_RegCtrl2->CFG_62_63), u32Stamp);
6024
6025 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD);
6026 break;
6027 case 3:
6028 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD);
6029
6030 REG32_W((&_RegCtrl2->CFG_64_65), u32Stamp);
6031
6032 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD);
6033 break;
6034 default:
6035 break;
6036 }
6037 }
6038
HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng,MS_U32 u32Stamp)6039 void HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng , MS_U32 u32Stamp)
6040 {
6041 switch(u32PVREng)
6042 {
6043 case 0:
6044 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0);
6045
6046 REG32_W(&_RegCtrl2->CFG_56_57, u32Stamp);
6047
6048 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0);
6049 break;
6050 case 1:
6051 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1);
6052
6053 REG32_W(&_RegCtrl2->CFG_58_59, u32Stamp);
6054
6055 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1);
6056 break;
6057 case 2:
6058 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2);
6059
6060 REG32_W(&_RegCtrl2->CFG_5A_5B, u32Stamp);
6061
6062 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2);
6063 break;
6064 case 3:
6065 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3);
6066
6067 REG32_W(&_RegCtrl2->CFG_5C_5D, u32Stamp);
6068
6069 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3);
6070 break;
6071 default:
6072 break;
6073 }
6074 }
6075
HAL_PVR_Alignment_Enable(MS_U32 u32PVREng,MS_BOOL bEnable)6076 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable)
6077 {
6078 if(bEnable)
6079 {
6080 switch(u32PVREng)
6081 {
6082 case 0:
6083 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN);
6084 break;
6085 case 1:
6086 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN);
6087 break;
6088 case 2:
6089 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN);
6090 break;
6091 case 3:
6092 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN);
6093 break;
6094 default:
6095 break;
6096 }
6097 }
6098 else
6099 {
6100 switch(u32PVREng)
6101 {
6102 case 0:
6103 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN);
6104 break;
6105 case 1:
6106 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN);
6107 break;
6108 case 2:
6109 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN);
6110 break;
6111 case 3:
6112 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN);
6113 break;
6114 default:
6115 break;
6116 }
6117 }
6118 }
6119
HAL_PVR_FlushData(MS_U32 u32PVREng)6120 void HAL_PVR_FlushData(MS_U32 u32PVREng)
6121 {
6122 switch(u32PVREng)
6123 {
6124 case 0:
6125 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA);
6126 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA);
6127 break;
6128 case 1:
6129 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA);
6130 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA);
6131 break;
6132 case 2:
6133 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR2_DATA);
6134 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR2_DATA);
6135 break;
6136 case 3:
6137 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR3_DATA);
6138 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR3_DATA);
6139 break;
6140 default:
6141 break;
6142 }
6143 }
6144
HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)6145 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)
6146 {
6147 if(bSkip)
6148 {
6149 switch(u32PVREng)
6150 {
6151 case 0:
6152 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN);
6153 break;
6154 case 1:
6155 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN);
6156 break;
6157 case 2:
6158 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN);
6159 break;
6160 case 3:
6161 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR4_EN);
6162 break;
6163 default:
6164 break;
6165 }
6166 }
6167 else
6168 {
6169 switch(u32PVREng)
6170 {
6171 case 0:
6172 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN);
6173 break;
6174 case 1:
6175 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN);
6176 break;
6177 case 2:
6178 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN);
6179 break;
6180 case 3:
6181 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR4_EN);
6182 break;
6183 default:
6184 break;
6185 }
6186 }
6187 }
6188
6189
HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)6190 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)
6191 {
6192 if(bDisable)
6193 {
6194 switch(u32PVREng)
6195 {
6196 case 0:
6197 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS);
6198 break;
6199 case 1:
6200 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS);
6201 break;
6202 case 2:
6203 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS);
6204 break;
6205 case 3:
6206 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS);
6207 break;
6208 default:
6209 break;
6210 }
6211 }
6212 else
6213 {
6214 switch(u32PVREng)
6215 {
6216 case 0:
6217 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS);
6218 break;
6219 case 1:
6220 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS);
6221 break;
6222 case 2:
6223 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS);
6224 break;
6225 case 3:
6226 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS);
6227 break;
6228 default:
6229 break;
6230 }
6231
6232 }
6233 }
6234
HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)6235 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)
6236 {
6237 switch(u32PVREng)
6238 {
6239 case 0:
6240 REG16_MSK_W(&_RegCtrl->reg15b8, TSP_BURST_LEN_MASK, (u16BurstMode << TSP_BURST_LEN_SHIFT));
6241 break;
6242 case 1:
6243 REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_SHIFT));
6244 break;
6245 case 2:
6246 REG16_MSK_W(&_RegCtrl2->CFG_16, CFG_16_PVR3_BURST_LEN_MASK, (u16BurstMode << CFG_16_PVR3_BURST_LEN_SHIFT));
6247 break;
6248 case 3:
6249 REG16_MSK_W(&_RegCtrl2->CFG_23, CFG_23_PVR4_BURST_LEN_MASK, (u16BurstMode << CFG_23_PVR4_BURST_LEN_SHIFT));
6250 break;
6251 default:
6252 break;
6253 }
6254 }
6255
HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng,MS_BOOL bLocal_Stream)6256 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream)
6257 {
6258 if (u32PVREng>=TSP_PVRENG_NUM)
6259 {
6260 return;
6261 }
6262
6263 if (bLocal_Stream) //Stream
6264 {
6265 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng));
6266 }
6267 else //local
6268 {
6269 REG16_CLR((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng));
6270 }
6271 }
6272
HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)6273 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)
6274 {
6275 if(bEnable)
6276 {
6277 switch(u32PVREng)
6278 {
6279 case 0:
6280 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1);
6281 break;
6282 case 1:
6283 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2);
6284 break;
6285 case 2:
6286 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3);
6287 break;
6288 case 3:
6289 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4);
6290 break;
6291 default:
6292 break;
6293 }
6294 }
6295 else
6296 {
6297 switch(u32PVREng)
6298 {
6299 case 0:
6300 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1);
6301 break;
6302 case 1:
6303 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2);
6304 break;
6305 case 2:
6306 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3);
6307 break;
6308 case 3:
6309 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4);
6310 break;
6311 default:
6312 break;
6313 }
6314 }
6315 }
6316
HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)6317 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)
6318 {
6319 switch(u32PVREng)
6320 {
6321 case 0:
6322 REG32_W(&_RegCtrl3->CFG3_44_45, u32PauseTime);
6323 break;
6324 case 1:
6325 REG32_W(&_RegCtrl3->CFG3_46_47, u32PauseTime);
6326 break;
6327 case 2:
6328 REG32_W(&_RegCtrl3->CFG3_48_49, u32PauseTime);
6329 break;
6330 case 3:
6331 REG32_W(&_RegCtrl3->CFG3_4A_4B, u32PauseTime);
6332 break;
6333 default:
6334 break;
6335 }
6336 }
6337
HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId,MS_BOOL bEnable)6338 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId, MS_BOOL bEnable)
6339 {
6340 if (bEnable)
6341 {
6342 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2));
6343 }
6344 else
6345 {
6346 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2));
6347 }
6348 }
6349
HAL_PVR_MOBF_Enable(MS_U32 u32PVREng,MS_BOOL bEnable,MS_U32 u32Key)6350 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key)
6351 {
6352 switch(u32PVREng)
6353 {
6354 case 0:
6355 REG16_W(&_RegCtrl->MOBF_PVR1_Index[0], (u32Key & TSP_MOBF_PVR1_INDEX_MASK));
6356 break;
6357 case 1:
6358 REG16_W(&_RegCtrl->MOBF_PVR2_Index[0], (u32Key & TSP_MOBF_PVR2_INDEX_MASK));
6359 break;
6360 case 2:
6361 REG16_W(&_RegCtrl2->CFG_78_7B[0], (u32Key & CFG_78_PVR3_INDEX));
6362 break;
6363 case 3:
6364 REG16_W(&_RegCtrl2->CFG_78_7B[2], (u32Key & CFG_78_PVR3_INDEX));
6365 break;
6366 default:
6367 break;
6368 }
6369 }
6370
6371 /*
6372 void HAL_PVR_SetTSIF(MS_U32 u32PVREng , MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP)
6373 {
6374 if (bPara)
6375 {
6376 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
6377 }
6378 else
6379 {
6380 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
6381 }
6382
6383 if (bExtSync)
6384 {
6385 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
6386 }
6387 else
6388 {
6389 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
6390 }
6391
6392 if (bDataSWP)
6393 {
6394 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
6395 }
6396 else
6397 {
6398 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
6399 }
6400 }
6401
6402 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis)
6403 {
6404 if(bDis)
6405 {
6406 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
6407 }
6408 else
6409 {
6410 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
6411 }
6412 }
6413
6414 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn)
6415 {
6416 if(bEn)
6417 {
6418 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
6419 }
6420 else
6421 {
6422 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
6423 }
6424 }
6425 */
6426
HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)6427 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)
6428 {
6429 MS_U32 u32Data;
6430
6431 //reserved
6432 switch (u32Type)
6433 {
6434
6435 case INFO_FW_VERSION:
6436 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
6437 break;
6438 case INFO_FW_DATE:
6439 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE);
6440 break;
6441 default:
6442 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
6443 break;
6444
6445 }
6446
6447 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO);
6448
6449 _delay(10); // supposed TSP is able to respond in 10us
6450 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6451 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6452
6453 return u32Data;
6454 }
6455
HAL_TSP_HCMD_BufRst(MS_U32 u32Value)6456 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value)
6457 {
6458 // MS_U32 u32Data;
6459
6460 REG32_W(&_RegCtrl->MCU_Data0 , u32Value);
6461 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST);
6462 _delay(10); // supposed TSP is able to respond in 10us
6463
6464 return TRUE;
6465 }
6466
HAL_TSP_HCMD_Read(MS_U32 u32Addr)6467 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr)
6468 {
6469 MS_U32 u32Data;
6470
6471 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
6472 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ);
6473
6474 _delay(10); // supposed TSP is able to respond in 10us
6475 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6476 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6477
6478 return u32Data;
6479 }
6480
6481
HAL_TSP_HCMD_Write(MS_U32 u32Addr,MS_U32 u32Value)6482 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value)
6483 {
6484 MS_U32 u32Data;
6485
6486 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
6487 REG32_W(&_RegCtrl->MCU_Data1, u32Value);
6488 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE);
6489
6490 _delay(10); // supposed TSP is able to respond in 10us
6491 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6492 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6493
6494 return TRUE;
6495 }
6496
6497
HAL_TSP_HCMD_Alive(void)6498 MS_BOOL HAL_TSP_HCMD_Alive(void)
6499 {
6500 MS_U32 u32Data;
6501
6502 REG32_W(&_RegCtrl->MCU_Data1, 0);
6503 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD
6504 _delay(10); // supposed TSP is able to respond in 10us
6505 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6506 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6507
6508 return (u32Data == TSP_MCU_DATA_ALIVE)? TRUE : FALSE;
6509 }
6510
HAL_TSP_HCMD_SET(MS_U32 mcu_cmd,MS_U32 mcu_data0,MS_U32 mcu_data1)6511 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1)
6512 {
6513 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0);
6514 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1);
6515 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd);
6516 }
6517
HAL_TSP_HCMD_GET(MS_U32 * pmcu_cmd,MS_U32 * pmcu_data0,MS_U32 * pmcu_data1)6518 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1)
6519 {
6520 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd);
6521 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0);
6522 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1);
6523 }
6524
HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId,MS_BOOL bDis)6525 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis)
6526 {
6527 MS_U32 u32Data = bDis ;
6528
6529 REG32_W(&_RegCtrl->MCU_Data0, FltId);
6530 REG32_W(&_RegCtrl->MCU_Data1,u32Data);
6531 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here
6532 _delay(10); // supposed TSP is able to respond in 10us
6533 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6534
6535 return ;
6536 }
6537
HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)6538 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)
6539 {
6540 MS_U32 u32Data;
6541
6542 REG32_W(&_RegCtrl->MCU_Data0, u32Enable);
6543 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG);
6544
6545 _delay(10); // supposed TSP is able to respond in 10us
6546 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6547 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6548
6549 return REG32_R(&_RegCtrl->MCU_Data1);
6550 }
6551
HAL_TSP_GetDBGStatus(MS_U16 u16Sel)6552 MS_U32 HAL_TSP_GetDBGStatus(MS_U16 u16Sel)
6553 {
6554 REG16_CLR(&_RegCtrl->DBG_SEL, TSP_DBG_SEL_MASK);
6555 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK));
6556
6557 return REG32_R(&_RegCtrl->TSP_Debug);
6558 }
6559
6560 // [ToDo...]
HAL_TSP_INT_Enable(MS_U32 u32Mask)6561 void HAL_TSP_INT_Enable(MS_U32 u32Mask)
6562 {
6563 // u32Mask [0:7] for bank 0x15 7e bit[0:7]
6564 /*
6565 7: audio/video packet error
6566 6: DMA read done
6567 5: HK_INT_FORCE. // it's trigure bit is at bank 15 44 bit[15]
6568 4: TSP_FILE_RP meets TSP_FILE_TAIL.
6569 3: TSP_FILE_RP meets TSP_FILE_MID.
6570 2: HK_INT_FORCE. // it's trigure bit is at bank 15 39 bit[15]
6571 1: STR2MI_WADR meets STR2MI_MID.
6572 0: STR2MI_WADR meets STR2MI_TAIL."
6573 */
6574 REG16_SET(&_RegCtrl->HwInt_Stat, (TSP_HWINT_EN_MASK & u32Mask) | TSP_HWINT_STATUS_MASK);
6575
6576 // u32Mask [8:15] for bank 0x16 6c bit[0:7]
6577 /*
6578 [7] : PVR2 meet_tail or PVR2_meet_mid
6579 [6] : vq0, vq1, vq2, vq3 overflow interrupt
6580 [5] : all DMA write address not in the protect zone interrupt
6581 [4] : PVR_cb meet the mid or PVR_cb meet the tail
6582 [3] : pcr filter 0 update finish
6583 [2] : pcr filter 1 update finish
6584 [1] : OTV HW interrupt
6585 [0] : reserved
6586 */
6587 REG16_SET(&_RegCtrl->HwInt2_Stat, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK);
6588
6589 // u32Mask [16:23] for bank 0x16 6f bit[0:7]
6590 /*
6591 [7:2] : reserved
6592 [1] : pcr filter 3 update finish
6593 [0] : pcr filter 2 update finish
6594 */
6595 REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16)) | TSP_HWINT3_STATUS_MASK);
6596 }
6597
6598
6599 // [ToDo...]
HAL_TSP_INT_Disable(MS_U32 u32Mask)6600 void HAL_TSP_INT_Disable(MS_U32 u32Mask)
6601 {
6602 //REG16_CLR(&_RegCtrl->HwInt_Stat, TSP_HWINT_EN_MASK & u32Mask);
6603 //REG16_CLR(&_RegCtrl->HwInt2_Stat, TSP_HWINT2_EN_MASK & (u32Mask >> 8));
6604
6605 REG16_W(&_RegCtrl->HwInt_Stat,
6606 (REG16_R(&_RegCtrl->HwInt_Stat) & ~(TSP_HWINT_EN_MASK & (u32Mask))) |
6607 TSP_HWINT_STATUS_MASK);
6608
6609 REG16_W(&_RegCtrl->HwInt2_Stat,
6610 (REG16_R(&_RegCtrl->HwInt2_Stat) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) |
6611 TSP_HWINT2_STATUS_MASK);
6612
6613 REG16_W(&_RegCtrl->HwInt3_Stat,
6614 (REG16_R(&_RegCtrl->HwInt3_Stat) & ~(TSP_HWINT3_EN_MASK & (u32Mask >> 16))) |
6615 TSP_HWINT3_STATUS_MASK);
6616 }
6617
6618
6619 // [ToDo...]
HAL_TSP_INT_ClrHW(MS_U32 u32Mask)6620 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask)
6621 {
6622 //REG16_CLR(&_RegCtrl->HwInt_Stat, (u32Mask & 0x00FF) << 8);
6623 //REG16_CLR(&_RegCtrl->HwInt2_Stat, u32Mask & 0xFF00);
6624
6625 REG16_W(&_RegCtrl->HwInt_Stat,
6626 (REG16_R(&_RegCtrl->HwInt_Stat) & (~TSP_HWINT_STATUS_MASK)) |
6627 (((~u32Mask) << TSP_HWINT_STATUS_SHIFT) & TSP_HWINT_STATUS_MASK) );
6628
6629 REG16_W(&_RegCtrl->HwInt2_Stat,
6630 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) |
6631 (((~(u32Mask >> 8))<< TSP_HWINT2_STATUS_SHIFT) & TSP_HWINT2_STATUS_MASK) );
6632
6633 REG16_W(&_RegCtrl->HwInt3_Stat,
6634 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) |
6635 (((~(u32Mask >> 16))<< TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATUS_MASK) );
6636 }
6637
6638 // [ToDo...]
HAL_TSP_INT_GetHW(void)6639 MS_U32 HAL_TSP_INT_GetHW(void)
6640 {
6641 MS_U32 status;
6642
6643 status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS_SHIFT) << 16);
6644
6645 status |= ((MS_U32)(((REG16_R(&_RegCtrl->HwInt2_Stat) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STATUS_SHIFT) << 8));
6646
6647 status |= ((MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_SHIFT));
6648
6649 return (status & 0x00FFFFFF);
6650 }
6651
HAL_TSP_INT_ClrSW(void)6652 void HAL_TSP_INT_ClrSW(void)
6653 {
6654 REG32_W(&_RegCtrl->SwInt_Stat, 0);
6655 }
6656
HAL_TSP_INT_GetSW(void)6657 MS_U32 HAL_TSP_INT_GetSW(void)
6658 {
6659 return REG32_R(&_RegCtrl->SwInt_Stat);
6660 }
6661
HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx,MS_U32 inputSrc)6662 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc)
6663 {
6664 switch (bufIdx)
6665 {
6666 case 0:
6667 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF0_SRC, inputSrc<<(bufIdx * 2));
6668 break;
6669 case 1:
6670 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF1_SRC, inputSrc<<(bufIdx * 2));
6671 break;
6672 case 2:
6673 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF2_SRC, inputSrc<<(bufIdx * 2));
6674 break;
6675 case 3:
6676 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF3_SRC, inputSrc<<(bufIdx * 2));
6677 break;
6678 default:
6679 break;
6680 }
6681 }
6682
HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)6683 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)
6684 {
6685 if (bByPassEn)
6686 {
6687 REG16_SET(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_TSIF2_BYPASS | CFG3_52_SPD_TSIF3_BYPASS);
6688 }
6689 else
6690 {
6691 REG16_CLR(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_TSIF2_BYPASS | CFG3_52_SPD_TSIF3_BYPASS);
6692 }
6693 }
6694
6695 //@TODO
6696 #if 1
HAL_TSP_FileIn_SPDConfig(MS_U32 tsif,MS_BOOL CTR_mode)6697 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode)
6698 {
6699 if(CTR_mode == TRUE)
6700 {
6701 printf("SPD CTR mode = %p\n",&(_RegCtrl7[tsif].CFG7_05));
6702 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable
6703 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[0]), 0x0000); //set counter IV
6704 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[1]), 0x0000);
6705 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[2]), 0x0000);
6706 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[3]), 0x0000);
6707 REG16_W(&(_RegCtrl7[tsif].CFG7_04), CFG7_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld
6708 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV
6709 }
6710
6711 switch(tsif)
6712 {
6713 case 0: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI0_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6714 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6715 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6716 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6717 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6718 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6719 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6720 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6721 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6722 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY0);
6723 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF0_BYPASS);//bypass SPD
6724 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET); //TSIF SPD reset
6725 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET);
6726 break;
6727 case 1: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI1_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6728 /*
6729 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x2222); //file-in SPD key
6730 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x2222);
6731 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x2222);
6732 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x2222);
6733 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x3333);
6734 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x3333);
6735 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x3333);
6736 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x3333);
6737 */
6738 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6739 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6740 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6741 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6742 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6743 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6744 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6745 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6746 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY1);
6747 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF1_BYPASS);//bypass SPD
6748 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET); //TSIF SPD reset
6749 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET);
6750 break;
6751 case 2: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI2_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6752 /*
6753 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x4444); //file-in SPD key
6754 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x4444);
6755 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x4444);
6756 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x4444);
6757 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x5555);
6758 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x5555);
6759 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x5555);
6760 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x5555);
6761 */
6762 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6763 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6764 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6765 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6766 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6767 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6768 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6769 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6770 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY2);
6771 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF2_BYPASS);//bypass SPD
6772 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET); //TSIF SPD reset
6773 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET);
6774 break;
6775 case 3: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI3_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6776 /*
6777 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x6666); //file-in SPD key
6778 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x6666);
6779 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x6666);
6780 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x6666);
6781 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x7777);
6782 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x7777);
6783 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x7777);
6784 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x7777);
6785 */
6786 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6787 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6788 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6789 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6790 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6791 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6792 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6793 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6794 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY3);
6795 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF3_BYPASS);//bypass SPD
6796 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF3_SPD_RESET); //TSIF SPD reset
6797 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF3_SPD_RESET);
6798 break;
6799 default:printf("Not Support !!\n");
6800 break;
6801 }
6802 }
6803 #endif
6804
6805 // for TSO
HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId,MS_U32 u32TSOEng,MS_BOOL bEn)6806 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn)
6807 {
6808 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
6809 if(bEn)
6810 {
6811 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_TSOFLT_MASK) | (((1 << u32TSOEng) << TSP_PIDFLT_TSOFLT_SHFT) & TSP_PIDFLT_TSOFLT_MASK));
6812 }
6813 else
6814 {
6815 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~(((1 << u32TSOEng) << TSP_PIDFLT_TSOFLT_SHFT) & TSP_PIDFLT_TSOFLT_MASK)));
6816 }
6817 }
6818
HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap,MS_U32 * pu32CapInfo)6819 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo)
6820 {
6821 switch (eCap)
6822 {
6823 case E_TSP_HAL_CAP_TYPE_PIDFLT_NUM :
6824 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PIDFLT_NUM;
6825 break;
6826
6827 case E_TSP_HAL_CAP_TYPE_SECFLT_NUM :
6828 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECFLT_NUM;
6829 break;
6830
6831 case E_TSP_HAL_CAP_TYPE_SECBUF_NUM :
6832 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_NUM;
6833 break;
6834
6835 case E_TSP_HAL_CAP_TYPE_RECENG_NUM :
6836 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECENG_NUM;
6837 break;
6838
6839 case E_TSP_HAL_CAP_TYPE_RECFLT_NUM :
6840 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_NUM;
6841 break;
6842
6843 case E_TSP_HAL_CAP_TYPE_TSIF_NUM :
6844 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSIF_NUM;
6845 break;
6846
6847 case E_TSP_HAL_CAP_TYPE_DEMOD_NUM :
6848 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_DEMOD_NUM;
6849 break;
6850
6851 case E_TSP_HAL_CAP_TYPE_TSPAD_NUM :
6852 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSPAD_NUM;
6853 break;
6854
6855 case E_TSP_HAL_CAP_TYPE_VQ_NUM :
6856 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_NUM;
6857 break;
6858
6859 case E_TSP_HAL_CAP_TYPE_CAFLT_NUM :
6860 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAFLT_NUM;
6861 break;
6862
6863 case E_TSP_HAL_CAP_TYPE_CAKEY_NUM :
6864 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAKEY_NUM;
6865 break;
6866
6867 case E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN :
6868 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_ALIGN;
6869 break;
6870
6871 case E_TSP_HAL_CAP_TYPE_PVR_ALIGN:
6872 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PVR_ALIGN;
6873 break;
6874
6875 case E_TSP_HAL_CAP_TYPE_FW_ALIGN :
6876 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_ALIGN;
6877 break;
6878
6879 case E_TSP_HAL_CAP_TYPE_VQ_ALIGN :
6880 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_ALIGN;
6881 break;
6882
6883 case E_TSP_HAL_CAP_TYPE_VQ_PITCH :
6884 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_PITCH;
6885 break;
6886
6887 case E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM:
6888 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM;
6889 break;
6890
6891 case E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM:
6892 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM;
6893 break;
6894
6895 case E_TSP_HAL_CAP_TYPE_HW_TYPE:
6896 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HW_TYPE;
6897 break;
6898
6899 case E_TSP_HAL_CAP_TYPE_RECFLT_IDX :
6900 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_IDX;
6901 break;
6902
6903 case E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX :
6904 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX;
6905 break;
6906
6907 case E_TSP_HAL_CAP_TYPE_VFIFO_NUM:
6908 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VFIFO_NUM;
6909 break;
6910
6911 case E_TSP_HAL_CAP_TYPE_AFIFO_NUM:
6912 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_AFIFO_NUM;
6913 break;
6914
6915 case E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT:
6916 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT;
6917 break;
6918
6919 case E_TSP_HAL_CAP_FIQ_NUM:
6920 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FIQ_NUM;
6921 break;
6922
6923 case E_TSP_HAL_CAP_FW_BUF_SIZE:
6924 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_BUF_SIZE;
6925 break;
6926 case E_TSP_HAL_CAP_FW_BUF_RANGE:
6927 *(pu32CapInfo) = TSP_FW_BUF_LOW_BUD;
6928 *(pu32CapInfo + 1) = TSP_FW_BUF_UP_BUD;
6929 break;
6930 case E_TSP_HAL_CAP_VQ_BUF_RANGE:
6931 *(pu32CapInfo) = TSP_VQ_BUF_LOW_BUD;
6932 *(pu32CapInfo + 1) = TSP_VQ_BUF_UP_BUD;
6933 break;
6934 case E_TSP_HAL_CAP_SEC_BUF_RANGE:
6935 *(pu32CapInfo) = TSP_SEC_BUF_LOW_BUD;
6936 *(pu32CapInfo + 1) = TSP_SEC_BUF_UP_BUD;
6937 break;
6938 default:
6939 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_NULL;
6940 return FALSE;
6941 }
6942
6943 return TRUE;
6944 }
6945
HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)6946 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)
6947 {
6948 if(bEnable)
6949 {
6950 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
6951 }
6952 else
6953 {
6954 REG16_CLR(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
6955 }
6956 }
6957
HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType,MS_BOOL bEnable)6958 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable)
6959 {
6960 if(bEnable)
6961 {
6962 switch (eHalPktType)
6963 {
6964 case E_TSP_HAL_TEI_REMOVE_AUDIO_PKT:
6965 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN);
6966 break;
6967 case E_TSP_HAL_TEI_REMOVE_VIDEO_PKT:
6968 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN);
6969 break;
6970 default:
6971 break;
6972 }
6973 }
6974 else
6975 {
6976 switch (eHalPktType)
6977 {
6978 case E_TSP_HAL_TEI_REMOVE_AUDIO_PKT:
6979 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN);
6980 break;
6981 case E_TSP_HAL_TEI_REMOVE_VIDEO_PKT:
6982 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN);
6983 break;
6984 default:
6985 break;
6986 }
6987 }
6988 }
6989
HAL_TSP_TEI_SKIP(MS_U32 tsIf,MS_BOOL bEnable)6990 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable)
6991 {
6992 if(bEnable)
6993 {
6994 switch (tsIf)
6995 {
6996 case 0:
6997 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0);
6998 break;
6999 case 1:
7000 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1);
7001 break;
7002 case 2:
7003 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2);
7004 break;
7005 case 3:
7006 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3);
7007 break;
7008 default:
7009 break;
7010 }
7011 }
7012 else
7013 {
7014 switch (tsIf)
7015 {
7016 case 0:
7017 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0);
7018 break;
7019 case 1:
7020 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1);
7021 break;
7022 case 2:
7023 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2);
7024 break;
7025 case 3:
7026 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3);
7027 break;
7028 default:
7029 break;
7030 }
7031 }
7032
7033 }
7034
HAL_TSP_DisPKTCnt_Clear(TSP_DST_SEQ eFltType)7035 void HAL_TSP_DisPKTCnt_Clear(TSP_DST_SEQ eFltType)
7036 {
7037 switch (eFltType)
7038 {
7039 case E_TSP_DST_FIFO_VIDEO :
7040 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
7041 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
7042 break;
7043 case E_TSP_DST_FIFO_VIDEO3D:
7044 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
7045 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
7046 break;
7047 case E_TSP_DST_FIFO_AUDIO :
7048 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
7049 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
7050 break;
7051 case E_TSP_DST_FIFO_AUDIO2 :
7052 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
7053 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
7054 break;
7055 case E_TSP_DST_FIFO_AUDIO3 :
7056 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
7057 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
7058 break;
7059 case E_TSP_DST_FIFO_AUDIO4 :
7060 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
7061 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
7062 break;
7063 default :
7064 printf("[%s][%s][%d] Clear AVPktNum Error\n",__FILE__,__FUNCTION__,__LINE__);
7065 break;
7066 }
7067 }
7068
_HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)7069 static MS_PHY _HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)
7070 {
7071 #ifdef HAL_MIU2_BASE
7072 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
7073 return (MS_PHY)HAL_MIU2_BASE;
7074 else
7075 #endif //HAL_MIU2_BUS_BASE
7076
7077 #ifdef HAL_MIU1_BASE
7078 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
7079 return (MS_PHY)HAL_MIU1_BASE;
7080 else
7081 #endif //HAL_MIU1_BUS_BASE
7082 return (MS_PHY)HAL_MIU0_BASE;
7083 }
7084
HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)7085 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)
7086 {
7087 if(bEn == TRUE)
7088 {
7089 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN);
7090 }
7091 else
7092 {
7093 REG16_CLR(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN);
7094 }
7095 }
7096
HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH,MS_PHY u32AddrL)7097 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL)
7098 {
7099 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
7100
7101 REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK));
7102 REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK));
7103 }
7104
HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)7105 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)
7106 {
7107
7108 if(bEn == TRUE)
7109 {
7110 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
7111 }
7112 else
7113 {
7114 REG16_CLR(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
7115 }
7116 }
7117
HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID,MS_PHY u32AddrH,MS_PHY u32AddrL)7118 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL)
7119 {
7120 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
7121 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_DMAW_BND_MASK);
7122 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_DMAW_BND_MASK);
7123
7124 switch(u8SecID)
7125 {
7126 case 0:
7127 REG32_W(&_RegCtrl->DMAW_LBND0,u32LBnd);
7128 REG32_W(&_RegCtrl->DMAW_UBND0,u32UBnd);
7129 break;
7130 case 1:
7131 REG32_W(&_RegCtrl->DMAW_LBND1,u32LBnd);
7132 REG32_W(&_RegCtrl->DMAW_UBND1,u32UBnd);
7133 break;
7134 default:
7135 break;
7136 }
7137 }
7138
HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)7139 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)
7140 {
7141 if(bEnable)
7142 {
7143 switch(u32PVREng)
7144 {
7145 case 0:
7146 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN);
7147 break;
7148 case 1:
7149 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN);
7150 break;
7151 case 2:
7152 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR3_DMAW_PROTECT_EN);
7153 break;
7154 case 3:
7155 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR4_DMAW_PROTECT_EN);
7156 break;
7157 default:
7158 break;
7159 }
7160 }
7161 else
7162 {
7163 switch(u32PVREng)
7164 {
7165 case 0:
7166 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN);
7167 break;
7168 case 1:
7169 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN);
7170 break;
7171 case 2:
7172 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR3_DMAW_PROTECT_EN);
7173 break;
7174 case 3:
7175 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR4_DMAW_PROTECT_EN);
7176 break;
7177 default:
7178 break;
7179 }
7180 }
7181 }
7182
HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32AddrH,MS_PHY u32AddrL)7183 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32AddrH, MS_PHY u32AddrL)
7184 {
7185 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
7186 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_PVR_MASK);
7187 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_PVR_MASK);
7188
7189 switch(u32PVREng)
7190 {
7191 case 0:
7192 REG32_W(&_RegCtrl->DMAW_LBND2, u32LBnd);
7193 REG32_W(&_RegCtrl->DMAW_UBND2, u32UBnd);
7194 break;
7195 case 1:
7196 REG32_W(&_RegCtrl->DMAW_LBND3, u32LBnd);
7197 REG32_W(&_RegCtrl->DMAW_UBND3, u32UBnd);
7198 break;
7199 case 2:
7200 REG32_W(&_RegCtrl->DMAW_LBND4, u32LBnd);
7201 REG32_W(&_RegCtrl->DMAW_UBND4, u32UBnd);
7202 break;
7203 case 3:
7204 REG32_W(&_RegCtrl3->CFG3_12_13, u32LBnd);
7205 REG32_W(&_RegCtrl3->CFG3_14_15, u32UBnd);
7206 break;
7207 default:
7208 break;
7209 }
7210 }
7211
HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)7212 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)
7213 {
7214 if(bEnable)
7215 {
7216 switch(eFileEng)
7217 {
7218 case E_FILEENG_TSIF0:
7219 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN);
7220 break;
7221 case E_FILEENG_TSIF1:
7222 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN);
7223 break;
7224 case E_FILEENG_TSIF2:
7225 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN);
7226 break;
7227 case E_FILEENG_TSIF3:
7228 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN3_DMAR_PROTECT_EN);
7229 break;
7230 default:
7231 break;
7232 }
7233 }
7234 else
7235 {
7236 switch(eFileEng)
7237 {
7238 case E_FILEENG_TSIF0:
7239 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN);
7240 break;
7241 case E_FILEENG_TSIF1:
7242 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN);
7243 break;
7244 case E_FILEENG_TSIF2:
7245 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN);
7246 break;
7247 case E_FILEENG_TSIF3:
7248 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN3_DMAR_PROTECT_EN);
7249 break;
7250 default:
7251 break;
7252 }
7253 }
7254 }
7255
HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH,MS_PHY u32AddrL)7256 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL)
7257 {
7258 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
7259 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK);
7260 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK);
7261
7262 switch(eFileEng)
7263 {
7264 case E_FILEENG_TSIF0:
7265 REG32_W(&_RegCtrl6->CFG6_30_31, u32LBnd);
7266 REG32_W(&_RegCtrl6->CFG6_32_33, u32UBnd);
7267 break;
7268 case E_FILEENG_TSIF1:
7269 REG32_W(&_RegCtrl6->CFG6_34_35, u32LBnd);
7270 REG32_W(&_RegCtrl6->CFG6_36_37, u32UBnd);
7271 break;
7272 case E_FILEENG_TSIF2:
7273 REG32_W(&_RegCtrl6->CFG6_38_39, u32LBnd);
7274 REG32_W(&_RegCtrl6->CFG6_3A_3B, u32UBnd);
7275 break;
7276 case E_FILEENG_TSIF3:
7277 REG32_W(&_RegCtrl6->CFG6_3C_3D, u32LBnd);
7278 REG32_W(&_RegCtrl6->CFG6_3E_3F, u32UBnd);
7279 break;
7280 default:
7281 break;
7282 }
7283 }
7284
HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)7285 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)
7286 {
7287 if(bEnable)
7288 {
7289 switch(u32MMFIEng)
7290 {
7291 case 0:
7292 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN);
7293 break;
7294 case 1:
7295 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN);
7296 break;
7297 default:
7298 break;
7299 }
7300 }
7301 else
7302 {
7303 switch(u32MMFIEng)
7304 {
7305 case 0:
7306 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN);
7307 break;
7308 case 1:
7309 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN);
7310 break;
7311 default:
7312 break;
7313 }
7314 }
7315 }
7316
HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH,MS_PHY u32AddrL)7317 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL)
7318 {
7319 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
7320 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK);
7321 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK);
7322
7323 switch(u32MMFIEng)
7324 {
7325 case 0:
7326 REG32_W(&_RegCtrl6->CFG6_48_49, u32LBnd);
7327 REG32_W(&_RegCtrl6->CFG6_4A_4B, u32UBnd);
7328 break;
7329 case 1:
7330 REG32_W(&_RegCtrl6->CFG6_4C_4D, u32LBnd);
7331 REG32_W(&_RegCtrl6->CFG6_4E_4F, u32UBnd);
7332 break;
7333 default:
7334 break;
7335 }
7336 }
7337
7338
HAL_TSP_SaveFltState(void)7339 void HAL_TSP_SaveFltState(void)
7340 {
7341 MS_U32 u32Size;
7342 TSP32 * pRegEnd;
7343 TSP32 * pReg;
7344 int i, j;
7345
7346 for (i = 0; i < TSP_PIDFLT_NUM; i++)
7347 {
7348 _u32PidFltReg[i] = TSP32_IdrR(&(_REGPid0->Flt[i]));
7349 _u32PidDstReg[i] = TSP32_IdrR(&(_REGPid1->Flt[i]));
7350 }
7351
7352 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x50))/sizeof(TSP32);
7353 for (i = 0; i < TSP_SECFLT_NUM; i++)
7354 {
7355 pReg = (TSP32*)&(_REGSec->Flt[i]);
7356 pRegEnd = pReg + u32Size;
7357 j = 0;
7358 for ( ; pReg < pRegEnd; pReg++)
7359 {
7360 _u32SecReg[i*u32Size+j] = TSP32_IdrR(pReg);
7361 j++;
7362 }
7363 }
7364 }
7365
HAL_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,MS_U32 * pData)7366 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData)
7367 {
7368 MS_U32 u32Data = 0;
7369 MS_BOOL brtn = FALSE;
7370
7371 //printf("\033[31m [%s] Mode = %lX , Config0 =%lX , Config1 = %lX \033[m\n",__FUNCTION__,u32Cmd,u32Config0,u32Config1); // Eason test
7372
7373 switch (u32Cmd)
7374 {
7375 case HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK:
7376 REG32_W(&_RegCtrl->MCU_Data1, u32Config0);
7377 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SEC_CC_CHECK_DISABLE);
7378 _delay(10); // supposed TSP is able to respond in 10us
7379 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
7380 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
7381 brtn = (u32Data == TSP_MCU_CMD_SEC_CC_CHECK_DISABLE)? TRUE : FALSE;
7382 break;
7383 default:
7384 break;
7385 }
7386 return brtn;
7387 }
7388
HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng,MS_BOOL bEnable)7389 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable)
7390 {
7391 printf("[%s] not support!!\n",__FUNCTION__);
7392 return FALSE;
7393 }
7394
HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng,MS_U16 u16CaPvrMode,MS_BOOL bEnable)7395 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable)
7396 {
7397 MS_U16 u16value = REG16_R(&_RegCtrl3->CFG3_38);
7398
7399 switch(u32Eng)
7400 {
7401 case 0:
7402 u16value &= ~(HW4_CFG38_CA_PVR1_SEL_MASK|HW4_CFG38_PKT192_SPS_EN1);
7403 break;
7404 case 1:
7405 u16value &= ~(HW4_CFG38_CA_PVR2_SEL_MASK|HW4_CFG38_PKT192_SPS_EN2);
7406 break;
7407 case 2:
7408 u16value &= ~(HW4_CFG38_CA_PVR3_SEL_MASK|HW4_CFG38_PKT192_SPS_EN3);
7409 break;
7410 case 3:
7411 u16value &= ~(HW4_CFG38_CA_PVR4_SEL_MASK|HW4_CFG38_PKT192_SPS_EN4);
7412 break;
7413 default:
7414 return FALSE;
7415 }
7416
7417 if(bEnable)
7418 {
7419 switch(u32Eng)
7420 {
7421 case 0:
7422 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR1_SEL_SHIFT);
7423 u16value |= HW4_CFG38_PKT192_SPS_EN1;
7424 break;
7425 case 1:
7426 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR2_SEL_SHIFT);
7427 u16value |= HW4_CFG38_PKT192_SPS_EN2;
7428 break;
7429 case 2:
7430 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR3_SEL_SHIFT);
7431 u16value |= HW4_CFG38_PKT192_SPS_EN3;
7432 break;
7433 case 3:
7434 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR4_SEL_SHIFT);
7435 u16value |= HW4_CFG38_PKT192_SPS_EN4;
7436 break;
7437 }
7438 }
7439
7440 REG16_W(&_RegCtrl3->CFG3_38, u16value);
7441
7442 return TRUE;
7443
7444 }
7445
7446 //@TODO
7447 #if 1
HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng,MS_BOOL CTR_mode)7448 void HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng, MS_BOOL CTR_mode)
7449 {
7450 switch(u32Eng)
7451 {
7452 case 0: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN1);
7453 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR1_KEY);
7454 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
7455 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
7456 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
7457 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
7458 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
7459 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
7460 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
7461 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
7462 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY1);
7463 break;
7464 case 1: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN2);
7465 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR2_KEY);
7466 /*
7467 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x2222);//PVR SPS key
7468 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x2222);
7469 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x2222);
7470 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x2222);
7471 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x3333);
7472 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x3333);
7473 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x3333);
7474 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x3333);
7475 */
7476 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
7477 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
7478 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
7479 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
7480 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
7481 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
7482 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
7483 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
7484 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY2);
7485 break;
7486 case 2: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN3);
7487 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR3_KEY);
7488 /*
7489 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x4444);//PVR SPS key
7490 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x4444);
7491 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x4444);
7492 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x4444);
7493 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x5555);
7494 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x5555);
7495 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x5555);
7496 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x5555);
7497 */
7498 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
7499 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
7500 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
7501 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
7502 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
7503 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
7504 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
7505 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
7506 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY3);
7507 break;
7508 case 3: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN4);
7509 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR4_KEY);
7510 /*
7511 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x6666);//PVR SPS key
7512 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x6666);
7513 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x6666);
7514 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x6666);
7515 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x7777);
7516 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x7777);
7517 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x7777);
7518 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x7777);
7519 */
7520 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
7521 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
7522 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
7523 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
7524 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
7525 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
7526 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
7527 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
7528 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY4);
7529 break;
7530 default: printf("Not Support !!\n");
7531 break;
7532 }
7533
7534 if(CTR_mode == TRUE)
7535 {
7536 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05));
7537 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode
7538 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV
7539 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000);
7540 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000);
7541 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000);
7542 REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld
7543 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV
7544 }
7545 }
7546 #endif
7547
7548 // u32GroupId: 0 -> filter0 ~ filter31
7549 // u32GroupId: 1 -> filter32 ~ filter63
7550 // u32GroupId: 2 -> filter64 ~ filter95
7551 // u32GroupId: 3 -> filter96 ~ filter127
7552 // u32GroupId: 4 -> filter128 ~ filter159
7553 // u32GroupId: 5 -> filter160 ~ filter191
7554
7555
HAL_DSCMB_GetStatus(MS_U32 u32PktDmx,MS_U32 u32GroupId,MS_U32 u32PidFltId,MS_U32 * pu32ScmbSts)7556 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts)
7557 {
7558 MS_U16 u16PktDmxSrc;
7559 MS_U16 u16WordId;
7560 MS_U32 u32PIDFltMask = u32PidFltId;
7561
7562 if(u32PidFltId != 0xFFFFFFFF)
7563 {
7564 u32PIDFltMask = (1 << (u32PidFltId & 0x1F));
7565 }
7566
7567 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK);
7568
7569 switch(u32PktDmx)
7570 {
7571 case 0:
7572 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX0 << TSP_MATCH_PID_SRC_SHIFT);
7573 break;
7574 case 1:
7575 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX1 << TSP_MATCH_PID_SRC_SHIFT);
7576 break;
7577 case 2:
7578 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX2 << TSP_MATCH_PID_SRC_SHIFT);
7579 break;
7580 case 3:
7581 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX3 << TSP_MATCH_PID_SRC_SHIFT);
7582 break;
7583 default:
7584 break;
7585 }
7586
7587 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc);
7588
7589 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to load match_pid_num
7590
7591 // get status
7592 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze
7593
7594 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK);
7595
7596 if (u32GroupId < 6)
7597 {
7598 u16WordId = _SET_(u16WordId, u32GroupId << TSP_MATCH_PID_SEL_SHIFT);
7599 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK,u16WordId);
7600 }
7601 else
7602 {
7603 printf("[TSP_ERR][%s][%d] Unsupported u32GroupId (%lu)!!!\n",__FUNCTION__, __LINE__, (long unsigned int)u32GroupId);
7604 }
7605
7606 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask);
7607
7608 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable
7609
7610 if(u32PIDFltMask != 0xFFFFFFFF)
7611 {
7612 *pu32ScmbSts = ((*pu32ScmbSts > 0) ? 1: 0);
7613 }
7614
7615 return TRUE;
7616 }
7617
7618 // -------------------------------------------------------------
7619 // Merge Stream
7620 // -------------------------------------------------------------
HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path,MS_U8 u8Idx,MS_U8 * pu8SyncByte,MS_BOOL bSet)7621 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet)
7622 {
7623 REG16 *SynReg=0;
7624 MS_U16 u16Mask = 0x00FF, u16Sync = 0, u16Shift = 0;
7625
7626 switch(u8Path)
7627 {
7628 case TSP_TSIF0:
7629 SynReg = &(_RegCtrl6->SyncByte_tsif0[u8Idx>>1]);
7630 break;
7631 case TSP_TSIF1:
7632 SynReg = &(_RegCtrl6->SyncByte_tsif1[u8Idx>>1]);
7633 break;
7634 case TSP_TSIF2:
7635 SynReg = &(_RegCtrl6->SyncByte_tsif2[u8Idx>>1]);
7636 break;
7637 case TSP_TSIF3:
7638 SynReg = &(_RegCtrl6->SyncByte_tsif3[u8Idx>>1]);
7639 break;
7640 default:
7641 return FALSE;
7642 }
7643
7644
7645 if(u8Idx & 0x1)
7646 {
7647 u16Shift = 8;
7648 }
7649
7650 if(bSet == TRUE)
7651 {
7652 u16Sync = (MS_U16)(*pu8SyncByte & 0xFF);
7653 REG16_W(SynReg,((REG16_R(SynReg) & ~(u16Mask << u16Shift)) | (u16Sync << u16Shift)));
7654 }
7655 else
7656 {
7657 u16Sync = (REG16_R(SynReg) & (u16Mask << u16Shift)) >> u16Shift;
7658 *pu8SyncByte = (MS_U8)u16Sync;
7659 }
7660
7661 return TRUE;
7662
7663 }
7664
HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path,MS_U8 u8Idx,MS_U8 * pu8SrcId,MS_BOOL bSet)7665 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet)
7666 {
7667 REG16 *SrcIdReg =0;
7668 MS_U16 u16SrcId = 0, u16Mask = 0x000F, u16Shift = 0;
7669
7670 switch(u8Path)
7671 {
7672 case TSP_TSIF0:
7673 SrcIdReg = &(_RegCtrl6->SourceId_tsif0[u8Idx>>2]);
7674 break;
7675 case TSP_TSIF1:
7676 SrcIdReg = &(_RegCtrl6->SourceId_tsif1[u8Idx>>2]);
7677 break;
7678 case TSP_TSIF2:
7679 SrcIdReg = &(_RegCtrl6->SourceId_tsif2[u8Idx>>2]);
7680 break;
7681 case TSP_TSIF3:
7682 SrcIdReg = &(_RegCtrl6->SourceId_tsif3[u8Idx>>2]);
7683 break;
7684 default:
7685 return FALSE;
7686 }
7687
7688 switch(u8Idx & 0x3)
7689 {
7690 case 0x1:
7691 u16Shift = 4;
7692 break;
7693 case 0x2:
7694 u16Shift = 8;
7695 break;
7696 case 0x3:
7697 u16Shift = 12;
7698 break;
7699 }
7700
7701 if(bSet == TRUE)
7702 {
7703 u16SrcId = (MS_U16)(*pu8SrcId & 0xFF);
7704 REG16_W(SrcIdReg,((REG16_R(SrcIdReg) & ~(u16Mask << u16Shift)) | (u16SrcId << u16Shift)));
7705 }
7706 else
7707 {
7708 u16SrcId = (REG16_R(SrcIdReg) & (u16Mask << u16Shift)) >> u16Shift;
7709 *pu8SrcId = (MS_U8)u16SrcId;
7710 }
7711
7712 return TRUE;
7713 }
7714
HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path,MS_U8 u8PktHeaderLen)7715 static void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen)
7716 {
7717 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7718
7719 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_MXL_PKT_HEADER_MASK)) | ((u8PktHeaderLen << TSP_MXL_PKT_HEADER_SHIFT) & TSP_MXL_PKT_HEADER_MASK)));
7720 }
7721
HAL_TSP_PktConverter_PktMode(MS_U8 u8Path,TSP_HAL_PKT_MODE ePktMode)7722 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode)
7723 {
7724 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7725
7726 switch(ePktMode)
7727 {
7728 case E_TSP_HAL_PKT_MODE_NORMAL:
7729 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_188Mode));
7730 break;
7731 case E_TSP_HAL_PKT_MODE_CI:
7732 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_CIMode));
7733 break;
7734 case E_TSP_HAL_PKT_MODE_OPEN_CABLE:
7735 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_OpenCableMode));
7736 break;
7737 case E_TSP_HAL_PKT_MODE_ATS:
7738 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_ATSMode));
7739 break;
7740 case E_TSP_HAL_PKT_MODE_MXL_192:
7741 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7742 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,4);
7743 break;
7744 case E_TSP_HAL_PKT_MODE_MXL_196:
7745 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7746 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,8);
7747 break;
7748 case E_TSP_HAL_PKT_MODE_MXL_200:
7749 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7750 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,12);
7751 break;
7752 case E_TSP_HAL_PKT_MODE_ND:
7753 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_NagraDongleMode));
7754 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,1);
7755 break;
7756 default:
7757 printf("[TSP_ERR][%s][%d] Wrong PktConverter Packet Mode!!!\n",__FUNCTION__,__LINE__);
7758 return FALSE;
7759 }
7760
7761 return TRUE;
7762 }
7763
HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path,MS_BOOL bEnable)7764 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable)
7765 {
7766 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7767
7768 if(bEnable)
7769 {
7770 REG16_W(PktConverterReg, _SET_(REG16_R(PktConverterReg), TSP_PKT_FORCE_SYNC_47)); // Set 1 to force sync byte be 0x47
7771 }
7772 else
7773 {
7774 REG16_W(PktConverterReg, _CLR_(REG16_R(PktConverterReg), TSP_PKT_FORCE_SYNC_47));
7775 }
7776 }
7777
HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path,MS_BOOL bEnable)7778 void HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path, MS_BOOL bEnable)
7779 {
7780 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7781
7782 if(bEnable)
7783 {
7784 REG16_W(PktConverterReg, _SET_(REG16_R(PktConverterReg), TSP_SRC_ID_FLT_EN)); // Set 1 to enable filter sync byte and path ID match
7785 }
7786 else
7787 {
7788 REG16_W(PktConverterReg, _CLR_(REG16_R(PktConverterReg), TSP_SRC_ID_FLT_EN));
7789 }
7790 }
7791
HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId,MS_U32 u32SrcId)7792 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId)
7793 {
7794 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
7795 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcId << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
7796 }
7797
HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)7798 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)
7799 {
7800 MS_U8 u8Id;
7801 MS_U8 u8SyncByte;
7802
7803 u8SyncByte = 0x47;
7804 for(u8Id = 0; u8Id < TSP_MERGESTREAM_NUM; u8Id++,u8SyncByte++)
7805 {
7806 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Id, &u8SyncByte, TRUE);
7807 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Id, &u8Id, TRUE);
7808 }
7809 HAL_TSP_PktConverter_PktMode(u8Path,E_TSP_HAL_PKT_MODE_NORMAL);
7810 }
7811
7812 //-------------------------------------------------------------------------------------------------
7813 // For Debug Table
7814 //-------------------------------------------------------------------------------------------------
7815
HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)7816 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)
7817 {
7818 switch (eFlow)
7819 {
7820 case E_TSP_HAL_FLOW_LIVE0:
7821 return E_TSP_SRC_PKTDMX0;
7822 case E_TSP_HAL_FLOW_LIVE1:
7823 return E_TSP_SRC_PKTDMX2;
7824 case E_TSP_HAL_FLOW_LIVE2:
7825 return E_TSP_SRC_PKTDMX3;
7826 case E_TSP_HAL_FLOW_LIVE3:
7827 return E_TSP_SRC_PKTDMX1;
7828 case E_TSP_HAL_FLOW_FILE0:
7829 return E_TSP_SRC_PKTDMX1;
7830 case E_TSP_HAL_FLOW_FILE1:
7831 return E_TSP_SRC_PKTDMX3;
7832 case E_TSP_HAL_FLOW_FILE2:
7833 return E_TSP_SRC_PKTDMX0;
7834 case E_TSP_HAL_FLOW_FILE3:
7835 return E_TSP_SRC_PKTDMX2;
7836 case E_TSP_HAL_FLOW_MMFI0:
7837 return E_TSP_SRC_MMFI0;
7838 case E_TSP_HAL_FLOW_MMFI1:
7839 return E_TSP_SRC_MMFI1;
7840 default:
7841 printf("[TSP_ERR][%s][%d] UnSupported Debug Flow : %d !!!\n",__FUNCTION__, __LINE__,eFlow);
7842 return E_TSP_SRC_INVALID;
7843 }
7844 }
7845
HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)7846 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)
7847 {
7848 MS_U16 u16TSIF = 0;;
7849
7850 switch(u32TsIf)
7851 {
7852 case 0:
7853 u16TSIF = TSIF_SRC_SEL_TSIF0;
7854 break;
7855 case 1:
7856 u16TSIF = TSIF_SRC_SEL_TSIF1;
7857 break;
7858 case 2:
7859 u16TSIF = TSIF_SRC_SEL_TSIF2;
7860 break;
7861 case 3:
7862 u16TSIF = TSIF_SRC_SEL_TSIF3;
7863 break;
7864 default:
7865 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7866 break;
7867 }
7868
7869 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_TSIF_SRC_SEL_MASK,(u16TSIF << CFG5_7F_TSIF_SRC_SEL_SHIFT));
7870 }
7871
HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)7872 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
7873 {
7874 if(bEn == TRUE)
7875 {
7876 switch(u32TsIf)
7877 {
7878 case 0:
7879 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD);
7880 break;
7881 case 1:
7882 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD);
7883 break;
7884 case 2:
7885 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD);
7886 break;
7887 case 3:
7888 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_3_LOAD);
7889 break;
7890 default:
7891 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7892 break;
7893 }
7894 }
7895 else
7896 {
7897 switch(u32TsIf)
7898 {
7899 case 0:
7900 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD);
7901 break;
7902 case 1:
7903 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD);
7904 break;
7905 case 2:
7906 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD);
7907 break;
7908 case 3:
7909 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_3_LOAD);
7910 break;
7911 default:
7912 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7913 break;
7914 }
7915 }
7916
7917 }
7918
HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf,MS_BOOL bLock)7919 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock)
7920 {
7921 if(bLock) // 188 mode
7922 {
7923 REG16_CLR(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE);
7924 }
7925 else // Non 188 mode
7926 {
7927 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE);
7928 }
7929
7930 return REG16_R(&_RegCtrl5->Locked_PKT_Cnt);
7931 }
7932
HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif)7933 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif)
7934 {
7935 switch (u32Tsif)
7936 {
7937 case 0 :
7938 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR);
7939 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR);
7940 break;
7941 case 1:
7942 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR);
7943 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR);
7944 break;
7945 case 2:
7946 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR);
7947 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR);
7948 break;
7949 case 3:
7950 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_3_CLR);
7951 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_3_CLR);
7952 break;
7953 default :
7954 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
7955 break;
7956 }
7957 }
7958
HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)7959 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)
7960 {
7961 switch (eClrSrc)
7962 {
7963 case E_TSP_SRC_PKTDMX0:
7964 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX0 << CFG5_7F_CLR_SRC_SHIFT);
7965 break;
7966 case E_TSP_SRC_PKTDMX1:
7967 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX1 << CFG5_7F_CLR_SRC_SHIFT);
7968 break;
7969 case E_TSP_SRC_PKTDMX2:
7970 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX2 << CFG5_7F_CLR_SRC_SHIFT);
7971 break;
7972 case E_TSP_SRC_PKTDMX3:
7973 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX3 << CFG5_7F_CLR_SRC_SHIFT);
7974 break;
7975 case E_TSP_SRC_MMFI0:
7976 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_MMFI0 << CFG5_7F_CLR_SRC_SHIFT);
7977 break;
7978 case E_TSP_SRC_MMFI1:
7979 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_MMFI1 << CFG5_7F_CLR_SRC_SHIFT);
7980 break;
7981 default:
7982 printf("[%s][%s][%d] UnSupported Clear Source : %d !\n",__FILE__,__FUNCTION__,__LINE__,eClrSrc);
7983 break;
7984 }
7985 }
7986
HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)7987 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId)
7988 {
7989 MS_U16 u16AvSrc = 0;
7990
7991 switch(ePktDmxId)
7992 {
7993 case E_TSP_SRC_PKTDMX0:
7994 u16AvSrc = AV_PKT_SRC_PKTDMX0;
7995 break;
7996 case E_TSP_SRC_PKTDMX1:
7997 u16AvSrc = AV_PKT_SRC_PKTDMX1;
7998 break;
7999 case E_TSP_SRC_PKTDMX2:
8000 u16AvSrc = AV_PKT_SRC_PKTDMX2;
8001 break;
8002 case E_TSP_SRC_PKTDMX3:
8003 u16AvSrc = AV_PKT_SRC_PKTDMX3;
8004 break;
8005 case E_TSP_SRC_MMFI0:
8006 u16AvSrc = AV_PKT_SRC_MMFI0;
8007 break;
8008 case E_TSP_SRC_MMFI1:
8009 u16AvSrc = AV_PKT_SRC_MMFI1;
8010 break;
8011 default:
8012 printf("[%s][%s][%d] UnSupported AV Source : %d!\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
8013 break;
8014 }
8015
8016 switch (eAvType)
8017 {
8018 case E_TSP_DST_FIFO_VIDEO :
8019 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_SRC_MASK, u16AvSrc << CFG5_7E_VID_SRC_SHIFT);
8020 break;
8021 case E_TSP_DST_FIFO_VIDEO3D :
8022 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_3D_SRC_MASK, u16AvSrc << CFG5_7E_VID_3D_SRC_SHIFT);
8023 break;
8024 case E_TSP_DST_FIFO_VIDEO3 :
8025 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_3_SRC_MASK, u16AvSrc << CFG5_7E_VID_3_SRC_SHIFT);
8026 break;
8027 case E_TSP_DST_FIFO_VIDEO4 :
8028 REG16_MSK_W(&_RegCtrl5->CFG5_78, CFG5_78_VID_4_SRC_MASK, u16AvSrc << CFG5_78_VID_4_SRC_SHIFT);
8029 break;
8030 case E_TSP_DST_FIFO_AUDIO :
8031 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_AUDA_SRC_MASK, u16AvSrc << CFG5_7E_AUDA_SRC_SHIFT);
8032 break;
8033 case E_TSP_DST_FIFO_AUDIO2 :
8034 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_AUDB_SRC_MASK, u16AvSrc << CFG5_7E_AUDB_SRC_SHIFT);
8035 break;
8036 case E_TSP_DST_FIFO_AUDIO3 :
8037 REG16_MSK_W(&_RegCtrl5->CFG5_78, CFG5_78_AUDC_SRC_MASK, u16AvSrc << CFG5_78_AUDC_SRC_SHIFT);
8038 break;
8039 case E_TSP_DST_FIFO_AUDIO4 :
8040 REG16_MSK_W(&_RegCtrl5->CFG5_78, CFG5_78_AUDD_SRC_MASK, u16AvSrc << CFG5_78_AUDD_SRC_SHIFT);
8041 break;
8042 default:
8043 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8044 break;
8045 }
8046 }
8047
HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)8048 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn)
8049 {
8050 if(bEn == TRUE)
8051 {
8052 switch (eAvType)
8053 {
8054 case E_TSP_DST_FIFO_VIDEO :
8055 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD);
8056 break;
8057 case E_TSP_DST_FIFO_VIDEO3D :
8058 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD);
8059 break;
8060 case E_TSP_DST_FIFO_VIDEO3 :
8061 REG16_SET(&_RegCtrl5->CFG5_74,CFG5_74_V3_PKT_CNT_LOAD);
8062 break;
8063 case E_TSP_DST_FIFO_VIDEO4 :
8064 REG16_SET(&_RegCtrl5->CFG5_75,CFG5_75_V4_PKT_CNT_LOAD);
8065 break;
8066 case E_TSP_DST_FIFO_AUDIO :
8067 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD);
8068 break;
8069 case E_TSP_DST_FIFO_AUDIO2 :
8070 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD);
8071 break;
8072 case E_TSP_DST_FIFO_AUDIO3 :
8073 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_ADC_PKT_CNT_LOAD);
8074 break;
8075 case E_TSP_DST_FIFO_AUDIO4 :
8076 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_ADD_PKT_CNT_LOAD);
8077 break;
8078 default :
8079 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8080 break;
8081 }
8082 }
8083 else
8084 {
8085 switch (eAvType)
8086 {
8087 case E_TSP_DST_FIFO_VIDEO :
8088 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD);
8089 break;
8090 case E_TSP_DST_FIFO_VIDEO3D :
8091 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD);
8092 break;
8093 case E_TSP_DST_FIFO_VIDEO3 :
8094 REG16_CLR(&_RegCtrl5->CFG5_74,CFG5_74_V3_PKT_CNT_LOAD);
8095 break;
8096 case E_TSP_DST_FIFO_VIDEO4 :
8097 REG16_CLR(&_RegCtrl5->CFG5_75,CFG5_75_V4_PKT_CNT_LOAD);
8098 break;
8099 case E_TSP_DST_FIFO_AUDIO :
8100 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD);
8101 break;
8102 case E_TSP_DST_FIFO_AUDIO2 :
8103 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD);
8104 break;
8105 case E_TSP_DST_FIFO_AUDIO3 :
8106 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_ADC_PKT_CNT_LOAD);
8107 break;
8108 case E_TSP_DST_FIFO_AUDIO4 :
8109 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_ADD_PKT_CNT_LOAD);
8110 break;
8111 default :
8112 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8113 break;
8114 }
8115 }
8116 }
8117
HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)8118 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)
8119 {
8120 switch (eAvType)
8121 {
8122 case E_TSP_DST_FIFO_VIDEO :
8123 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
8124 return REG16_R(&_RegCtrl5->Av_PKT_Cnt);
8125 case E_TSP_DST_FIFO_VIDEO3D:
8126 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
8127 return REG16_R(&_RegCtrl5->Av_PKT_Cnt1);
8128 case E_TSP_DST_FIFO_VIDEO3 :
8129 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
8130 return REG16_R(&_RegCtrl5->Av_PKT_Cnt2);
8131 case E_TSP_DST_FIFO_VIDEO4:
8132 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
8133 return REG16_R(&_RegCtrl5->Av_PKT_Cnt2);
8134 case E_TSP_DST_FIFO_AUDIO :
8135 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
8136 return REG16_R(&_RegCtrl5->Av_PKT_Cnt);
8137 case E_TSP_DST_FIFO_AUDIO2 :
8138 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
8139 return REG16_R(&_RegCtrl5->Av_PKT_Cnt1);
8140 default :
8141 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8142 return 0;
8143 }
8144 }
8145
HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)8146 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)
8147 {
8148 switch (eAvType)
8149 {
8150 case E_TSP_DST_FIFO_VIDEO :
8151 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR);
8152 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR);
8153 break;
8154 case E_TSP_DST_FIFO_VIDEO3D :
8155 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR);
8156 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR);
8157 break;
8158 case E_TSP_DST_FIFO_VIDEO3 :
8159 REG16_SET(&_RegCtrl5->CFG5_74,CFG5_74_V3_PKT_CNT_CLR);
8160 REG16_CLR(&_RegCtrl5->CFG5_74,CFG5_74_V3_PKT_CNT_CLR);
8161 break;
8162 case E_TSP_DST_FIFO_VIDEO4 :
8163 REG16_SET(&_RegCtrl5->CFG5_75,CFG5_75_V4_PKT_CNT_CLR);
8164 REG16_CLR(&_RegCtrl5->CFG5_75,CFG5_75_V4_PKT_CNT_CLR);
8165 break;
8166 case E_TSP_DST_FIFO_AUDIO :
8167 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR);
8168 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR);
8169 break;
8170 case E_TSP_DST_FIFO_AUDIO2 :
8171 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR);
8172 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR);
8173 break;
8174 case E_TSP_DST_FIFO_AUDIO3 :
8175 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_ADC_PKT_CNT_CLR);
8176 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_ADC_PKT_CNT_CLR);
8177 break;
8178 case E_TSP_DST_FIFO_AUDIO4 :
8179 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_ADD_PKT_CNT_CLR);
8180 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_ADD_PKT_CNT_CLR);
8181 break;
8182 default :
8183 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8184 break;
8185 }
8186 }
8187
HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)8188 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)
8189 {
8190 MS_U16 u16AvType = 0;
8191
8192 switch(eAvType)
8193 {
8194 case E_TSP_DST_FIFO_VIDEO:
8195 u16AvType = DIS_DROP_CNT_V;
8196 break;
8197 case E_TSP_DST_FIFO_VIDEO3D:
8198 u16AvType = DIS_DROP_CNT_V3D;
8199 break;
8200 case E_TSP_DST_FIFO_VIDEO3:
8201 u16AvType = DIS_DROP_CNT_V3;
8202 break;
8203 case E_TSP_DST_FIFO_VIDEO4:
8204 u16AvType = DIS_DROP_CNT_V4;
8205 break;
8206 case E_TSP_DST_FIFO_AUDIO:
8207 u16AvType = DIS_DROP_CNT_A;
8208 break;
8209 case E_TSP_DST_FIFO_AUDIO2:
8210 u16AvType = DIS_DROP_CNT_AD;
8211 break;
8212 case E_TSP_DST_FIFO_AUDIO3:
8213 u16AvType = DIS_DROP_CNT_ADC;
8214 break;
8215 case E_TSP_DST_FIFO_AUDIO4:
8216 u16AvType = DIS_DROP_CNT_ADD;
8217 break;
8218 default:
8219 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8220 break;
8221 }
8222
8223 switch(ePktDmxId)
8224 {
8225 case E_TSP_SRC_PKTDMX0:
8226 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_PIDFLT_SRC_SEL_MASK,(u16AvType<<CFG5_7F_PIDFLT_SRC_SEL_SHIFT));
8227 break;
8228 case E_TSP_SRC_PKTDMX1:
8229 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_PIDFLT_SRC_SEL1_MASK,(u16AvType<<CFG5_7F_PIDFLT_SRC_SEL1_SHIFT));
8230 break;
8231 case E_TSP_SRC_PKTDMX2:
8232 REG16_MSK_W(&_RegCtrl5->CFG5_77,CFG5_77_PIDFLT_SRC_SEL2_MASK,(u16AvType<<CFG5_77_PIDFLT_SRC_SEL2_SHIFT));
8233 break;
8234 case E_TSP_SRC_PKTDMX3:
8235 REG16_MSK_W(&_RegCtrl5->CFG5_77,CFG5_77_PIDFLT_SRC_SEL3_MASK,(u16AvType<<CFG5_77_PIDFLT_SRC_SEL3_SHIFT));
8236 break;
8237 case E_TSP_SRC_MMFI0:
8238 REG16_MSK_W(&_RegCtrl5->CFG5_78,CFG5_78_PIDFLT_SRC_SEL_MMFI0_MASK,(u16AvType<<CFG5_78_PIDFLT_SRC_SEL_MMFI0_SHIFT));
8239 break;
8240 case E_TSP_SRC_MMFI1:
8241 REG16_MSK_W(&_RegCtrl5->CFG5_78,CFG5_78_PIDFLT_SRC_SEL_MMFI1_MASK,(u16AvType<<CFG5_78_PIDFLT_SRC_SEL_MMFI1_SHIFT));
8242 break;
8243 default:
8244 printf("[%s][%s][%d] UnSupported AV FIFO Source : %d !\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
8245 break;
8246 }
8247 }
8248
HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)8249 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)
8250 {
8251 if(bEn == TRUE)
8252 {
8253 switch (eAvType)
8254 {
8255 case E_TSP_DST_FIFO_VIDEO :
8256 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD);
8257 break;
8258 case E_TSP_DST_FIFO_VIDEO3D :
8259 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD);
8260 break;
8261 case E_TSP_DST_FIFO_VIDEO3 :
8262 REG16_SET(&_RegCtrl5->CFG5_74,CFG5_74_DROP_PKT_CNT_V3_LOAD);
8263 break;
8264 case E_TSP_DST_FIFO_VIDEO4 :
8265 REG16_SET(&_RegCtrl5->CFG5_75,CFG5_75_DROP_PKT_CNT_V4_LOAD);
8266 break;
8267 case E_TSP_DST_FIFO_AUDIO :
8268 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD);
8269 break;
8270 case E_TSP_DST_FIFO_AUDIO2 :
8271 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD);
8272 break;
8273 case E_TSP_DST_FIFO_AUDIO3 :
8274 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADC_LOAD);
8275 break;
8276 case E_TSP_DST_FIFO_AUDIO4 :
8277 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADD_LOAD);
8278 break;
8279 default :
8280 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8281 break;
8282 }
8283 }
8284 else
8285 {
8286 switch (eAvType)
8287 {
8288 case E_TSP_DST_FIFO_VIDEO :
8289 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD);
8290 break;
8291 case E_TSP_DST_FIFO_VIDEO3D :
8292 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD);
8293 break;
8294 case E_TSP_DST_FIFO_VIDEO3 :
8295 REG16_CLR(&_RegCtrl5->CFG5_74,CFG5_74_DROP_PKT_CNT_V3_LOAD);
8296 break;
8297 case E_TSP_DST_FIFO_VIDEO4 :
8298 REG16_CLR(&_RegCtrl5->CFG5_75,CFG5_75_DROP_PKT_CNT_V4_LOAD);
8299 break;
8300 case E_TSP_DST_FIFO_AUDIO :
8301 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD);
8302 break;
8303 case E_TSP_DST_FIFO_AUDIO2 :
8304 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD);
8305 break;
8306 case E_TSP_DST_FIFO_AUDIO3 :
8307 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADC_LOAD);
8308 break;
8309 case E_TSP_DST_FIFO_AUDIO4 :
8310 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADD_LOAD);
8311 break;
8312 default :
8313 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8314 break;
8315 }
8316 }
8317 }
8318
HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)8319 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)
8320 {
8321 if(bPayload)
8322 {
8323 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL);
8324 }
8325 else
8326 {
8327 REG16_CLR(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL);
8328 }
8329
8330 if(bEn == TRUE)
8331 {
8332 switch (eAvType)
8333 {
8334 case E_TSP_DST_FIFO_VIDEO :
8335 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD);
8336 break;
8337 case E_TSP_DST_FIFO_VIDEO3D :
8338 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V3D_LOAD);
8339 break;
8340 case E_TSP_DST_FIFO_VIDEO3 :
8341 REG16_SET(&_RegCtrl5->CFG5_74,CFG5_74_DIS_PKT_CNT_V3_LOAD);
8342 break;
8343 case E_TSP_DST_FIFO_VIDEO4 :
8344 REG16_SET(&_RegCtrl5->CFG5_75,CFG5_75_DIS_PKT_CNT_V4_LOAD);
8345 break;
8346 case E_TSP_DST_FIFO_AUDIO :
8347 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD);
8348 break;
8349 case E_TSP_DST_FIFO_AUDIO2 :
8350 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD);
8351 break;
8352 case E_TSP_DST_FIFO_AUDIO3 :
8353 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADC_LOAD);
8354 break;
8355 case E_TSP_DST_FIFO_AUDIO4 :
8356 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADD_LOAD);
8357 break;
8358 default :
8359 printf("[%s][%s][%d] UnSupported AV Type : %d \n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8360 break;
8361 }
8362 }
8363 else
8364 {
8365 switch (eAvType)
8366 {
8367 case E_TSP_DST_FIFO_VIDEO :
8368 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD);
8369 break;
8370 case E_TSP_DST_FIFO_VIDEO3D :
8371 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V3D_LOAD);
8372 break;
8373 case E_TSP_DST_FIFO_VIDEO3 :
8374 REG16_CLR(&_RegCtrl5->CFG5_74,CFG5_74_DIS_PKT_CNT_V3_LOAD);
8375 break;
8376 case E_TSP_DST_FIFO_VIDEO4 :
8377 REG16_CLR(&_RegCtrl5->CFG5_75,CFG5_75_DIS_PKT_CNT_V4_LOAD);
8378 break;
8379 case E_TSP_DST_FIFO_AUDIO :
8380 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD);
8381 break;
8382 case E_TSP_DST_FIFO_AUDIO2 :
8383 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD);
8384 break;
8385 case E_TSP_DST_FIFO_AUDIO3 :
8386 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADC_LOAD);
8387 break;
8388 case E_TSP_DST_FIFO_AUDIO4 :
8389 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADD_LOAD);
8390 break;
8391 default :
8392 printf("[%s][%s][%d] UnSupported AV Type : %d \n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8393 break;
8394 }
8395 }
8396 }
8397
HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId,MS_BOOL bDrop)8398 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop)
8399 {
8400 if(bDrop)
8401 {
8402 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE);
8403 }
8404 else
8405 {
8406 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE);
8407 }
8408
8409 switch (ePktDmxId)
8410 {
8411 case E_TSP_SRC_PKTDMX0:
8412 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_0);
8413 case E_TSP_SRC_PKTDMX1:
8414 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_1);
8415 case E_TSP_SRC_PKTDMX2:
8416 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_2);
8417 case E_TSP_SRC_PKTDMX3:
8418 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_3);
8419 case E_TSP_SRC_MMFI0:
8420 return REG16_R(&_RegCtrl5->CFG5_0B);
8421 case E_TSP_SRC_MMFI1:
8422 return REG16_R(&_RegCtrl5->CFG5_0C);
8423 default :
8424 printf("[%s][%s][%d] UnSupported AV FIFO Source : %d\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
8425 return 0;
8426 }
8427 }
8428
HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)8429 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)
8430 {
8431 switch (eAvType)
8432 {
8433 case E_TSP_DST_FIFO_VIDEO :
8434 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR);
8435 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR);
8436 break;
8437 case E_TSP_DST_FIFO_VIDEO3D :
8438 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR);
8439 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR);
8440 break;
8441 case E_TSP_DST_FIFO_VIDEO3:
8442 REG16_SET(&_RegCtrl5->CFG5_74,CFG5_74_DROP_PKT_CNT_V3_CLR);
8443 REG16_CLR(&_RegCtrl5->CFG5_74,CFG5_74_DROP_PKT_CNT_V3_CLR);
8444 break;
8445 case E_TSP_DST_FIFO_VIDEO4 :
8446 REG16_SET(&_RegCtrl5->CFG5_75,CFG5_75_DROP_PKT_CNT_V4_CLR);
8447 REG16_CLR(&_RegCtrl5->CFG5_75,CFG5_75_DROP_PKT_CNT_V4_CLR);
8448 break;
8449 case E_TSP_DST_FIFO_AUDIO :
8450 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR);
8451 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR);
8452 break;
8453 case E_TSP_DST_FIFO_AUDIO2 :
8454 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR);
8455 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR);
8456 break;
8457 case E_TSP_DST_FIFO_AUDIO3 :
8458 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADC_CLR);
8459 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADC_CLR);
8460 break;
8461 case E_TSP_DST_FIFO_AUDIO4 :
8462 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADD_CLR);
8463 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADD_CLR);
8464 break;
8465 default :
8466 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8467 break;
8468 }
8469 }
8470
HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)8471 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)
8472 {
8473 switch (eAvType)
8474 {
8475 case E_TSP_DST_FIFO_VIDEO :
8476 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
8477 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
8478 break;
8479 case E_TSP_DST_FIFO_VIDEO3D :
8480 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
8481 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
8482 break;
8483 case E_TSP_DST_FIFO_VIDEO3 :
8484 REG16_SET(&_RegCtrl5->CFG5_74,CFG5_74_DIS_PKT_CNT_V3_CLR);
8485 REG16_CLR(&_RegCtrl5->CFG5_74,CFG5_74_DIS_PKT_CNT_V3_CLR);
8486 break;
8487 case E_TSP_DST_FIFO_VIDEO4 :
8488 REG16_SET(&_RegCtrl5->CFG5_75,CFG5_75_DIS_PKT_CNT_V4_CLR);
8489 REG16_CLR(&_RegCtrl5->CFG5_75,CFG5_75_DIS_PKT_CNT_V4_CLR);
8490 break;
8491 case E_TSP_DST_FIFO_AUDIO :
8492 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
8493 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
8494 break;
8495 case E_TSP_DST_FIFO_AUDIO2 :
8496 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
8497 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
8498 break;
8499 case E_TSP_DST_FIFO_AUDIO3 :
8500 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
8501 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
8502 break;
8503 case E_TSP_DST_FIFO_AUDIO4 :
8504 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
8505 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
8506 break;
8507 default :
8508 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8509 break;
8510 }
8511 }
8512
HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)8513 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)
8514 {
8515 MS_U16 u16TSIF = 0;;
8516
8517 switch(u32TsIf)
8518 {
8519 case 0:
8520 u16TSIF = TSIF_SRC_SEL_TSIF0;
8521 break;
8522 case 1:
8523 u16TSIF = TSIF_SRC_SEL_TSIF1;
8524 break;
8525 case 2:
8526 u16TSIF = TSIF_SRC_SEL_TSIF2;
8527 break;
8528 case 3:
8529 u16TSIF = TSIF_SRC_SEL_TSIF3;
8530 break;
8531 default:
8532 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8533 break;
8534 }
8535
8536 REG16_MSK_W(&_RegCtrl5->CFG5_70,CFG5_70_ERR_PKT_SRC_SEL_MASK,(u16TSIF << CFG5_70_ERR_PKT_SRC_SEL_SHIFT));
8537 }
8538
HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)8539 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
8540 {
8541 if(bEn == TRUE)
8542 {
8543 switch(u32TsIf)
8544 {
8545 case 0:
8546 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD);
8547 break;
8548 case 1:
8549 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD);
8550 break;
8551 case 2:
8552 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD);
8553 break;
8554 case 3:
8555 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_3_LOAD);
8556 break;
8557 default:
8558 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8559 break;
8560 }
8561 }
8562 else
8563 {
8564 switch(u32TsIf)
8565 {
8566 case 0:
8567 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD);
8568 break;
8569 case 1:
8570 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD);
8571 break;
8572 case 2:
8573 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD);
8574 break;
8575 case 3:
8576 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_3_LOAD);
8577 break;
8578 default:
8579 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8580 break;
8581 }
8582 }
8583
8584 }
8585
HAL_TSP_Debug_ErrPktCnt_Get(void)8586 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void)
8587 {
8588 return REG16_R(&_RegCtrl5->Err_PKT_Cnt);
8589 }
8590
HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif)8591 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif)
8592 {
8593 switch (u32Tsif)
8594 {
8595 case 0 :
8596 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR);
8597 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR);
8598 break;
8599 case 1:
8600 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR);
8601 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR);
8602 break;
8603 case 2 :
8604 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR);
8605 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR);
8606 break;
8607 case 3 :
8608 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_3_CLR);
8609 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_3_CLR);
8610 break;
8611
8612 default :
8613 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
8614 break;
8615 }
8616 }
8617
HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)8618 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)
8619 {
8620 MS_U16 u16TSIF = 0;;
8621
8622 switch(u32TsIf)
8623 {
8624 case 0:
8625 u16TSIF = TSIF_SRC_SEL_TSIF0;
8626 break;
8627 case 1:
8628 u16TSIF = TSIF_SRC_SEL_TSIF1;
8629 break;
8630 case 2:
8631 u16TSIF = TSIF_SRC_SEL_TSIF2;
8632 break;
8633 case 3:
8634 u16TSIF = TSIF_SRC_SEL_TSIF3;
8635 break;
8636 default:
8637 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8638 break;
8639 }
8640
8641 REG16_MSK_W(&_RegCtrl5->CFG5_70,CFG5_70_INPUT_PKT_SRC_SEL_MASK,(u16TSIF << CFG5_70_INPUT_PKT_SRC_SEL_SHIT));
8642 }
8643
HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)8644 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
8645 {
8646 if(bEn == TRUE)
8647 {
8648 switch(u32TsIf)
8649 {
8650 case 0:
8651 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD);
8652 break;
8653 case 1:
8654 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD);
8655 break;
8656 case 2:
8657 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD);
8658 break;
8659 case 3:
8660 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_3_LOAD);
8661 break;
8662 default:
8663 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8664 break;
8665 }
8666 }
8667 else
8668 {
8669 switch(u32TsIf)
8670 {
8671 case 0:
8672 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD);
8673 break;
8674 case 1:
8675 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD);
8676 break;
8677 case 2:
8678 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD);
8679 break;
8680 case 3:
8681 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_3_LOAD);
8682 break;
8683 default:
8684 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8685 break;
8686 }
8687 }
8688 }
8689
HAL_TSP_Debug_InputPktCnt_Get(void)8690 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void)
8691 {
8692 return REG16_R(&_RegCtrl5->Input_PKT_Cnt);
8693 }
8694
HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)8695 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)
8696 {
8697 switch (u32Tsif)
8698 {
8699 case 0 :
8700 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR);
8701 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR);
8702 break;
8703 case 1:
8704 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR);
8705 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR);
8706 break;
8707 case 2 :
8708 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR);
8709 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR);
8710 break;
8711 case 3 :
8712 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_3_CLR);
8713 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_3_CLR);
8714 break;
8715
8716 default :
8717 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
8718 break;
8719 }
8720
8721 }
8722
HAL_TSP_Privilege_Enable(MS_BOOL bEnable)8723 void HAL_TSP_Privilege_Enable(MS_BOOL bEnable)
8724 {
8725 if (bEnable)
8726 {
8727 REG16_SET(&_RegCtrl3->CFG3_7C, CFG3_7C_PRIVILEGE_FLAG);
8728 }
8729 else
8730 {
8731 REG16_CLR(&_RegCtrl3->CFG3_7C, CFG3_7C_PRIVILEGE_FLAG);
8732 }
8733 }
8734
HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng,MS_U32 u32FQSrc)8735 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc)
8736 {
8737 // not support
8738 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_INFO, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupport feature!\n",__FILE__,__FUNCTION__,__LINE__));
8739 return FALSE;
8740 }
8741
HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)8742 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)
8743 {
8744 // not support
8745 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_INFO, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupport feature!\n",__FILE__,__FUNCTION__,__LINE__));
8746 return 0xFF;
8747 }
8748
HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng,MS_BOOL bFltNull)8749 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull)
8750 {
8751 if(bFltNull)
8752 {
8753 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_FILTER_NULL_PKT);
8754 }
8755 else
8756 {
8757 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_FILTER_NULL_PKT);
8758 }
8759
8760 return TRUE;
8761 }
8762
HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType,MS_U8 u8Eng,MS_PHY phyBufStart)8763 void HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType, MS_U8 u8Eng, MS_PHY phyBufStart)
8764 {
8765 MS_U8 u8MiuSel = 0;
8766 MS_PHY phyMiuOffsetFileinAddr = 0;
8767 MS_U8 u8Shift = u8Eng * TSP_MIU_SEL_BITS_LEN;
8768
8769 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinAddr, phyBufStart);
8770
8771 switch(eType)
8772 {
8773 case E_TSP_HAL_MIU_SEL_MMFI:
8774 REG16_MSK_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG_MIU_SEL_MMFI0_MASK << u8Shift), (u8MiuSel << (REG_MIU_SEL_MMFI0_SHIFT + u8Shift)));
8775 break;
8776 case E_TSP_HAL_MIU_SEL_FQ:
8777 REG16_MSK_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG_MIU_SEL_FIQ0_MASK << u8Shift), (u8MiuSel << (REG_MIU_SEL_FIQ0_SHIFT + u8Shift)));
8778 break;
8779 default:
8780 break;
8781 }
8782 }
8783