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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halTSP.c
97 // @brief Transport Stream Processer (TSP) HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "halTSP.h"
101 #include "halCHIP.h"
102
103 //--------------------------------------------------------------------------------------------------
104 // Driver Compiler Option
105 //--------------------------------------------------------------------------------------------------
106 #define TSP_HAL_REG_SAFE_MODE 1UL // Register protection access between 1 task and 1+ ISR
107
108 //[HWBUG]
109 #define MULTI_ACCESS_SW_PATCH 1UL // It's still risk becuase some registers like readaddr will
110
111 // @FIXME: remove the test later
112 #define LINUX_TEST 0UL
113 // cause overflow before patching to correct value.
114 #define MIU_BUS 4UL
115
116 #define VQ_PACKET_UNIT_LEN 192UL //192 bytes
117
118 //--------------------------------------------------------------------------------------------------
119 // TSP Hardware Abstraction Layer
120 //--------------------------------------------------------------------------------------------------
121 static REG_Ctrl* _TspCtrl = NULL; // TSP0 & TSP1
122 static REG_Ctrl2* _TspCtrl2 = NULL; // TSP2
123 static REG_Ctrl3* _TspCtrl3 = NULL; // TSP3
124
125 static MS_VIRT _virtRegBase = 0;
126
127 extern MS_BOOL _bIsHK;
128 static MS_S32 _s32HALTSPMutexId = -1;
129 static MS_BOOL _b64STCMode = FALSE;
130
131 static MS_PHY _phyOrLoadMiuOffset = 0;
132 static MS_PHY _phySecBufMiuOffset = 0;
133 static MS_PHY _phyFIBufMiuOffset = 0;
134 static MS_PHY _phyPVRBufMiuOffset[TSP_PVR_IF_NUM] = {[0 ... (TSP_PVR_IF_NUM-1)] = 0UL};
135
136 static MS_BOOL _bTsPadUsed[TSP_TS_PAD_NUM] = {FALSE};
137
138 //[NOTE] Jerry
139 // Some register has write order, for example, writing PCR_L will disable PCR counter
140 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
141 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFFUL); \
142 (reg)->H = ((value) >> 16UL); } while(0)
143
144 #define _HAL_REG32L_W(reg, value) (reg)->data = ((value) & 0x0000FFFFUL);
145
146 #define _HAL_REG16_W(reg, value) (reg)->u16data = (value);
147
148
149 #define _HAL_HALTSP_ENTRY() do{ \
150 if(_s32HALTSPMutexId == -1) \
151 _s32HALTSPMutexId = MsOS_CreateMutex(E_MSOS_FIFO, "HALTSP_Mutex", MSOS_PROCESS_SHARED); \
152 }while(0)
153 #define _HAL_HALTSP_EXIT() do{ \
154 if(_s32HALTSPMutexId != -1) \
155 { \
156 MsOS_DeleteMutex(_s32HALTSPMutexId); _s32HALTSPMutexId = -1; \
157 } \
158 }while(0)
159
160 #define _HAL_HALTSP_LOCK() (MsOS_ObtainMutex(_s32HALTSPMutexId, MSOS_WAIT_FOREVER))
161 #define _HAL_HALTSP_UNLOCK() (MsOS_ReleaseMutex(_s32HALTSPMutexId))
162
163 //--------------------------------------------------------------------------------------------------
164 // Macro of bit operations
165 //--------------------------------------------------------------------------------------------------
166 #define HAS_FLAG(flag, bit) ((flag) & (bit))
167 #define SET_FLAG(flag, bit) ((flag)|= (bit))
168 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
169 #define SET_FLAG1(flag, bit) ((flag)| (bit))
170 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
171
172 //#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT)
173 //#define BIT(x) (1<<(x))
174 //#define BMASK(bits) (BIT(((1)?bits)+1)-BIT(((0)?bits)))
175 // #define BMASK_L(bits) (BMASK(bits)&0xFFFF)
176 // #define BMASK_H(bits) (BMASK(bits)>>16)
177 //#define BITS(bits,value) ((BIT(((1)?bits)+1)-BIT(((0)?bits))) & (value<<((0)?bits)))
178
179 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
180
181 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
182 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL
183 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL
184 #define REG_CLKGEN0_STC_CW_EN 0x0004UL
185 #define REG_CLKGEN0_STC_REF_DIV2_EN 0x0008UL
186 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL
187 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL
188
189 #define REG_CLKGEN0_TSN_CLK 0x28UL
190 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL
191 #define REG_CLKGEN0_TSN_CLK_DEMOD 0x1CUL
192 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL
193 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL
194 //#define TSP_CLK_TS0 0
195 //#define TSP_CLK_INDEMOD 7
196 // bit[4:0] -> ts0 -> 0: disable clock
197 // 1: invert clock
198 // bit [4:2] -> 0: TS0
199 // 7: Internal Demmod
200 // bit[12:8] -> ts1 -> 0: disable clock
201 // 1: invert clock
202 // bit [4:2] -> 0: TS0
203 // 7: Internal Demmod
204 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
205 #define REG_TOP_TS0_PE 0x0EUL
206 #define REG_TOP_TS1_PE 0x06UL
207 #define REG_TOP_TS2_PE 0x36UL
208 #define REG_TOP_TS_PE_MASK 0x07FFUL
209
210 #define REG_TOP_TSN_MUX 0x11UL
211 #define REG_TOP_TSN_MUX_MASK 0x0FUL
212 #define REG_TOP_TSN_MUX_TS0_SHIFT 0UL
213 #define REG_TOP_TSN_MUX_TS1_SHIFT 8UL
214 // bit[3:0] -> ts0 -> 0: TS0
215 // 7: Demod
216 // bit[10:8] -> ts1 -> 0: TS0
217 // 7: Demod
218 #define REG_TOP_TSCONFIG 0x57UL
219 #define REG_TOP_TS_TS1_CFG_MASK 0x07UL
220 #define REG_TOP_TS1CFG_SHIFT 11UL
221 #define REG_TOP_TSCFG_DISABLE_PAD 0UL
222 #define REG_TOP_TS1_PARALLEL_IN 1UL
223 #define REG_TOP_TS1_SERIAL_IN 3UL
224
225 #define REG_TOP_TS_TS2_CFG_MASK 0x03UL
226 #define REG_TOP_TS2CFG_SHIFT 14UL
227 #define REG_TOP_TSCFG_DISABLE_PAD 0UL
228 #define REG_TOP_TS2_SERIAL_IN 1UL
229
230
231 // bit[10:8] -> 0: Disable
232 // 1: use all PAD_TS0 pads
233 // 2: e PAD_TS0_VLD, PAD_TS0_SYNC, PAD_TS0_CLK and PAD_TS0_D0 pads
234 // 3: mspi mode
235 // 4: 3 wire mode
236
237 #define ABS_DIFF(x1, x2) (((x1) > (x2))? ((x1) - (x2)) : ((x2) - (x1)))
238 #define IsCover(_start1, _end1, _start2, _end2) (ABS_DIFF(_end1, _end2) < (((_end1) > (_end2))?((_end1)-(_start1)):((_end2)-(_start2))) )?TRUE:FALSE
239 //--------------------------------------------------------------------------------------------------
240 // Forward declaration
241 //--------------------------------------------------------------------------------------------------
242 static void _HAL_TSP_FW_load(
243 MS_PHY phyFwAddrPhys,
244 MS_U32 u32FwSize,
245 MS_BOOL bFwDMA,
246 MS_BOOL bIQmem,
247 MS_BOOL bDQmem);
248
249 static void _HAL_TSP_tsif_select(MS_U8 u8_tsif);
250 // static void _HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 PadId);
251
252 //--------------------------------------------------------------------------------------------------
253 // Implementation
254 //--------------------------------------------------------------------------------------------------
_delay(void)255 static void _delay(void)
256 {
257 volatile MS_U32 i;
258 for (i = 0; i< 0xFFFFUL; i++);
259 }
260
_HAL_REG32_R(REG32 * reg)261 static MS_U32 _HAL_REG32_R(REG32 *reg)
262 {
263 MS_U32 value = 0UL;
264 value = (reg)->H << 16UL;
265 value |= (reg)->L;
266 return value;
267 }
268
_HAL_REG32L_R(REG32_L * reg)269 static MS_U16 _HAL_REG32L_R(REG32_L *reg)
270 {
271 MS_U16 value;
272 value = (reg)->data;
273 return value;
274 }
275
_HAL_REG16_R(REG16 * reg)276 static MS_U16 _HAL_REG16_R(REG16 *reg)
277 {
278 MS_U16 value = 0;
279 value = (reg)->u16data;
280 return value;
281 }
282
_HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)283 static MS_PHY _HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)
284 {
285 #ifdef HAL_MIU2_BASE
286 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
287 return (MS_PHY)HAL_MIU2_BASE;
288 else
289 #endif //HAL_MIU2_BUS_BASE
290 #ifdef HAL_MIU1_BASE
291 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
292 return (MS_PHY)HAL_MIU1_BASE;
293 else
294 #endif //HAL_MIU1_BUS_BASE
295 return (MS_PHY)HAL_MIU0_BASE;
296 }
297
298 #define REG16_T(addr) (*((volatile MS_U16*)(addr)))
299 #define ADDR_INDR_CTRL (_virtRegBase+ 0x2b20UL)
300 #define ADDR_INDR_ADDR0 (_virtRegBase+ 0x2b24UL)
301 #define ADDR_INDR_ADDR1 (_virtRegBase+ 0x2b28UL)
302 #define ADDR_INDR_WRITE0 (_virtRegBase+ 0x2b2cUL)
303 #define ADDR_INDR_WRITE1 (_virtRegBase+ 0x2b30UL)
304 #define ADDR_INDR_READ0 (_virtRegBase+ 0x2b34UL)
305 #define ADDR_INDR_READ1 (_virtRegBase+ 0x2b38UL)
306
307 #if 0
308 #define XBYTE_1591 (_virtRegBase+ 0x2a0cUL) // TsRec_Head21_Mid20
309 #define XBYTE_15A4 (_virtRegBase+ 0x2a10UL) // TsRec_Mid21_Tail20
310 #define XBYTE_15A6 (_virtRegBase+ 0x2b48UL) // TsRec_Mid
311
312 void HAL_TSP_HW_Lock_Init(void)
313 {
314 REG16_T(XBYTE_1591) = 0;
315 REG16_T(XBYTE_15A4) = 0;
316 REG16_T(XBYTE_15A6) = 0;
317 }
318
319 void _HAL_TSP_HW_Lock(void)
320 {
321 #ifdef MCU_HK
322 REG16_T(XBYTE_1591) = 0xFF;
323 REG16_T(XBYTE_15A4) = 0xFF;
324 while (REG16_T(XBYTE_15A4) && REG16_T(XBYTE_15A6));
325 REG16_T(XBYTE_1591) = 0xFF;
326 #else // MIPS HK
327 REG16_T(XBYTE_15A6) = 0xFF;
328 REG16_T(XBYTE_15A4) = 0x00;
329 while (REG16_T(XBYTE_1591) && (REG16_T(XBYTE_15A4)==0));
330 #endif
331 }
332
333 void _HAL_TSP_HW_Unlock(void)
334 {
335 #ifdef MCU_HK
336 REG16_T(XBYTE_1591) = 0x00;
337 #else
338 REG16_T(XBYTE_15A6) = 0x00;
339 #endif
340 }
341
342 #undef XBYTE_1591
343 #undef XBYTE_15A4
344 #undef XBYTE_15A6
345
346 #else
347
348 #define TSP_SEM_AEON (_virtRegBase+ 0xC1480UL) //TSP_HW_SEMAPHORE0, TS3 0x20
349 #define TSP_SEM_ORDER (_virtRegBase+ 0xC1484UL) // TSP_HW_SEMAPHORE1, TS3 0x21
350 #define TSP_SEM_MIPS (_virtRegBase+ 0xC1488UL) // TSP_HW_SEMAPHORE2, TS3 0x22
351
HAL_TSP_HW_Lock_Init(void)352 void HAL_TSP_HW_Lock_Init(void)
353 {
354 REG16_T(TSP_SEM_AEON) = 0;
355 REG16_T(TSP_SEM_MIPS) = 0;
356 REG16_T(TSP_SEM_ORDER) = 0;
357
358 _HAL_HALTSP_ENTRY();
359 }
360
_HAL_TSP_HW_TryLock(MS_BOOL bInit)361 static MS_BOOL _HAL_TSP_HW_TryLock(MS_BOOL bInit)
362 {
363 if (_bIsHK)
364 {
365 if (bInit)
366 {
367 REG16_T(TSP_SEM_AEON) = 0xFFFF;
368 REG16_T(TSP_SEM_ORDER) = 0xFFFF;
369 }
370 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS))
371 {
372 // REG16_T(TSP_SEM_AEON) = 0x0000;
373 return FALSE;
374 }
375 return TRUE;
376 }
377 else
378 {
379 if (bInit)
380 {
381 REG16_T(TSP_SEM_MIPS) = 0xFFFF;
382 REG16_T(TSP_SEM_ORDER) = 0x00;
383 }
384 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON)))
385 {
386 // REG16_T(TSP_SEM_MIPS) = 0x0000;
387 return FALSE;
388 }
389 return TRUE;
390 }
391 }
392
_HAL_TSP_HW_Lock(void)393 static void _HAL_TSP_HW_Lock(void)
394 {
395 if (FALSE == _HAL_TSP_HW_TryLock(TRUE))
396 {
397 while (FALSE == _HAL_TSP_HW_TryLock(FALSE));
398 }
399 }
400
_HAL_TSP_HW_Unlock(void)401 static void _HAL_TSP_HW_Unlock(void)
402 {
403 if (_bIsHK)
404 {
405 REG16_T(TSP_SEM_AEON) = 0x00;
406 }
407 else
408 {
409 REG16_T(TSP_SEM_MIPS) = 0x00;
410 }
411 }
412
HAL_TSP_HW_Lock_Release(void)413 void HAL_TSP_HW_Lock_Release(void)
414 {
415 REG16_T(TSP_SEM_AEON) = 0x00;
416 REG16_T(TSP_SEM_MIPS) = 0x00;
417
418 _HAL_HALTSP_EXIT();
419
420
421 }
422
HAL_TSP_TTX_IsAccess(MS_U32 u32Try)423 MS_BOOL HAL_TSP_TTX_IsAccess(MS_U32 u32Try)
424 {
425 if(u32Try == 0)
426 return FALSE;
427
428 if (_bIsHK)
429 {
430 if ( REG16_T(TSP_SEM_AEON))
431 {
432 return FALSE;
433 }
434 }
435 else
436 {
437 if (REG16_T(TSP_SEM_MIPS))
438 {
439 return FALSE;
440 }
441 }
442
443 if (_HAL_TSP_HW_TryLock(TRUE))
444 {
445 return TRUE;
446 }
447
448 _HAL_TSP_HW_Unlock();
449 return FALSE;
450 }
451
HAL_TSP_TTX_UnlockAccess(void)452 void HAL_TSP_TTX_UnlockAccess(void)
453 {
454 _HAL_TSP_HW_Unlock();
455 }
456
457 #undef TSP_SEM_AEON
458 #undef TSP_SEM_MIPS
459 #undef TSP_SEM_ORDER
460
461 #endif
462
HAL_REG32_IndR(REG32 * reg)463 MS_U32 HAL_REG32_IndR(REG32 *reg)
464 {
465 MS_VIRT virtReg = (MS_VIRT)reg;
466 MS_U32 u32Ret;
467
468 _HAL_TSP_HW_Lock();
469
470 _HAL_HALTSP_LOCK();
471
472 // set address
473 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
474 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
475
476 // set command
477 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
478 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
479 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
480
481 // get read value
482 u32Ret = ((MS_U32)(REG16_T(ADDR_INDR_READ0))| ((MS_U32)(REG16_T(ADDR_INDR_READ1)<< 16UL)));
483
484 _HAL_HALTSP_UNLOCK();
485 _HAL_TSP_HW_Unlock();
486 return u32Ret;
487 }
488
HAL_REG32_IndR_tmp(REG32 * reg)489 static MS_U32 HAL_REG32_IndR_tmp(REG32 *reg)
490 {
491 MS_VIRT virtReg = (MS_VIRT)reg;
492 MS_U32 u32Ret;
493
494 _HAL_HALTSP_LOCK();
495
496 // set address
497 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
498 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
499
500 // set command
501 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
502 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
503 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
504
505 // get read value
506 u32Ret = ((MS_U32)(REG16_T(ADDR_INDR_READ0))| ((MS_U32)(REG16_T(ADDR_INDR_READ1)<< 16)));
507
508 _HAL_HALTSP_UNLOCK();
509
510 return u32Ret;
511 }
HAL_REG32_IndW_tmp(REG32 * reg,MS_U32 value)512 static void HAL_REG32_IndW_tmp(REG32 *reg, MS_U32 value)
513 {
514 MS_VIRT virtReg = (MS_VIRT)reg;
515 _HAL_HALTSP_LOCK();
516
517 // set address
518 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
519 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
520
521 // set write value
522 REG16_T(ADDR_INDR_WRITE0)= (MS_U16)value;
523 REG16_T(ADDR_INDR_WRITE1)= (MS_U16)(value >> 16UL);
524
525 // set command
526 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
527 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
528 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
529
530 _HAL_HALTSP_UNLOCK();
531 }
532
HAL_REG32_IndW(REG32 * reg,MS_U32 value)533 void HAL_REG32_IndW(REG32 *reg, MS_U32 value)
534 {
535 MS_VIRT virtReg = (MS_VIRT)reg;
536 _HAL_TSP_HW_Lock();
537
538 _HAL_HALTSP_LOCK();
539
540 // set address
541 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
542 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
543
544 // set write value
545 REG16_T(ADDR_INDR_WRITE0)= (MS_U16)value;
546 REG16_T(ADDR_INDR_WRITE1)= (MS_U16)(value >> 16UL);
547
548 // set command
549 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
550 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
551 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
552
553 _HAL_HALTSP_UNLOCK();
554
555 _HAL_TSP_HW_Unlock();
556 }
557
558 static MS_U16 u16LastAddr0, u16LastAddr1, u16LastWrite0, u16LastWrite1, u16LastRead0, u16LastRead1;
559
560 static MS_U32 _u32PidFltBuf[(TSP_PIDFLT_NUM_ALL*sizeof(REG_PidFlt))>> 3];
561 static MS_U32 _u32SecFltBuf[TSP_SECFLT_NUM*((sizeof(REG_SecFlt)-sizeof((((REG_SecFlt*)0)->_x50)))>> 3)];
562 //[LEGACY] //[OBSOLETE]
563 MS_BOOL _bIsHK = TRUE;
564 //[LEGACY] //[OBSOLETE]
HAL_TSP_SaveFltState(void)565 void HAL_TSP_SaveFltState(void)
566 {
567 MS_U32 u32EngId;
568 MS_U32 i, j;
569 MS_U32 u32SecEnd = ((size_t)&(((REG_SecFlt*)0)->_x50))/sizeof(REG32);
570
571 for (u32EngId = 0; u32EngId < TSP_ENGINE_NUM; u32EngId++)
572 {
573 for (i = 0; i < TSP_PIDFLT_NUM_ALL; i++)
574 {
575 REG_PidFlt *pPidFilter = &(_TspPid[u32EngId].Flt[i]);
576 _u32PidFltBuf[i] = HAL_REG32_IndR(pPidFilter);
577 }
578 j = 0;
579 for (i = 0; i < TSP_SECFLT_NUM; i++)
580 {
581 REG32* pRegStart = (REG32*) &(_TspSec[u32EngId].Flt[i]);
582 // REG32* pRegEnd = (REG32*)&(_TspSec[u32EngId].Flt[i + 1]);
583 REG32* pRegEnd = pRegStart + u32SecEnd;
584 REG32* pReg = pRegStart;
585 while (pReg < pRegEnd)
586 {
587 _u32SecFltBuf[j] = HAL_REG32_IndR(pReg);
588 j++;
589 pReg++;
590 }
591 }
592 }
593 }
HAL_TSP_RestoreFltState(void)594 void HAL_TSP_RestoreFltState(void)
595 {
596 MS_U32 u32EngId;
597 MS_U32 i, j;
598 MS_U32 u32SecEnd = ((size_t)&(((REG_SecFlt*)0)->_x50))/sizeof(REG32);
599
600 for (u32EngId = 0; u32EngId < TSP_ENGINE_NUM; u32EngId++)
601 {
602 for (i = 0; i < TSP_PIDFLT_NUM_ALL; i++)
603 {
604 REG_PidFlt *pPidFilter = &(_TspPid[u32EngId].Flt[i]);
605 HAL_REG32_IndW(pPidFilter, _u32PidFltBuf[i]);
606 }
607 j = 0;
608 for (i = 0; i < TSP_SECFLT_NUM; i++)
609 {
610 REG32* pRegStart = (REG32*) &(_TspSec[u32EngId].Flt[i]);
611 REG32* pRegEnd = pRegStart + u32SecEnd;
612 REG32* pReg = pRegStart;
613 while (pReg < pRegEnd)
614 {
615 HAL_REG32_IndW(pReg, _u32SecFltBuf[j]);
616 j++;
617 pReg++;
618 }
619 }
620 }
621 }
622
623
HAL_TSP_ISR_SAVE_ALL(void)624 void HAL_TSP_ISR_SAVE_ALL(void)
625 {
626 // save address
627 u16LastAddr0= (MS_U16)REG16_T(ADDR_INDR_ADDR0);
628 u16LastAddr1= (MS_U16)REG16_T(ADDR_INDR_ADDR1);
629
630 // save write
631 u16LastWrite0= (MS_U16)REG16_T(ADDR_INDR_WRITE0);
632 u16LastWrite1= (MS_U16)REG16_T(ADDR_INDR_WRITE1);
633
634 // save read
635 u16LastRead0= (MS_U16)REG16_T(ADDR_INDR_READ0);
636 u16LastRead1= (MS_U16)REG16_T(ADDR_INDR_READ1);
637 }
638
HAL_TSP_ISR_RESTORE_ALL(void)639 void HAL_TSP_ISR_RESTORE_ALL(void)
640 {
641 // restore read
642 REG16_T(ADDR_INDR_READ0)= u16LastRead0;
643 REG16_T(ADDR_INDR_READ1)= u16LastRead1;
644
645 // restore write
646 REG16_T(ADDR_INDR_WRITE0)= u16LastWrite0;
647 REG16_T(ADDR_INDR_WRITE1)= u16LastWrite1;
648
649 // restore addr
650 REG16_T(ADDR_INDR_ADDR0)= u16LastAddr0;
651 REG16_T(ADDR_INDR_ADDR1)= u16LastAddr1;
652 }
653 #undef ADDR_INDR_CTRL
654 #undef ADDR_INDR_ADDR0
655 #undef ADDR_INDR_ADDR1
656 #undef ADDR_INDR_WRITE0
657 #undef ADDR_INDR_WRITE1
658 #undef ADDR_INDR_READ0
659 #undef ADDR_INDR_READ1
660
661 //--------------------------------------------------------------------------------------------------
662 // For MISC part
663 //--------------------------------------------------------------------------------------------------
HAL_TSP_Scmb_Detect(MS_BOOL bEnable)664 void HAL_TSP_Scmb_Detect(MS_BOOL bEnable)
665 {
666 if (bEnable)
667 {
668 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
669 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld));
670 }
671 else
672 {
673 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
674 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld));
675 }
676 }
677
HAL_TSP_CSA_Set_ScrmPath(MS_U32 u32ScrmPath)678 void HAL_TSP_CSA_Set_ScrmPath(MS_U32 u32ScrmPath)
679 {
680 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL, u32ScrmPath);
681 }
682
HAL_TSP_Set_AVPAUSE(MS_BOOL bSet)683 void HAL_TSP_Set_AVPAUSE(MS_BOOL bSet)
684 {
685 if (bSet)
686 {
687 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL,
688 SET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE));
689 }
690 else
691 {
692 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL,
693 RESET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE));
694 }
695 }
696
HAL_TSP_CSA_Get_ScrmPath(void)697 MS_U32 HAL_TSP_CSA_Get_ScrmPath(void)
698 {
699 return (MS_U32)(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL) & TSP_CA_CTRL_MASK);
700 }
701
702 //--------------------------------------------------------------------------------------------------
703 // For PID filter part
704 //--------------------------------------------------------------------------------------------------
HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt * pPidFilter)705 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFilter)
706 {
707 return (HAL_REG32_IndR((REG32 *)pPidFilter) & TSP_PIDFLT_OUT_MASK);
708 }
709
HAL_TSP_PidFlt_GetPid(REG_PidFlt * pPidFilter)710 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFilter)
711 {
712 return (HAS_FLAG(HAL_REG32_IndR((REG32 *)pPidFilter), TSP_PIDFLT_PID_MASK)>> TSP_PIDFLT_PID_SHFT);
713 }
714
HAL_TSP_PidFlt_SetPid(REG_PidFlt * pPidFilter,MS_U32 u32PID)715 void HAL_TSP_PidFlt_SetPid(REG_PidFlt *pPidFilter, MS_U32 u32PID)
716 {
717 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_PID_MASK) | ((u32PID << TSP_PIDFLT_PID_SHFT) & TSP_PIDFLT_PID_MASK));
718 }
719
HAL_TSP_PidFlt_SelFltOutput(REG_PidFlt * pPidFilter,MS_U32 u32FltOutput)720 void HAL_TSP_PidFlt_SelFltOutput(REG_PidFlt *pPidFilter, MS_U32 u32FltOutput)
721 {
722 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_OUT_MASK) | (u32FltOutput & TSP_PIDFLT_OUT_MASK));
723 }
724
HAL_TSP_PidFlt_SelSecFlt(REG_PidFlt * pPidFilter,MS_U32 u32SecFltId)725 void HAL_TSP_PidFlt_SelSecFlt(REG_PidFlt *pPidFilter, MS_U32 u32SecFltId)
726 {
727 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_SECFLT_MASK) | ((u32SecFltId << TSP_PIDFLT_SECFLT_SHFT) & TSP_PIDFLT_SECFLT_MASK));
728 }
729
HAL_TSP_PidFlt_PVREnable(REG_PidFlt * pPidFilter)730 void HAL_TSP_PidFlt_PVREnable(REG_PidFlt *pPidFilter)
731 {
732 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) | TSP_PIDFLT_PVR_ENABLE));
733 }
734
735
HAL_TSP_SecFlt_SetType(REG_SecFlt * pSecFilter,MS_U32 u32FltType)736 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFilter, MS_U32 u32FltType)
737 {
738 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, (HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~TSP_SECFLT_TYPE_MASK) | (u32FltType << TSP_SECFLT_TYPE_SHFT));
739 }
740
HAL_TSP_PidFlt_GetSecFlt(REG_PidFlt * pPidFilter)741 MS_U32 HAL_TSP_PidFlt_GetSecFlt(REG_PidFlt *pPidFilter)
742 {
743 return ((HAL_REG32_IndR((REG32 *)pPidFilter) & TSP_PIDFLT_SECFLT_MASK) >> TSP_PIDFLT_SECFLT_SHFT);
744 }
745
HAL_TSP_PidFlt_SelFltSource(REG_PidFlt * pPidFilter,MS_U32 u32FltSource)746 void HAL_TSP_PidFlt_SelFltSource(REG_PidFlt *pPidFilter, MS_U32 u32FltSource)
747 {
748 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_IN_MASK) | (u32FltSource & TSP_PIDFLT_IN_MASK));
749 }
750
751 //--------------------------------------------------------------------------------------------------
752 // For section filter part
753 //--------------------------------------------------------------------------------------------------
HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt * pSecFilter)754 MS_U32 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFilter)
755 {
756 return (pSecFilter - (REG_SecFlt*)REG_SECFLT_BASE)>> 8; // div 0x100
757 }
758
HAL_TSP_SecFlt_ResetState(REG_SecFlt * pSecFilter)759 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFilter)
760 {
761 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~(TSP_SECFLT_STATE_MASK));
762 }
763
HAL_TSP_SecFlt_SetRmnCount(REG_SecFlt * pSecFilter,MS_U32 u32RmnCount)764 void HAL_TSP_SecFlt_SetRmnCount(REG_SecFlt *pSecFilter, MS_U32 u32RmnCount)
765 {
766 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_RMNCNT_MASK) |
767 ((u32RmnCount << TSP_SECFLT_RMNCNT_SHFT) & TSP_SECFLT_RMNCNT_MASK));
768 }
769
HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt * pSecFilter)770 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFilter)
771 {
772 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, 0);
773 }
774
775
HAL_TSP_SW_INT_STATUS(void)776 MS_U32 HAL_TSP_SW_INT_STATUS(void)
777 {
778 if (_bIsHK)
779 {
780 return _HAL_REG32_R(&_TspCtrl[0].SwInt_Stat);
781 }
782 else
783 {
784 MS_U32 u32SwIntStatus = (MS_U32)_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_M);
785 u32SwIntStatus |= ((_HAL_REG32_R(&_TspCtrl[0].SwInt_Stat1_H) & TSP_SWINT1_H_MASK) >> TSP_SWINT1_H_SHFT)<< 16;
786 return u32SwIntStatus;
787 }
788 }
789
790 // match mask --> 0 will compare
HAL_TSP_SecFlt_SetMask(REG_SecFlt * pSecFilter,MS_U8 * pu8Mask)791 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFilter, MS_U8 *pu8Mask)
792 {
793 MS_U32 i;
794 MS_U32 u32Temp;
795 MS_U32 j;
796
797 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
798 {
799 j = (i<< 2);
800 u32Temp = (pu8Mask[j]) | (pu8Mask[j+ 1] << 8 ) | (pu8Mask[j+ 2] << 16 )| (pu8Mask[j+ 3] << 24);
801 HAL_REG32_IndW((REG32 *)&pSecFilter->Mask[i], u32Temp);
802 }
803 }
804
805 // not match mask --> 1 will compare
HAL_TSP_SecFlt_SetNMask(REG_SecFlt * pSecFilter,MS_U8 * pu8NMask)806 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFilter, MS_U8 *pu8NMask)
807 {
808 MS_U32 u32FltId;
809 MS_U32 u32Temp;
810 REG_SecFlt* ptempSecFlt = &(_TspSec[0].Flt[31]);
811
812 u32Temp = (pu8NMask[0x0]) | (pu8NMask[0x1] << 8 ) | (pu8NMask[0x2] << 16 )| (pu8NMask[0x3] << 24);
813 HAL_REG32_IndW(&(ptempSecFlt->Match[0]), u32Temp);
814
815 u32Temp = (pu8NMask[0x4]) | (pu8NMask[0x5] << 8 ) | (pu8NMask[0x6] << 16 )| (pu8NMask[0x7] << 24);
816 HAL_REG32_IndW(&(ptempSecFlt->Match[1]), u32Temp);
817
818 u32Temp = (pu8NMask[0x8]) | (pu8NMask[0x9] << 8 ) | (pu8NMask[0xa] << 16 )| (pu8NMask[0xb] << 24);
819 HAL_REG32_IndW(&(ptempSecFlt->Match[2]), u32Temp);
820
821 u32Temp = (pu8NMask[0xc]) | (pu8NMask[0xd] << 8 ) | (pu8NMask[0xe] << 16 )| (pu8NMask[0xf] << 24);
822 HAL_REG32_IndW(&(ptempSecFlt->Match[3]), u32Temp);
823
824 u32FltId = (MS_U32)(pSecFilter - (REG_SecFlt*)REG_SECFLT_BASE);
825
826 //printf("[%s][%d] u32FltId %d\n", __FUNCTION__, __LINE__, (unsigned int)u32FltId);
827
828 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_NMATCH | u32FltId);
829
830 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
831 }
832
HAL_TSP_SecFlt_SetMatch(REG_SecFlt * pSecFilter,MS_U8 * pu8Match)833 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFilter, MS_U8 *pu8Match)
834 {
835 MS_U32 i;
836 MS_U32 u32Temp;
837 MS_U32 j;
838
839 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
840 {
841 j = (i<< 2);
842 u32Temp = (pu8Match[j]) | (pu8Match[j+ 1] << 8 ) | (pu8Match[j+ 2] << 16 )| (pu8Match[j+ 3] << 24);
843 HAL_REG32_IndW((REG32 *)&pSecFilter->Match[i], u32Temp);
844 }
845 }
846
HAL_TSP_SecFlt_SetReqCount(REG_SecFlt * pSecFilter,MS_U32 u32ReqCount)847 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFilter, MS_U32 u32ReqCount)
848 {
849 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_REQCNT_MASK) |
850 ((u32ReqCount << TSP_SECFLT_REQCNT_SHFT) & TSP_SECFLT_REQCNT_MASK));
851 }
852
HAL_TSP_SecFlt_SetMode(REG_SecFlt * pSecFilter,MS_U32 u32SecFltMode)853 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFilter, MS_U32 u32SecFltMode)
854 {
855 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, (HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~TSP_SECFLT_MODE_MASK) | ((u32SecFltMode << TSP_SECFLT_MODE_SHFT) & TSP_SECFLT_MODE_MASK));
856 }
857
HAL_TSP_SecFlt_GetCRC32(REG_SecFlt * pSecFilter)858 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFilter)
859 {
860 return HAL_REG32_IndR((REG32 *)&pSecFilter->CRC32);
861 }
862
HAL_TSP_SecFlt_GetState(REG_SecFlt * pSecFilter)863 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFilter)
864 {
865 return ((HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & TSP_SECFLT_STATE_MASK) >> TSP_SECFLT_STATE_SHFT);
866 }
867
HAL_TSP_SecFlt_GetMode(REG_SecFlt * pSecFilter)868 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFilter)
869 {
870 return ((HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & TSP_SECFLT_MODE_MASK) >> TSP_SECFLT_MODE_SHFT);
871 }
872
HAL_TSP_SecFlt_PcrReset(REG_SecFlt * pSecFilter)873 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFilter)
874 {
875 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) | TSP_SECFLT_PCRRST);
876 }
877
HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId)878 void HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId)
879 {
880 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_VER_RESET | u32SecFltId);
881 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
882 }
883
HAL_TSP_SecFlt_SetDataAddr(MS_PHY phyDataAddr)884 void HAL_TSP_SecFlt_SetDataAddr(MS_PHY phyDataAddr)
885 {
886 MS_PHY phyAddr = phyDataAddr - _HAL_TSP_MIU_OFFSET(phyDataAddr);
887 MS_U32 u32cmd = TSP_MCU_CMD_MEM_HIGH_ADDR | ((MS_U32)(phyAddr & 0xFFFF0000UL) >> 16UL);
888
889 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32cmd);
890 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
891
892 u32cmd = TSP_MCU_CMD_MEM_LOW_ADDR | ((MS_U32)(phyAddr & 0xFFFFUL));
893 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32cmd);
894 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
895 }
896
897
898 //--------------------------------------------------------------------------------------------------
899 // For section buffer part
900 //--------------------------------------------------------------------------------------------------
901 // To avoid SW read hidden HW byte enable information.
902 #define _TSP_SEC_BUF_ADDR_START(pSecFilter) (TSP_SECFLT_BUFSTART_MASK & HAL_REG32_IndR((REG32 *)&((pSecFilter)->BufStart)))
903
HAL_TSP_SecBuf_SetBuffer(REG_SecFlt * pSecBuf,MS_PHY phyStartAddr,MS_U32 u32BufSize)904 void HAL_TSP_SecBuf_SetBuffer(REG_SecFlt *pSecBuf, MS_PHY phyStartAddr, MS_U32 u32BufSize)
905 {
906 MS_PHY phyAddr = 0UL;
907
908 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyStartAddr);
909 phyAddr = phyStartAddr - _phySecBufMiuOffset;
910
911 HAL_REG32_IndW((REG32 *)&pSecBuf->BufStart, (MS_U32)phyAddr);
912 HAL_REG32_IndW((REG32 *)&pSecBuf->BufEnd, ((MS_U32)phyAddr + u32BufSize));
913 }
914
HAL_TSP_SecBuf_SetBufRead(REG_SecFlt * pSecBuf,MS_PHY phyReadAddr)915 void HAL_TSP_SecBuf_SetBufRead(REG_SecFlt *pSecBuf, MS_PHY phyReadAddr)
916 {
917 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyReadAddr);
918
919 HAL_REG32_IndW((REG32 *)&pSecBuf->BufRead, (MS_U32)(phyReadAddr-_phySecBufMiuOffset));
920 }
921
HAL_TSP_SecBuf_GetBufStart(REG_SecFlt * pSecBuf)922 MS_PHY HAL_TSP_SecBuf_GetBufStart(REG_SecFlt *pSecBuf)
923 {
924 return (((MS_PHY)_TSP_SEC_BUF_ADDR_START(pSecBuf) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
925 }
926
HAL_TSP_SecBuf_GetBufEnd(REG_SecFlt * pSecBuf)927 MS_PHY HAL_TSP_SecBuf_GetBufEnd(REG_SecFlt *pSecBuf)
928 {
929 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufEnd) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
930 }
931
HAL_TSP_SecBuf_GetBufCur(REG_SecFlt * pSecBuf)932 MS_PHY HAL_TSP_SecBuf_GetBufCur(REG_SecFlt *pSecBuf)
933 {
934 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufCur) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
935 }
936
HAL_TSP_SecBuf_ResetBuffer(REG_SecFlt * pSecBuf)937 void HAL_TSP_SecBuf_ResetBuffer(REG_SecFlt *pSecBuf)
938 {
939 HAL_REG32_IndW((REG32 *)&pSecBuf->BufCur, _TSP_SEC_BUF_ADDR_START(pSecBuf));
940 HAL_REG32_IndW((REG32 *)&pSecBuf->BufRead, _TSP_SEC_BUF_ADDR_START(pSecBuf));
941 HAL_REG32_IndW((REG32 *)&pSecBuf->BufWrite, _TSP_SEC_BUF_ADDR_START(pSecBuf));
942 }
943
HAL_TSP_SecBuf_GetBufRead(REG_SecFlt * pSecBuf)944 MS_PHY HAL_TSP_SecBuf_GetBufRead(REG_SecFlt *pSecBuf)
945 {
946 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufRead) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
947 }
948
HAL_TSP_SecBuf_GetBufWrite(REG_SecFlt * pSecBuf)949 MS_PHY HAL_TSP_SecBuf_GetBufWrite(REG_SecFlt *pSecBuf)
950 {
951 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufWrite) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
952 }
953
954 #undef _TSP_SEC_BUF_ADDR_START
955
HAL_TSP_SecBuf_SetBufRead_tmp(REG_SecFlt * pSecBuf,MS_PHY phyReadAddr)956 void HAL_TSP_SecBuf_SetBufRead_tmp(REG_SecFlt *pSecBuf, MS_PHY phyReadAddr)
957 {
958 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyReadAddr);
959 HAL_REG32_IndW_tmp((REG32 *)&pSecBuf->BufRead, (MS_U32)(phyReadAddr-_phySecBufMiuOffset));
960 }
961
HAL_TSP_SecBuf_GetBufWrite_tmp(REG_SecFlt * pSecBuf)962 MS_PHY HAL_TSP_SecBuf_GetBufWrite_tmp(REG_SecFlt *pSecBuf)
963 {
964 return (((MS_PHY)HAL_REG32_IndR_tmp((REG32 *)&pSecBuf->BufWrite) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
965 }
966
967 //--------------------------------------------------------------------------------------------------
968 // For DMA part
969 //--------------------------------------------------------------------------------------------------
970 //[HW LIMIT][HW TODO] TsDma pause can not be access by TSP CPU
971 //[HW LIMIT][HW TODO] TsDma pause it hard to control because read/write in different register
972 //[HW LIMIT][HW TODO] When setting TsDma it should be disable interrupt
HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay)973 void HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay)
974 {
975 // Richard: the file in timer in Uranus is 24 bits.
976 // to simplify the process, writing 32 bits directly.
977 // HW will truncate the high 8 bits out, and use low 24 bits only (from Albert Lin)
978 _HAL_REG32_W(&_TspCtrl[0].TsFileIn_Timer, u32Delay);
979 }
980
HAL_TSP_CmdQ_TsDma_SetAddr(MS_PHY phyStreamAddr)981 void HAL_TSP_CmdQ_TsDma_SetAddr(MS_PHY phyStreamAddr)
982 {
983 _phyFIBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyStreamAddr);
984 _HAL_REG32_W(&_TspCtrl[0].TsDma_Addr, (MS_U32)(phyStreamAddr-_phyFIBufMiuOffset));
985 }
986
HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize)987 MS_BOOL HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize)
988 {
989 if (u32StreamSize < 16) // t2 HW limite, CMQ had some problem while bufsize < 16
990 {
991 return FALSE;
992 }
993 _HAL_REG32_W(&_TspCtrl[0].TsDma_Size, u32StreamSize);
994 return TRUE;
995 }
996
HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl)997 void HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl)
998 {
999 // enable filein byte timer
1000 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1001 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_BYTE_TIMER_EN));
1002
1003 _HAL_REG32_W(&_TspCtrl[0].TsDma_Ctrl_CmdQ, TSP_TSDMA_CTRL_START | (u32TsDmaCtrl & TSP_TSDMA_CTRL_PESMODE_MASK));
1004 }
1005
HAL_TSP_TsDma_Pause(void)1006 void HAL_TSP_TsDma_Pause(void)
1007 {
1008 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1009 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE));
1010 }
1011
HAL_TSP_TsDma_Resume(void)1012 void HAL_TSP_TsDma_Resume(void)
1013 {
1014 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1015 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE));
1016 }
1017
HAL_TSP_CmdQ_TsDma_GetState(void)1018 MS_U32 HAL_TSP_CmdQ_TsDma_GetState(void)
1019 {
1020 return (HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ), TSP_TSDMA_CTRL_START) |
1021 (MS_U32)(HAS_FLAG(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)));
1022 }
1023
HAL_TSP_CmdQ_EmptyCount(void)1024 MS_U32 HAL_TSP_CmdQ_EmptyCount(void)
1025 {
1026 return (TSP_CMDQ_SIZE - ((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_CNT_MASK)>>TSP_CMDQ_CNT_SHFT));
1027 }
1028
HAL_TSP_Get_CmdQFifoLevel(void)1029 MS_U8 HAL_TSP_Get_CmdQFifoLevel(void)
1030 {
1031 return (MS_U8)((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT);
1032 }
1033
HAL_TSP_SetCtrlMode(MS_U32 u32EngId,MS_U32 u32Mode,MS_U32 u32TsIfId)1034 void HAL_TSP_SetCtrlMode(MS_U32 u32EngId, MS_U32 u32Mode, MS_U32 u32TsIfId)
1035 {
1036 // Control bits:
1037 // TSP_CTRL_CPU_EN
1038 // TSP_CTRL_SW_RST
1039 // TSP_CTRL_MEM_DMA_EN
1040
1041 // for file in related setting
1042 if(u32Mode == 0)
1043 {
1044 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1045 (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl) & ~(TSP_CTRL_CPU_EN |
1046 TSP_CTRL_SW_RST |
1047 TSP_CTRL_TSFILE_EN)));
1048 HAL_TSP_filein_enable(FALSE);
1049 }
1050 else
1051 {
1052 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1053 (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl) & ~(TSP_CTRL_CPU_EN |
1054 TSP_CTRL_SW_RST |
1055 //TSP_CTRL_TSFILE_EN |
1056 //[URANUS] TSP_CTRL_CLK_GATING_DISABLE |
1057 // @FIXME: Richard ignore this at this stage
1058 0 )) | u32Mode);
1059
1060 if(HAS_FLAG(u32Mode, TSP_CTRL_TSFILE_EN))
1061 HAL_TSP_filein_enable(TRUE);
1062 }
1063
1064 if (TSP_IF_NUM > u32TsIfId)
1065 {
1066 _HAL_TSP_tsif_select(HAS_FLAG(u32Mode, (MS_U8)(u32TsIfId & 0xFF)));
1067 }
1068 }
1069
1070 //--------------------------------------------------------------------------------------------------
1071 // For PVR part
1072 //--------------------------------------------------------------------------------------------------
HAL_TSP_PVR_SetBuffer(MS_PHY phyBufStart0,MS_PHY phyBufStart1,MS_U32 u32BufSize0,MS_U32 u32BufSize1)1073 void HAL_TSP_PVR_SetBuffer(MS_PHY phyBufStart0, MS_PHY phyBufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1)
1074 {
1075 MS_PHY phyBufEnd;
1076
1077 _phyPVRBufMiuOffset[0] = _HAL_TSP_MIU_OFFSET(phyBufStart0);
1078
1079 // for buffer 0
1080 phyBufEnd= phyBufStart0+ u32BufSize0;
1081 _HAL_REG32_W(&_TspCtrl[0].TsRec_Head, ((MS_U32)(phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)); // 8 bytes unit
1082 _HAL_REG32_W(&_TspCtrl[0].TsRec_Tail, ((MS_U32)(phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)); // 8 bytes unit
1083
1084 // for buffer 1
1085 phyBufEnd= phyBufStart1+ u32BufSize1;
1086 #define ADDR_PVR_HEAD20 (_virtRegBase+ 0x2a04)
1087 #define ADDR_PVR_HEAD21 (_virtRegBase+ 0x2a08)
1088 #define ADDR_PVR_MID20 (_virtRegBase+ 0x2a0c)
1089 #define ADDR_PVR_MID21 (_virtRegBase+ 0x2a10)
1090 #define ADDR_PVR_TAIL20 (_virtRegBase+ 0x2a14)
1091 #define ADDR_PVR_TAIL21 (_virtRegBase+ 0x2a18)
1092 REG16_T(ADDR_PVR_HEAD20)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF;
1093 REG16_T(ADDR_PVR_HEAD21)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF;
1094 REG16_T(ADDR_PVR_TAIL20)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF;
1095 REG16_T(ADDR_PVR_TAIL21)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF;
1096 #undef ADDR_PVR_HEAD20
1097 #undef ADDR_PVR_HEAD21
1098 #undef ADDR_PVR_MID20
1099 #undef ADDR_PVR_MID21
1100 #undef ADDR_PVR_TAIL20
1101 #undef ADDR_PVR_TAIL21
1102
1103 // enable PVR ping pong buffer
1104 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1105 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_STR2MI_MIU_PINPON_EN));
1106
1107 // flush PVR buffer
1108 HAL_TSP_PVR_WaitFlush();
1109 }
1110
HAL_TSP_PVR_Enable(MS_BOOL bEnable)1111 void HAL_TSP_PVR_Enable(MS_BOOL bEnable)
1112 {
1113 //set burst len = 1
1114 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1115 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_burst_len_MASK));
1116
1117 // disable timeshift write protect -- it must enable while record/playback use the same buffer
1118 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1119 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP));
1120
1121 if (bEnable)
1122 {
1123 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1124 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE));
1125 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1126 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1127 }
1128 else
1129 {
1130 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1131 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE));
1132 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1133 // RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1134 }
1135 }
1136
HAL_TSP_PVR_Reset(void)1137 void HAL_TSP_PVR_Reset(void)
1138 {
1139 // Richard: @FIXME:
1140 // Don't know PVR "reset" definition. call flush instead.
1141 HAL_TSP_PVR_WaitFlush();
1142 }
1143
HAL_TSP_PVR_All(MS_BOOL bPvrAll)1144 void HAL_TSP_PVR_All(MS_BOOL bPvrAll)
1145 {
1146 if (bPvrAll)
1147 {
1148 // bypass mode
1149 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1150 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1151 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1152 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN));
1153 }
1154 else
1155 {
1156 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1157 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1158 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1159 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN));
1160 }
1161 }
1162
HAL_TSP_PVR_Filein_Enable(MS_BOOL bBypassHD,MS_BOOL bEnable,MS_BOOL bRecAll)1163 void HAL_TSP_PVR_Filein_Enable(MS_BOOL bBypassHD, MS_BOOL bEnable, MS_BOOL bRecAll)
1164 {
1165 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].reg15b4);
1166
1167 if(bBypassHD)
1168 u32data |= TSP_PVR_TS_HEADER;
1169 else
1170 u32data &= ~TSP_PVR_TS_HEADER;
1171
1172 if(bRecAll)
1173 {
1174 u32data |= TSP_REC_ALL_FILE;
1175 }
1176 else
1177 {
1178 u32data &= ~TSP_REC_ALL_FILE;
1179 }
1180
1181 if(bEnable)
1182 u32data |= TSP_PVR_FILEIN;
1183 else
1184 u32data &= ~TSP_PVR_FILEIN;
1185
1186 _HAL_REG32_W(&_TspCtrl[0].reg15b4, u32data);
1187 }
1188
HAL_TSP_PVR_Eng_IsEnabled(MS_U32 u32EngId)1189 MS_BOOL HAL_TSP_PVR_Eng_IsEnabled(MS_U32 u32EngId)
1190 {
1191 if(u32EngId == 0)
1192 {
1193 return ((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PVR_ENABLE) > 0);
1194 }
1195 else
1196 {
1197 return FALSE;
1198 }
1199 }
1200
HAL_TSP_LiveAB_En(MS_BOOL bPF_EN)1201 void HAL_TSP_LiveAB_En(MS_BOOL bPF_EN)
1202 {
1203 if (bPF_EN)
1204 {
1205 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_LIVEAB_SEL);
1206 }
1207 else
1208 {
1209 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_LIVEAB_SEL);
1210 }
1211 }
1212
HAL_TSP_IsLiveAB_Enable(void)1213 MS_BOOL HAL_TSP_IsLiveAB_Enable(void)
1214 {
1215 return ((_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & TSP_LIVEAB_SEL) != 0);
1216 }
1217
HAL_TSP_SetPKTSize(MS_U32 u32PKTSize)1218 void HAL_TSP_SetPKTSize(MS_U32 u32PKTSize)
1219 {
1220 if((u32PKTSize == 0x82) || (u32PKTSize == 0x86)) // RVU
1221 {
1222 printf("HAL_TSP_SetPKTSize: This chip not support RVU!\n"); // not support
1223 }
1224 else
1225 {
1226 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_ALT_TS_SIZE));
1227 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, (_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein)&~TSP_PKT_SIZE_MASK)|(TSP_PKT_SIZE_MASK&u32PKTSize));
1228 }
1229 }
1230
1231 // Set 1 to disable file-in timestamp block scheme, bypass timestamp
HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable)1232 void HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable)
1233 {
1234 if (!bEnable)
1235 {
1236 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_PKT192_BLK_DIS_FIN);
1237 }
1238 else
1239 {
1240 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_PKT192_BLK_DIS_FIN);
1241 }
1242 }
1243
1244
HAL_TSP_PVR_GetBufWrite(void)1245 MS_PHY HAL_TSP_PVR_GetBufWrite(void)
1246 {
1247 MS_PHY phyvalue;
1248
1249 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
1250 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD));
1251 phyvalue = (MS_PHY)(_HAL_REG32_R(&_TspCtrl[0].TsRec_WPtr)<< MIU_BUS) + _phyPVRBufMiuOffset[0];
1252 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
1253 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD));
1254
1255 return phyvalue;
1256
1257 }
1258
HAL_TSP_PVR_WaitFlush(void)1259 void HAL_TSP_PVR_WaitFlush(void)
1260 {
1261 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1262 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH));
1263 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1264 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH));
1265 }
1266
HAL_TSP_PVR_REC_FLT_Enable(MS_BOOL bEnable)1267 void HAL_TSP_PVR_REC_FLT_Enable(MS_BOOL bEnable)
1268 {
1269 if(bEnable)
1270 {
1271 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1272 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1273 }
1274 else
1275 {
1276 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1277 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1278 }
1279 }
1280
1281
1282 //--------------------------------------------------------------------------------------------------
1283 // For FW part
1284 //--------------------------------------------------------------------------------------------------
1285 /*
1286 void HAL_TSP_SetFwMsg(MS_U32 u32Mode)
1287 {
1288 _HAL_REG32_W(&_TspCtrl[0].Mcu_Msg, u32Mode);
1289 }
1290
1291 MS_U32 HAL_TSP_GetFwMsg(void)
1292 {
1293 return (_HAL_REG32_R(&_TspCtrl[0].Mcu_Msg));
1294 }
1295 */
1296
1297 static MS_U32 _u32FlowPadMap[2] = { 0x0, 0x0};
1298
1299 //--------------------------------------------------------------------------------------------------
1300 // For pad select part
1301 //--------------------------------------------------------------------------------------------------
HAL_TSP_SelPad(MS_U32 u32EngId,MS_U32 u32Flow,MS_U32 u32Pad)1302 void HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 u32Flow, MS_U32 u32Pad)
1303 {
1304
1305 MS_U32 u32Shft = 0;
1306
1307 MS_ASSERT(4 >= u32Pad);
1308
1309 if(u32Flow >= TSP_IF_NUM)
1310 {
1311 return;
1312 }
1313
1314 switch (u32Pad)
1315 {
1316 case 0: // internal demod
1317 u32Pad = TSP_MUX_INDEMOD;
1318 break;
1319 //ts0 pad is null
1320 case 2: // TS1 pad
1321 u32Pad = TSP_MUX_TS1;
1322 if(_bTsPadUsed[1] == FALSE)
1323 {
1324 TSP_TOP_REG(REG_TOP_TS1_PE) = TSP_TOP_REG(REG_TOP_TS1_PE)| REG_TOP_TS_PE_MASK;
1325 _bTsPadUsed[1] = TRUE;
1326 }
1327 break;
1328 case 4: // TS2 pad
1329 u32Pad = TSP_MUX_TS2;
1330 if(_bTsPadUsed[2] == FALSE)
1331 {
1332 TSP_TOP_REG(REG_TOP_TS2_PE) = TSP_TOP_REG(REG_TOP_TS2_PE)| REG_TOP_TS_PE_MASK;
1333 _bTsPadUsed[2] = TRUE;
1334 }
1335 break;
1336 default:
1337 return ;
1338 }
1339
1340 _u32FlowPadMap[u32Flow] = u32Pad;
1341
1342 if(u32Flow == 0)
1343 u32Shft= REG_TOP_TSN_MUX_TS0_SHIFT;
1344 else
1345 u32Shft = REG_TOP_TSN_MUX_TS1_SHIFT;
1346
1347 TSP_TOP_REG(REG_TOP_TSN_MUX) = (TSP_TOP_REG(REG_TOP_TSN_MUX) & ~(REG_TOP_TSN_MUX_MASK<< u32Shft)) | (u32Pad<< u32Shft);
1348
1349 }
1350
HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId,MS_U32 u32Flow,MS_BOOL bClkInv)1351 void HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bClkInv)
1352 {
1353 MS_U32 u32Clk = 0;
1354 MS_U32 u32Shft = 0;
1355
1356 if(u32Flow >= TSP_IF_NUM)
1357 {
1358 return;
1359 }
1360
1361 if(_u32FlowPadMap[u32Flow] == TSP_MUX_INDEMOD)
1362 u32Clk = TSP_CLK_INDEMOD;
1363 else if(_u32FlowPadMap[u32Flow] == TSP_MUX_TS1)
1364 u32Clk = TSP_CLK_TS1;
1365 else if(_u32FlowPadMap[u32Flow] == TSP_MUX_TS2)
1366 u32Clk = TSP_CLK_TS2;
1367
1368 if (bClkInv)
1369 {
1370 u32Clk |= TSP_CLK_INVERSE;
1371 }
1372
1373 u32Shft = (0 == u32Flow)? 0: 8;
1374 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< u32Shft)) | (u32Clk<< u32Shft);
1375 }
1376
HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId,MS_BOOL bExtSync,MS_U32 u32Flow)1377 void HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId, MS_BOOL bExtSync, MS_U32 u32Flow)
1378 {
1379 REG32* pReg = NULL;
1380 MS_U32 u32ExtSync = 0;
1381
1382 if (0 == u32Flow)
1383 {
1384 pReg = &(_TspCtrl[0].Hw_Config0);
1385 u32ExtSync = TSP_HW_CFG0_TSIF0_EXTSYNC;
1386 }
1387 else if (1 == u32Flow)
1388 {
1389 pReg = &(_TspCtrl[0].Hw_Config2);
1390 u32ExtSync = TSP_HW_CFG2_TSIF1_EXTSYNC;
1391 }
1392 else
1393 {
1394 //ASSERT(0);
1395 return;
1396 }
1397
1398 if (bExtSync)
1399 {
1400 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32ExtSync));
1401 }
1402 else
1403 {
1404 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32ExtSync));
1405 }
1406 }
1407
HAL_TSP_SelPad_Parl(MS_U32 u32EngId,MS_BOOL bParl,MS_U32 u32Flow)1408 void HAL_TSP_SelPad_Parl(MS_U32 u32EngId, MS_BOOL bParl, MS_U32 u32Flow)
1409 {
1410 REG32* pReg = NULL;
1411 MS_U32 u32Parl = 0;
1412 MS_U32 u32Pad = _u32FlowPadMap[u32Flow];
1413
1414 if (0 == u32Flow) // TS_IF0
1415 {
1416 pReg = &(_TspCtrl[0].Hw_Config0);
1417 u32Parl = TSP_HW_CFG0_TSIF0_PARL;
1418 }
1419 else if (1 == u32Flow) // TS_IF1
1420 {
1421 pReg = &(_TspCtrl[0].Hw_Config2);
1422 u32Parl = TSP_HW_CFG2_TSIF1_PARL;
1423 }
1424 else
1425 {
1426 //ASSERT(0);
1427 return;
1428 }
1429
1430 if(u32Pad == TSP_MUX_TS1)
1431 {
1432 if(bParl)
1433 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~(REG_TOP_TS_TS1_CFG_MASK<< REG_TOP_TS1CFG_SHIFT)) | (REG_TOP_TS1_PARALLEL_IN<< REG_TOP_TS1CFG_SHIFT);
1434 else
1435 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~(REG_TOP_TS_TS1_CFG_MASK<< REG_TOP_TS1CFG_SHIFT)) | (REG_TOP_TS1_SERIAL_IN<< REG_TOP_TS1CFG_SHIFT);
1436 }
1437 else if(u32Pad == TSP_MUX_TS2)
1438 {
1439 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~(REG_TOP_TS_TS2_CFG_MASK<< REG_TOP_TS2CFG_SHIFT)) | (REG_TOP_TS2_SERIAL_IN<< REG_TOP_TS2CFG_SHIFT);
1440 }
1441
1442 if (bParl) // parallel
1443 {
1444 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32Parl));
1445 }
1446 else // serial
1447 {
1448 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32Parl));
1449 }
1450 }
1451
HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId,MS_U32 u32Flow,MS_BOOL bInvert)1452 void HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bInvert)
1453 {
1454 REG32* pReg = &(_TspCtrl[0].Hw_Config4);
1455 MS_U32 u32Invert = 0;
1456
1457 if(0 == u32Flow)
1458 {
1459 u32Invert = TSP_HW_CFG4_TS_DATA0_SWAP;
1460 }
1461 else if(1 == u32Flow)
1462 {
1463 u32Invert = TSP_HW_CFG4_TS_DATA1_SWAP;
1464 }
1465 else
1466 {
1467 return;
1468 }
1469
1470 if(bInvert)
1471 {
1472 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32Invert));
1473 }
1474 else
1475 {
1476 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32Invert));
1477 }
1478 }
1479
HAL_TSP_GetCap(MS_U32 u32Cap,void * pData)1480 MS_BOOL HAL_TSP_GetCap(MS_U32 u32Cap, void* pData)
1481 {
1482 MS_BOOL bRet = TRUE;
1483
1484 switch (u32Cap)
1485 {
1486 case HAL_TSP_CAP_PID_FILTER_NUM:
1487 *((MS_U32*)pData) = TSP_PIDFLT_NUM_ALL;
1488 break;
1489 case HAL_TSP_CAP_SEC_FILTER_NUM:
1490 *((MS_U32*)pData) = TSP_SECFLT_NUM;
1491 break;
1492 case HAL_TSP_CAP_SEC_BUF_NUM:
1493 *((MS_U32*)pData) = TSP_SECBUF_NUM;
1494 break;
1495 case HAL_TSP_CAP_PVR_ENG_NUM:
1496 *((MS_U32*)pData) = TSP_PVR_IF_NUM;
1497 break;
1498 case HAL_TSP_CAP_PVR_FILTER_NUM:
1499 *((MS_U32*)pData) = TSP_PIDFLT1_NUM;
1500 break;
1501 case HAL_TSP_CAP_MMFI_AUDIO_FILTER_NUM:
1502 *((MS_U32*)pData) = TSP_MMFI_AUDIO_FILTER_NUM;
1503 break;
1504 case HAL_TSP_CAP_MMFI_V3D_FILTER_NUM:
1505 *((MS_U32*)pData) = TSP_MMFI_V3D_FILTER_NUM;
1506 break;
1507 case HAL_TSP_CAP_TSIF_NUM:
1508 *((MS_U32*)pData) = TSP_IF_NUM;
1509 break;
1510 case HAL_TSP_CAP_DEMOD_NUM:
1511 *((MS_U32*)pData) = TSP_DEMOD_NUM;
1512 break;
1513 case HAL_TSP_CAP_VFIFO_NUM:
1514 *((MS_U32*)pData) = TSP_VFIFO_NUM;
1515 break;
1516 case HAL_TSP_CAP_AFIFO_NUM:
1517 *((MS_U32*)pData) = TSP_AFIFO_NUM;
1518 break;
1519 case HAL_TSP_CAP_TS_PAD_NUM:
1520 *((MS_U32*)pData) = TSP_TS_PAD_NUM;
1521 break;
1522 case HAL_TSP_CAP_VQ_NUM:
1523 *((MS_U32*)pData) = TSP_VQ_NUM;
1524 break;
1525 case HAL_TSP_CAP_CA_FLT_NUM:
1526 *((MS_U32*)pData) = TSP_CA_FLT_NUM;
1527 break;
1528 case HAL_TSP_CAP_CA_KEY_NUM:
1529 *((MS_U32*)pData) = TSP_CA_KEY_NUM;
1530 break;
1531 case HAL_TSP_CAP_FW_ALIGN:
1532 *((MS_U32*)pData) = (1L << (MIU_BUS+TSP_DNLD_ADDR_ALI_SHIFT));
1533 break;
1534 case HAL_TSP_CAP_VQ_ALIGN:
1535 case HAL_TSP_CAP_SEC_BUF_ALIGN:
1536 case HAL_TSP_CAP_PVR_ALIGN:
1537 *((MS_U32*)pData) = (1L << MIU_BUS);
1538 break;
1539 case HAL_TSP_CAP_VQ_PITCH:
1540 *((MS_U32*)pData) = VQ_PACKET_UNIT_LEN;
1541 break;
1542 case HAL_TSP_CAP_PVRCA_PATH_NUM:
1543 *((MS_U32*)pData) = 1;
1544 break;
1545 case HAL_TSP_CAP_PVRCA0_FLT_RANGE:
1546 *((MS_U32*)pData) = TSP_SECFLT_NUM;
1547 *((MS_U32*)pData + 1) = TSP_SECFLT_NUM + TSP_PIDFLT1_NUM - 1;
1548 break;
1549 case HAL_TSP_CAP_PVRCA1_FLT_RANGE:
1550 case HAL_TSP_CAP_PVR1_FILTER_NUM:
1551 case HAL_TSP_CAP_SHAREKEY_FLT_RANGE:
1552 *((MS_U32*)pData) = 0;
1553 break;
1554 case HAL_TSP_CAP_HW_TYPE:
1555 *((MS_U32*)pData) = 0x00001001;
1556 break;
1557
1558 case HAL_TSP_CAP_HWPCR_SUPPORT:
1559 *((MS_U32*)pData) = 0;
1560 break;
1561
1562 case HAL_TSP_CAP_HWWP_SET_NUM:
1563 *((MS_U32*)pData) = TSP_WP_SET_NUM;
1564 break;
1565
1566 case HAL_TSP_CAP_DSCMB_ENG_NUM:
1567 *((MS_U32*)pData) = 1;
1568 break;
1569 case HAL_TSP_CAP_MAX_SEC_FLT_DEPTH:
1570 *((MS_U32*)pData) = TSP_SEC_FLT_DEPTH;
1571 break;
1572 case HAL_TSP_CAP_FW_BUF_SIZE:
1573 *((MS_U32*)pData) = TSP_FW_BUF_SIZE;
1574 break;
1575 case HAL_TSP_CAP_FW_BUF_RANGE:
1576 *((MS_U32*)pData) = TSP_FW_BUF_LOW_BUD;
1577 *((MS_U32*)pData+1) = TSP_FW_BUF_UP_BUD;
1578 break;
1579 case HAL_TSP_CAP_VQ_BUF_RANGE:
1580 *((MS_U32*)pData) = TSP_VQ_BUF_LOW_BUD;
1581 *((MS_U32*)pData+1) = TSP_VQ_BUF_UP_BUD;
1582 break;
1583 case HAL_TSP_CAP_SEC_BUF_RANGE:
1584 *((MS_U32*)pData) = TSP_SEC_BUF_LOW_BUD;
1585 *((MS_U32*)pData+1) = TSP_SEC_BUF_UP_BUD;
1586 break;
1587 case HAL_TSP_CAP_FIQ_NUM:
1588 *((MS_U32*)pData) = TSP_FIQ_NUM;
1589 break;
1590 default:
1591 *((MS_U32*)pData) = 0xFFFFFFFF;
1592 bRet = FALSE;
1593 break;
1594 }
1595 return bRet;
1596
1597 }
1598
HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable)1599 void HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable)
1600 {
1601 if(bEnable)
1602 {
1603 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1604 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | (TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV|TSP_DUP_PKT_SKIP_AD));
1605 }
1606 else
1607 {
1608 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1609 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~(TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV|TSP_DUP_PKT_SKIP_AD));
1610 }
1611 }
1612
HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId,MS_BOOL bEnable)1613 void HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId, MS_BOOL bEnable)
1614 {
1615 MS_U32 u32Flag[4] = {TSP_DUP_PKT_SKIP_VD, TSP_DUP_PKT_SKIP_AV, TSP_DUP_PKT_SKIP_AD, TSP_DUP_PKT_SKIP_V3D};
1616
1617 if(bEnable)
1618 {
1619 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1620 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | u32Flag[u32StreamId]);
1621 }
1622 else
1623 {
1624 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1625 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~u32Flag[u32StreamId]);
1626 }
1627 }
1628
HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId,MS_U16 * pu16Pad,MS_U16 * pu16Clk,MS_BOOL * pbExtSync,MS_BOOL * pbParl)1629 MS_BOOL HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId, MS_U16* pu16Pad, MS_U16* pu16Clk, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
1630 {
1631 MS_U16 u16pad;
1632 MS_U32 u32data;
1633
1634 *pu16Pad = 0xFFFF;
1635 *pu16Clk = TSP_CLK_DISABLE;
1636 *pbExtSync = FALSE;
1637 *pbParl = FALSE;
1638
1639 u16pad = TSP_TOP_REG(REG_TOP_TSN_MUX);
1640
1641 switch(u8TsIfId)
1642 {
1643 case 0:
1644 u16pad >>= REG_TOP_TSN_MUX_TS0_SHIFT;
1645 *pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK;
1646 u32data = _HAL_REG32_R(&_TspCtrl[0].Hw_Config0);
1647 *pbExtSync = ((u32data & TSP_HW_CFG0_TSIF0_EXTSYNC) == TSP_HW_CFG0_TSIF0_EXTSYNC);
1648 *pbParl = ((u32data & TSP_HW_CFG0_TSIF0_PARL) == TSP_HW_CFG0_TSIF0_PARL);
1649 break;
1650 case 1:
1651 u16pad >>= REG_TOP_TSN_MUX_TS1_SHIFT;
1652 *pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK;
1653 u32data = _HAL_REG32_R(&_TspCtrl[0].Hw_Config2);
1654 *pbExtSync = ((u32data & TSP_HW_CFG2_TSIF1_EXTSYNC) == TSP_HW_CFG2_TSIF1_EXTSYNC);
1655 *pbParl = ((u32data & TSP_HW_CFG2_TSIF1_PARL) == TSP_HW_CFG2_TSIF1_PARL);
1656 break;
1657 default:
1658 return FALSE;
1659 }
1660
1661 *pu16Pad = u16pad & REG_TOP_TSN_MUX_MASK;
1662
1663 return TRUE;
1664 }
1665
HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId)1666 MS_BOOL HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId)
1667 {
1668 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].Idr_Read1);
1669
1670 switch (u32StreamId)
1671 {
1672 case 0: // return VFifo status
1673 return ((u32data & TSP_VD_FIFO_OVERFLOW) == TSP_VD_FIFO_OVERFLOW);
1674 case 1: // return AFifo 0 status
1675 return ((u32data & TSP_AU_FIFO_OVERFLOW) == TSP_AU_FIFO_OVERFLOW);
1676 case 2: // return AFifo 1 status
1677 return ((u32data & TSP_AUB_FIFO_OVERFLOW) == TSP_AUB_FIFO_OVERFLOW);
1678 case 3: // return V3D Fifo status
1679 return ((u32data & TSP_V3D_FIFO_OVERFLOW) == TSP_V3D_FIFO_OVERFLOW);
1680 default:
1681 return FALSE;
1682 }
1683 }
1684
1685 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1686 // Macro function
1687 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
_HAL_TSP_FW_load(MS_PHY phyFwAddrPhys,MS_U32 u32FwSize,MS_BOOL bFwDMA,MS_BOOL bIQmem,MS_BOOL bDQmem)1688 static void _HAL_TSP_FW_load(
1689 MS_PHY phyFwAddrPhys,
1690 MS_U32 u32FwSize,
1691 MS_BOOL bFwDMA,
1692 MS_BOOL bIQmem,
1693 MS_BOOL bDQmem)
1694 {
1695 #define _TSP_QMEM_I_MASK 0xffff8000UL //total: 0x4000
1696 #define _TSP_QMEM_I_ADDR_HIT 0x00000000UL
1697 #define _TSP_QMEM_I_ADDR_MISS 0xffffffffUL
1698 #define _TSP_QMEM_D_MASK 0xffff8000UL
1699 #define _TSP_QMEM_D_ADDR_HIT 0x00000000UL
1700 #define _TSP_QMEM_D_ADDR_MISS 0xffffffffUL
1701 #define _TSP_QMEM_SIZE 0x1000UL // 16K bytes, 32bit aligment //0x4000
1702
1703 // bDQmem is always true
1704 MS_ASSERT(bDQmem);
1705
1706 _phyOrLoadMiuOffset = _HAL_TSP_MIU_OFFSET(phyFwAddrPhys);
1707
1708 _HAL_REG32_W(&_TspCtrl2[0].Qmem_Config,
1709 SET_FLAG1(_HAL_REG32_R(&_TspCtrl2[0].Qmem_Config), TSP_TSP_SEL_SRAM));
1710
1711 // @FIXME: Richard: Only allow TSP FW running in DRAM at this first stage.
1712 // improve this afterward.
1713 MS_ASSERT(phyFwAddrPhys & TSP_CPU_BASE_ADDR_MASK);
1714 _HAL_REG32_W(&_TspCtrl[0].Cpu_Base, 0/*u32FwAddrPhys >> 3*/); // 16 bytes address unit
1715
1716 if (bFwDMA)
1717 {
1718 MS_U32 u32DnldCtrl = 0;
1719 MS_U32 u32DnldCtrl1 = 0;
1720 u32DnldCtrl = (MS_U32)(((phyFwAddrPhys-_phyOrLoadMiuOffset) >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT) & TSP_DNLD_ADDR_MASK;
1721 u32DnldCtrl1 = (MS_U32)((((phyFwAddrPhys-_phyOrLoadMiuOffset) >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT) & TSP_DNLD_ADDR_MASK1) >> TSP_DNLD_ADDR_SHFT1;
1722 printf("firmware 111 0x%08lx 0x%08lx 0x%08lx\n", (unsigned long)phyFwAddrPhys, (unsigned long)u32DnldCtrl1, (unsigned long)u32DnldCtrl);
1723
1724 u32DnldCtrl |= (_TSP_QMEM_SIZE << TSP_DNLD_NUM_SHFT);
1725
1726 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl, u32DnldCtrl);
1727 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2, (_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2) & ~(TSP_DNLD_ADDR_MASK1 >> TSP_DNLD_ADDR_SHFT1)) | u32DnldCtrl1);
1728 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1729 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE));
1730 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1731 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START));
1732 while (!HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_DONE));//printf(".");
1733 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1734 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE));
1735 }
1736
1737 _HAL_REG32_W(&_TspCtrl[0].Qmem_Imask, _TSP_QMEM_I_MASK);
1738
1739 if (bIQmem)
1740 {
1741 _HAL_REG32_W(&_TspCtrl[0].Qmem_Ibase,
1742 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Qmem_Ibase), _TSP_QMEM_I_ADDR_HIT));
1743 }
1744 else
1745 {
1746 _HAL_REG32_W(&_TspCtrl[0].Qmem_Ibase, _TSP_QMEM_I_ADDR_MISS);
1747 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1748 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_ICACHE_EN));
1749 }
1750
1751 _HAL_REG32_W(&_TspCtrl[0].Qmem_Dmask,
1752 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Qmem_Dmask), _TSP_QMEM_D_MASK));
1753 _HAL_REG32_W(&_TspCtrl[0].Qmem_Dbase,
1754 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Qmem_Dbase), _TSP_QMEM_D_ADDR_HIT));
1755
1756 #undef _TSP_QMEM_I_MASK
1757 #undef _TSP_QMEM_I_ADDR_HIT
1758 #undef _TSP_QMEM_I_ADDR_MISS
1759 #undef _TSP_QMEM_D_MASK
1760 #undef _TSP_QMEM_D_ADDR_HIT
1761 #undef _TSP_QMEM_D_ADDR_MISS
1762 #undef _TSP_QMEM_SIZE
1763 }
1764
HAL_TSP_filein_enable(MS_BOOL b_enable)1765 void HAL_TSP_filein_enable(MS_BOOL b_enable)
1766 {
1767 // disable timeshift write protect -- it must enable while record/playback use the same buffer
1768 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1769 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP));
1770
1771 // Richard: enable/disable file in timer as well
1772 // file in could only walk through pid filter set 0.
1773 if (b_enable)
1774 {
1775 // Set Data port enable for audio bypass
1776 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1777 // SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1778 //_HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1779 // SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_ENABLE| TSP_CTRL1_FILEIN_TIMER_ENABLE));
1780
1781 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1782 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
1783 }
1784 else
1785 {
1786 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1787 // RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1788 //_HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1789 // RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_ENABLE| TSP_CTRL1_FILEIN_TIMER_ENABLE));
1790
1791 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1792 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
1793 }
1794 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1795 //RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1796 }
1797
_HAL_TSP_tsif_select(MS_U8 u8_tsif)1798 static void _HAL_TSP_tsif_select(MS_U8 u8_tsif)
1799 {
1800 if (u8_tsif == 1)
1801 {
1802 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1803 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1804 }
1805 else
1806 {
1807 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1808 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
1809 }
1810 }
1811
1812 /*
1813 static void _HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 PadId)
1814 {
1815 if (PadId) // TS1
1816 {
1817 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1818 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_PAD1_SEL));
1819 }
1820 else // TS0
1821 {
1822 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1823 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_PAD1_SEL));
1824 }
1825 }
1826 */
1827
HAL_TSP_PS_Path_Disable(void)1828 void HAL_TSP_PS_Path_Disable(void)
1829 {
1830 // set PS VID/AUD enable while video/audio/audio2 bypass mode
1831 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1832 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN|TSP_HW_CFG4_PS_AUD2_EN)));
1833 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1834 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1835 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1836 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1837 }
1838
HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl)1839 void HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl)
1840 {
1841 switch (u32TsDmaCtrl)
1842 {
1843 case TSP_TSDMA_CTRL_VPES0:
1844 if((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PS_VID_EN) == 0)
1845 {
1846 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1847 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_AUD_EN|TSP_HW_CFG4_PS_AUD2_EN));
1848 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1849 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1850
1851 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1852 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1853 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1854 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_VID_EN));
1855 }
1856 break;
1857 case TSP_TSDMA_CTRL_APES0:
1858 if((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PS_AUD_EN) == 0)
1859 {
1860 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1861 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD2_EN));
1862 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1863 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1864
1865 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1866 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1867 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1868 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_AUD_EN));
1869 }
1870 break;
1871 case TSP_TSDMA_CTRL_A2PES0:
1872 if((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PS_AUD2_EN) == 0)
1873 {
1874 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1875 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN)));
1876 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1877 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1878
1879 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1880 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1881 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1882 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_AUD2_EN));
1883 }
1884 break;
1885 case TSP_TSDMA_CTRL_V3DPES0:
1886 if((_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2) & TSP_PS_VID3D_EN) == 0)
1887 {
1888 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1889 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN)));
1890
1891 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1892 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1893 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1894 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1895 }
1896 break;
1897 default:
1898 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1899 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN|TSP_HW_CFG4_PS_AUD2_EN)));
1900 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1901 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1902 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1903 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1904 break;
1905 }
1906 }
1907
HAL_TSP_GetCtrlMode(MS_U32 u32EngId)1908 MS_U32 HAL_TSP_GetCtrlMode(MS_U32 u32EngId)
1909 {
1910 return (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl));
1911 }
1912
HAL_TSP_DoubleBuf_En(MS_BOOL bBuf_Sel)1913 void HAL_TSP_DoubleBuf_En(MS_BOOL bBuf_Sel)
1914 {
1915 if (bBuf_Sel)
1916 {
1917 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | (TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_DESC));
1918 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~TSP_DOUBLE_BUF_SWITCH);
1919 }
1920 else
1921 {
1922 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE));
1923 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | (TSP_DOUBLE_BUF_SWITCH|TSP_DOUBLE_BUF_DESC));
1924 }
1925 //_HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | TSP_DOUBLE_BUF_DESC);
1926 }
1927
HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId,MS_BOOL bFlush)1928 void HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId, MS_BOOL bFlush)
1929 {
1930 MS_U32 u32Flag;
1931
1932 switch(u32StreamId)
1933 {
1934 case 0:
1935 u32Flag = TSP_RESET_VFIFO;
1936 break;
1937 case 1:
1938 u32Flag = TSP_RESET_AFIFO;
1939 break;
1940 case 2:
1941 u32Flag = TSP_RESET_AFIFO2;
1942 break;
1943 case 3:
1944 u32Flag = TSP_RESET_VFIFO3D;
1945 break;
1946 default:
1947 return;
1948 }
1949 if (bFlush)
1950 {
1951 _HAL_REG32_W(&_TspCtrl[0].reg160C,
1952 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), u32Flag));
1953 }
1954 else
1955 {
1956 _HAL_REG32_W(&_TspCtrl[0].reg160C,
1957 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), u32Flag));
1958 }
1959 }
1960
1961 #define ADDR_AVFIFO_STATUS (_virtRegBase+ 0x2adc)
HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId)1962 MS_U32 HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId)
1963 {
1964 switch (u32StreamId)
1965 {
1966 case 0: // return VFifo status
1967 return (((REG16_T(ADDR_AVFIFO_STATUS))>>4)&0x0f);
1968 case 1: // return AFifo 0 status
1969 return (((REG16_T(ADDR_AVFIFO_STATUS))>>8)&0x0f);
1970 case 2: // return AFifo 1 status
1971 return (((REG16_T(ADDR_AVFIFO_STATUS))>>12)&0x0f);
1972 case 3: // return V3D Fifo status
1973 return (REG16_T(ADDR_AVFIFO_STATUS)&0x0f);
1974 default:
1975 return -1;
1976 }
1977 }
1978 #undef ADDR_AVFIFO_STATUS
1979
HAL_TSP_Ind_Enable(void)1980 void HAL_TSP_Ind_Enable(void)
1981 {
1982 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1983 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
1984 }
1985
HAL_TSP_HW_INT_STATUS(void)1986 MS_U32 HAL_TSP_HW_INT_STATUS(void)
1987 {
1988 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat) & TSP_HWINT_STATUS_MASK);
1989 }
1990
HAL_TSP_SetBank(MS_VIRT u32NonPmBankAddr,MS_VIRT u32PmBankAddr)1991 void HAL_TSP_SetBank(MS_VIRT u32NonPmBankAddr, MS_VIRT u32PmBankAddr)
1992 {
1993 _virtRegBase = u32NonPmBankAddr;
1994 _TspCtrl = (REG_Ctrl*)(_virtRegBase + REG_CTRL_BASE);
1995 _TspCtrl2 = (REG_Ctrl2*)(_virtRegBase + REG_CTRL_MMFIBASE);
1996 _TspCtrl3 = (REG_Ctrl3*)(_virtRegBase + REG_CTRL_BASE_TS3);
1997 }
1998
HAL_TSP_Reset(MS_U32 u32EngId)1999 void HAL_TSP_Reset(MS_U32 u32EngId)
2000 {
2001 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl, 0);
2002 }
2003
HAL_TSP_HwPatch(void)2004 void HAL_TSP_HwPatch(void)
2005 {
2006 _HAL_REG32_W(&_TspCtrl2[0].Qmem_Config,
2007 SET_FLAG1(_HAL_REG32_R(&_TspCtrl2[0].Qmem_Config), TSP_TSP_SEL_SRAM));
2008
2009 // To prevent the race condition of accessing section filter registers from HW/CPU.
2010 // It's a HW bug.
2011 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2012 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_ISYNC_PATCH_EN));
2013
2014 // Bad initial value of TSP_CTRL1
2015 // Suppose Standby mode for TSP should NOT be enabled.
2016 // Enabling TSP standby mode cause TSP section registers (SRAM in AEON) malfunction.
2017 // Disable it by SW at this stage.
2018 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2019 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_STANDBY));
2020
2021 // @FIXME: disable not match mask
2022 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2023 _HAL_REG32_R(&_TspCtrl[0].reg15b4)|TSP_NMATCH_DIS);
2024
2025 // Jericho helps
2026 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2027 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), 0xFFFF0000));
2028 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2029 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), 0xBBBB0000));
2030
2031 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2032 #ifdef VQ_ENABLE
2033 _HAL_REG32_R(&_TspCtrl[0].reg160C)| (TSP_RM_DMA_GLITCH|TSP_DOUBLE_BUF_DESC));
2034 #else
2035 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RM_DMA_GLITCH));
2036 #endif
2037
2038 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2039 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) |
2040 (TSP_SYSTIME_MODE_STC64|TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV));
2041
2042 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2043 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PREVENT_OVF_META));
2044
2045 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
2046 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), (TSP_STR2MI_WP_LD|TSP_RM_OVERFLOW_GLITCH))); //improve pvr performance
2047
2048
2049 // Set match PID, default is AV FIFO
2050 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2051 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_AVPID_ST_AV));
2052
2053 // Set PUSI 3 byte mode for Audio
2054 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
2055 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_PUSI_3BYTE_MODE));
2056
2057 // 2p sram setting
2058 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2059 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_HW_STANDBY_MODE));
2060
2061 // Set filein segment bit to 0
2062 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2063 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
2064
2065 _HAL_REG16_W(&_TspCtrl2[0].HwCfg1,
2066 SET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg1), (AF_PKT_LOSS_BYTE_ECO|UPDATE_SCRAMBLE_PID_PUSI|NEW_OVERFLOW_MODE|FIX_PINPON_SYNC_IN_ECO)));
2067
2068 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0, _HAL_REG16_R(&_TspCtrl2[0].HwCfg0) | (PREVENT_SRAM_COLLISION|MASK_SCR_VID_EN|MASK_SCR_VID_3D_EN|MASK_SCR_AUD_EN|MASK_SCR_AUDB_EN));
2069
2070 _HAL_REG16_W(&_TspCtrl2[0].HwCfg2, _HAL_REG16_R(&_TspCtrl2[0].HwCfg2) | REG_RST_CC_MODE);
2071
2072 _b64STCMode = TRUE;
2073
2074 //VQ parameters
2075 _HAL_REG16_W(&_TspCtrl3[0].Hw_Eco0, SET_FLAG1(_HAL_REG16_R(&_TspCtrl3[0].Hw_Eco0), TSP_FIXED_MIU_FLUSH));
2076 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, (_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL) & ~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK) | (0x0C << TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT));
2077 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, (_HAL_REG32_R(&_TspCtrl[0].VQ1_Config) & ~TSP_VQ1_FORCEFIRE_CNT_1K_MASK) | (0x0C << TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT));
2078 }
2079
HAL_TSP_DoubleBuf_Disable(void)2080 void HAL_TSP_DoubleBuf_Disable(void)
2081 {
2082
2083 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2084 #ifdef VQ_ENABLE
2085 _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_SWITCH));
2086 #else
2087 _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_SWITCH|TSP_DOUBLE_BUF_DESC));
2088 #endif
2089 }
2090
2091 // Default value of low bound is 0, default value of up bound is 0xFFFFFFFF, means no protection
2092 // If set both low bound and up bound to be 0, means protection all
2093 // The range can be written: phyStartAddr <= x <= phyEndAddr
2094 // Protection range: x > phyEndAddr && x < phyStartAddr
HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable,MS_PHY phyStartAddr,MS_PHY phyEndAddr)2095 void HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY phyStartAddr, MS_PHY phyEndAddr)
2096 {
2097 MS_U32 lbnd1_8;
2098 MS_U32 ubnd1_8;
2099 MS_U32 lbnd9_24;
2100 MS_U32 ubnd9_24;
2101 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(phyStartAddr);
2102
2103 if (bEnable)
2104 {
2105 if(phyStartAddr == phyEndAddr)
2106 phyStartAddr += (1UL << MIU_BUS);
2107 else
2108 phyEndAddr -= (1UL << MIU_BUS);
2109
2110 phyStartAddr -= phyMiuOffset;
2111 phyEndAddr -= phyMiuOffset;
2112
2113 lbnd1_8 = (MS_U32)((phyStartAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) & 0x00FFUL;
2114 lbnd9_24 = (MS_U32)(((phyStartAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) >> 8UL) & 0xFFFFUL;
2115 ubnd1_8 = (MS_U32)((phyEndAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) & 0x00FFUL;
2116 ubnd9_24 = (MS_U32)(((phyEndAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) >> 8UL) & 0xFFFFUL;
2117
2118 _HAL_REG32_W(&_TspCtrl[0].reg16C0, (_HAL_REG32_R(&_TspCtrl[0].reg16C0) & ~(TSP_ORZ_DMAW_LBND_LSB8)) | lbnd1_8);
2119 _HAL_REG32_W(&_TspCtrl[0].ORZ_DMAW, (_HAL_REG32_R(&_TspCtrl[0].ORZ_DMAW) & ~(TSP_ORZ_DMAW_LBND)) | lbnd9_24);
2120 _HAL_REG32_W(&_TspCtrl[0].reg16C0, (_HAL_REG32_R(&_TspCtrl[0].reg16C0) & ~(TSP_ORZ_DMAW_UBND_LSB8)) | (ubnd1_8 << TSP_ORZ_DMAW_UBND_LSB8_SHIFT));
2121 _HAL_REG32_W(&_TspCtrl[0].ORZ_DMAW, (_HAL_REG32_R(&_TspCtrl[0].ORZ_DMAW) & ~(TSP_ORZ_DMAW_UBND)) | (ubnd9_24 << TSP_ORZ_DMAW_UBND_SHIFT));
2122
2123 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | TSP_ORZ_DMAW_PROT_EN);
2124 }
2125 else
2126 {
2127 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~TSP_ORZ_DMAW_PROT_EN);
2128 }
2129 }
2130
2131 //--------------------------------------------------------------------------------------------------
2132 // For STC part
2133 //--------------------------------------------------------------------------------------------------
HAL_TSP_Stc_ctrl(MS_U32 u32EngId,MS_U32 u32Sync)2134 void HAL_TSP_Stc_ctrl(MS_U32 u32EngId, MS_U32 u32Sync)
2135 {
2136 /////////////Set STC control by HK////////////////
2137 // select synth from chip top : bit 1 -> 0 -> controlled by HK
2138 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
2139
2140 // set HK STC synth CW
2141 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2142 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (u32Sync & 0xFFFF);
2143 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (u32Sync >> 16) & 0xFFFF;
2144
2145 // set STC synth
2146 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2147 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
2148 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2149
2150 /////////////Set STC control by TSP////////////////
2151 // select synth from TSP : bit 1 -> 1 -> controlled by TSP
2152 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;
2153
2154 // set TSP STC synth CW
2155 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2156 HAL_REG32_IndW((REG32 *)(0x0021024c<<1), u32Sync);
2157
2158 // t2 , t3 had no 0x0021025c, it was add after t4, synthesizer enable
2159 HAL_REG32_IndW((REG32 *)(0x0021025c<<1), HAL_REG32_IndR((REG32 *)(0x0021025c<<1))| 0x01);
2160 HAL_REG32_IndW((REG32 *)(0x0021025c<<1), HAL_REG32_IndR((REG32 *)(0x0021025c<<1))& ~0x01);
2161 }
2162
HAL_TSP_STC_Update_Disable(MS_U32 u32EngId,MS_BOOL bDisable)2163 void HAL_TSP_STC_Update_Disable(MS_U32 u32EngId, MS_BOOL bDisable)
2164 {
2165 if(bDisable)
2166 {
2167 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2168 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_cnt_33b_ld));
2169 }
2170 else
2171 {
2172 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2173 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_cnt_33b_ld));
2174 }
2175 }
2176
HAL_TSP_GetSTC(MS_U32 u32EngId)2177 MS_U32 HAL_TSP_GetSTC(MS_U32 u32EngId)
2178 {
2179 if(_b64STCMode)
2180 {
2181 MS_U32 u32temp;
2182
2183 u32temp = (_HAL_REG32_R(&_TspCtrl[0].TsRec_Tail2_Pcr1) & TSP_PCR1_L16_MASK) >> TSP_PCR1_L16_SHFT;
2184 u32temp |= ((_HAL_REG32_R(&_TspCtrl[0].Pcr1) & 0xFFFF) << 16);
2185 return u32temp ;
2186 }
2187 else
2188 {
2189 return HAL_REG32_IndR((REG32 *)(0x00210244<< 1));
2190 }
2191 }
2192
HAL_TSP_GetSTC_32(MS_U32 u32EngId)2193 MS_U32 HAL_TSP_GetSTC_32(MS_U32 u32EngId)
2194 {
2195 if(_b64STCMode)
2196 {
2197 MS_U32 u32temp;
2198
2199 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr1) >> 16)& 0xFFFF;
2200 u32temp |= (((_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & TSP_PCR64_H16_MASK) & 0xFFFF) << 16);
2201 return u32temp ;
2202 }
2203 else
2204 {
2205 return (HAL_REG32_IndR((REG32 *)(0x00210248<< 1)) & 0x01);
2206 }
2207 }
2208
HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)2209 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)
2210 {
2211 if (bEnable)
2212 {
2213 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_SYSTIME_MODE_STC64);
2214 }
2215 else
2216 {
2217 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_SYSTIME_MODE_STC64);
2218 }
2219
2220 _b64STCMode = bEnable;
2221 }
2222
HAL_TSP_SetSTC(MS_U32 u32EngId,MS_U32 u32STC,MS_U32 u32STC_32)2223 void HAL_TSP_SetSTC(MS_U32 u32EngId, MS_U32 u32STC, MS_U32 u32STC_32)
2224 {
2225 if(_b64STCMode)
2226 {
2227 MS_U32 u32temp;
2228
2229 u32temp = ((u32STC & 0xFFFF) << TSP_PCR1_L16_SHFT) |
2230 (_HAL_REG32_R(&_TspCtrl[0].TsRec_Tail2_Pcr1) & ~TSP_PCR1_L16_MASK);
2231 _HAL_REG32_W(&_TspCtrl[0].TsRec_Tail2_Pcr1, u32temp);
2232
2233 u32temp = ((u32STC >> 16) & 0xFFFF) | ((u32STC_32 & 0xFFFF) << 16);
2234 _HAL_REG32_W(&_TspCtrl[0].Pcr1, u32temp);
2235
2236 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_PCR64_H16_MASK) | ((u32STC_32 >> 16) & TSP_PCR64_H16_MASK);
2237 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32temp);
2238 }
2239 else
2240 {
2241 HAL_REG32_IndW((REG32 *)(0x00210244<< 1), u32STC);
2242 HAL_REG32_IndW((REG32 *)(0x00210248<< 1), u32STC_32 & 0x01);
2243 }
2244 }
2245
HAL_TSP_SetSTCOffset(MS_U32 u32EngId,MS_U32 u32Offset,MS_BOOL bAdd)2246 MS_BOOL HAL_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd)
2247 {
2248 #if 0
2249 MS_U32 u32opt = ((MS_U32)bAdd & 0xFF) << TSP_MCU_CMD_SET_STC_OFFSET_OPTION_SHIFT;
2250
2251 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Offset);
2252 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_SET_STC_OFFSET | u32opt | u32EngId);
2253
2254 while(_HAL_REG32_R(&_TspCtrl[0].MCU_Cmd) != 0);
2255
2256 return TRUE;
2257
2258 #endif
2259
2260 return FALSE;
2261 }
2262
2263
2264 #if 0
2265 void HAL_TSP_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32)
2266 {
2267 if(_b64STCMode)
2268 {
2269 MS_U32 u32temp;
2270
2271 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr1) & ~ 0xFFFF0000) | ((u32STC_32 & 0xFFFF) << 16);
2272 _HAL_REG32_W(&_TspCtrl[0].Pcr1, u32temp);
2273 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_PCR64_H16_MASK) | ((u32STC_32 >> 16) & TSP_PCR64_H16_MASK);
2274 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32temp);
2275 }
2276 else
2277 {
2278 HAL_REG32_IndW((REG32 *)(0x00210248<< 1), u32STC_32 & 0x01);
2279 }
2280 }
2281 #endif
2282
HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId,MS_U32 u32STC)2283 void HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId, MS_U32 u32STC)
2284 {
2285 _HAL_REG32_W(&_TspCtrl[0].Pcr.ML, u32STC);
2286 }
2287
HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId,MS_U32 u32STC_32)2288 void HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32)
2289 {
2290 _HAL_REG32L_W(&_TspCtrl[0].Pcr.H32, u32STC_32 & 0x01);
2291 }
2292
HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId)2293 MS_U32 HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId)
2294 {
2295 return (_HAL_REG32_R(&_TspCtrl[0].Pcr.ML));
2296 }
2297
HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId)2298 MS_U32 HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId)
2299 {
2300 return (_HAL_REG32L_R(&_TspCtrl[0].Pcr.H32) & 0x01);
2301 }
2302
HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng,MS_U8 u8Opt)2303 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Opt)
2304 {
2305 MS_U32 i = 0;
2306 MS_U32 u32Enable = 0;
2307 MS_U32 u32Cmd = 0;
2308
2309 if(u8Opt & HAL_TSP_STC_UPDATE_HK)
2310 {
2311 u32Enable = 1;
2312 }
2313 if(u8Opt & HAL_TSP_STC_UPDATE_UPDATEONCE)
2314 {
2315 u32Cmd = TSP_MCU_CMD_CTRL_STC_UPDATE_ONCE;
2316 }
2317
2318 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Enable);
2319
2320 if (u8Eng == 0)
2321 {
2322 u32Cmd |= TSP_MCU_CMD_CTRL_STC_UPDATE;
2323 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32Cmd);
2324 }
2325 else
2326 {
2327 return FALSE;
2328 }
2329
2330 while (i< 4)
2331 {
2332 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2333 {
2334 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2335 return TRUE;
2336 }
2337 i++;
2338 _delay();
2339 }
2340 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2341 return FALSE;
2342 }
HAL_TSP_GetPcr(MS_U32 u32EngId,MS_U32 * pu32Pcr_32,MS_U32 * pu32Pcr)2343 MS_BOOL HAL_TSP_GetPcr(MS_U32 u32EngId, MS_U32 *pu32Pcr_32, MS_U32 *pu32Pcr)
2344 {
2345 MS_U32 i = 0;
2346
2347 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2348 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2349 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_PCR_GET);
2350 while (i< 4)
2351 {
2352 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2353 {
2354 *pu32Pcr = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2355 *pu32Pcr_32 = _HAL_REG32_R(&_TspCtrl[0].MCU_Data1);
2356 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2357 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2358 return ((0!= *pu32Pcr) || (0!= *pu32Pcr_32))? TRUE: FALSE;
2359 }
2360 i++;
2361 _delay();
2362 }
2363 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2364 return FALSE;
2365 }
2366
HAL_TSP_CmdQ_IsEmpty(void)2367 MS_BOOL HAL_TSP_CmdQ_IsEmpty(void)
2368 {
2369 if (_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_EMPTY)
2370 {
2371 return TRUE;
2372 }
2373 return FALSE;
2374 }
2375
HAL_TSP_Int_Disable(MS_U32 u32Mask)2376 void HAL_TSP_Int_Disable(MS_U32 u32Mask)
2377 {
2378 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2379 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)(u32Mask>>8)));
2380 }
2381
HAL_TSP_Int_Enable(MS_U32 u32Mask)2382 void HAL_TSP_Int_Enable(MS_U32 u32Mask)
2383 {
2384 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2385 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)(u32Mask>>8)));
2386 }
2387
HAL_TSP_Int_ClearSw(void)2388 void HAL_TSP_Int_ClearSw(void)
2389 {
2390 if (_bIsHK)
2391 {
2392 _HAL_REG32_W(&_TspCtrl[0].SwInt_Stat, 0);
2393 }
2394 else
2395 {
2396 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_M, 0);
2397 _HAL_REG32_W(&_TspCtrl[0].SwInt_Stat1_H,
2398 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].SwInt_Stat1_H), TSP_SWINT1_H_MASK));
2399 }
2400 }
2401
HAL_TSP_Int_ClearHw(MS_U32 u32Mask)2402 void HAL_TSP_Int_ClearHw(MS_U32 u32Mask)
2403 {
2404 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2405 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)u32Mask));
2406 }
2407
HAL_TSP_CmdQ_CmdCount(void)2408 MS_U32 HAL_TSP_CmdQ_CmdCount(void)
2409 {
2410 return (((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_CNT_MASK)>>TSP_CMDQ_CNT_SHFT));
2411 }
2412
HAL_TSP_CmdQ_TsDma_Reset(void)2413 void HAL_TSP_CmdQ_TsDma_Reset(void)
2414 {
2415 _HAL_REG32_W(&_TspCtrl[0].TsDma_Ctrl_CmdQ, 0);
2416 }
2417
HAL_TSP_CmdQ_Reset(void)2418 MS_BOOL HAL_TSP_CmdQ_Reset(void)
2419 {
2420 int ii = 0;
2421 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2422 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_CMDQ_RESET));
2423 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2424 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_CMDQ_RESET));
2425
2426 //reset the last data that hw is excuting --> HW new design
2427 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0,
2428 SET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg0), TSP_TSIFCFG_WB_FSM_RESET));
2429
2430 //check R done
2431 for(ii = 0; ii < 100; ii++)
2432 {
2433 if(_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_TSDMA_RDONE)
2434 {
2435 break;
2436 }
2437 MsOS_DelayTask(1);
2438 }
2439
2440 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0,
2441 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg0), TSP_TSIFCFG_WB_FSM_RESET));
2442
2443 if(ii == 100)
2444 {
2445 printf("%s, wait fine in reset timeout\n", __FUNCTION__);
2446 return FALSE;
2447 }
2448
2449 return TRUE;
2450 }
2451
HAL_TSP_WbDmaEnable(MS_BOOL bEnable)2452 void HAL_TSP_WbDmaEnable(MS_BOOL bEnable)
2453 {
2454 if (bEnable)
2455 {
2456 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2457 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2458 }
2459 else
2460 {
2461 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2462 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2463 }
2464 }
2465
2466 // u32TSSrc: 0 -> TS0, 1 -> File
2467 // u32GroupId: 0 -> filter0~filter31
HAL_TSP_Scmb_Status(MS_U32 u32TSSrc,MS_U32 u32GroupId,MS_U32 u32PidFltId)2468 MS_U32 HAL_TSP_Scmb_Status(MS_U32 u32TSSrc, MS_U32 u32GroupId, MS_U32 u32PidFltId)
2469 {
2470 MS_U32 u32PIDFltMask = u32PidFltId;
2471 MS_U32 u32ScmbSts = 0;
2472
2473 if(u32PidFltId != 0xFFFFFFFF)
2474 {
2475 u32PIDFltMask = (1 << (u32PidFltId & 0x1F));
2476 }
2477
2478 if (u32TSSrc == 0)
2479 {
2480 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2481 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld));
2482
2483 u32ScmbSts = HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsPidScmbStatTsin), u32PIDFltMask);
2484
2485 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2486 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld));
2487 }
2488 else
2489 {
2490 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2491 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_fi_ld));
2492
2493 u32ScmbSts = HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsPidScmbStatFile), u32PIDFltMask);
2494
2495 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2496 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_fi_ld));
2497 }
2498
2499 if(u32PIDFltMask != 0xFFFFFFFF)
2500 {
2501 u32ScmbSts = ((u32ScmbSts > 0) ? 1: 0);
2502 }
2503
2504 return u32ScmbSts;
2505
2506 }
2507 #if 0
2508 void HAL_TSP_CPU_SetBase(MS_U32 u32Addr, MS_U32 u32Size)
2509 {
2510 #if (!LINUX_TEST)
2511 // TSP FW running in QMEM
2512 _HAL_TSP_FW_load(u32Addr, u32Size, TRUE, TRUE, TRUE);
2513 #else
2514 // only for linux
2515 // @FIXME: abstract this later
2516 void* pBuf = NULL;
2517 MS_U32 u32PhysAddr = 0;
2518
2519 #if 0
2520 if (NULL == (pBuf = MsOS_AllocateMemory (u32Size, gs32NonCachedPoolID)))
2521 {
2522 MS_ASSERT(0);
2523 }
2524
2525 memcpy(pBuf, (void*)u32Addr, u32Size);
2526 u32PhysAddr = (MS_U32)VA2PA(pBuf);
2527 printf("firmware 0x%08x 0x%08x\n", (MS_U32)pBuf, u32Addr);
2528 _HAL_TSP_FW_load(u32PhysAddr, u32Size, TRUE, TRUE, TRUE);
2529 MsOS_FreeMemory(pBuf, gs32NonCachedPoolID);
2530 #else
2531 if (NULL == (pBuf = MsOS_AllocateMemory (72*1024*1024, gs32NonCachedPoolID)))
2532 {
2533 MS_ASSERT(0);
2534 }
2535 u32PhysAddr = 60*1024*1024;
2536 memcpy(PA2KSEG1(u32PhysAddr), (void*)u32Addr, u32Size);
2537 printf("firmware 0x%08x 0x%08x\n", (MS_U32)PA2KSEG1(u32PhysAddr), u32PhysAddr);
2538 _HAL_TSP_FW_load(u32PhysAddr, u32Size, TRUE, TRUE, TRUE);
2539 MsOS_FreeMemory(pBuf, gs32NonCachedPoolID);
2540 #endif
2541 #endif
2542 }
2543 #else
HAL_TSP_CPU_SetBase(MS_PHY phyAddr,MS_U32 u32Size)2544 void HAL_TSP_CPU_SetBase(MS_PHY phyAddr, MS_U32 u32Size)
2545 {
2546 printf("[%s][%d] load firmware (address, size) = (0x%08lx, 0x%08lx)\n", __FUNCTION__, __LINE__, (unsigned long)phyAddr, (unsigned long)u32Size);
2547 _HAL_TSP_FW_load(phyAddr, u32Size, TRUE, TRUE, TRUE);
2548 }
2549
2550 #endif // #if 0
2551
HAL_TSP_Alive(void)2552 MS_BOOL HAL_TSP_Alive(void)
2553 {
2554 MS_U32 i = 0;
2555 MS_U32 u32Data;
2556
2557 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2558 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_ALIVE);
2559 while (i< 4)
2560 {
2561 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2562 {
2563 u32Data = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2564 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2565 return (TSP_MCU_DATA_ALIVE == u32Data)? TRUE: FALSE;
2566 }
2567 i++;
2568 _delay();
2569 }
2570 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2571 return FALSE;
2572 }
2573
HAL_TSP_SetOwner(REG_SecFlt * pSecFilter,MS_BOOL bOwner)2574 void HAL_TSP_SetOwner(REG_SecFlt* pSecFilter, MS_BOOL bOwner)
2575 {
2576 MS_U32 u32HkId;
2577
2578 if (_bIsHK)
2579 {
2580 u32HkId = (bOwner)? 0: 1;
2581 }
2582 else
2583 {
2584 u32HkId = (bOwner)? 1: 0;
2585 }
2586 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_OWNER_MASK) |
2587 ((u32HkId << TSP_SECFLT_OWNER_SHFT) & TSP_SECFLT_OWNER_MASK));
2588 }
2589
HAL_TSP_FileIn_Set(MS_BOOL bset)2590 void HAL_TSP_FileIn_Set(MS_BOOL bset)
2591 {
2592 if (bset)
2593 {
2594 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2595 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_FILEIN192_EN));
2596 }
2597 else
2598 {
2599 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2600 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_FILEIN192_EN));
2601 }
2602 }
2603
HAL_TSP_ResetTimeStamp(void)2604 void HAL_TSP_ResetTimeStamp(void)
2605 {
2606 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2607 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2608 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2609 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2610 }
2611
HAL_TSP_GetPVRTimeStamp(void)2612 MS_U32 HAL_TSP_GetPVRTimeStamp(void)
2613 {
2614 MS_U32 u32lpcr;
2615
2616 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2617 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_RLD));
2618 u32lpcr = _HAL_REG32_R(&_TspCtrl[0].LPcr1);
2619 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2620 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_RLD));
2621
2622 return u32lpcr;
2623 }
2624
HAL_TSP_SetPVRTimeStamp(MS_U32 u32Stamp)2625 void HAL_TSP_SetPVRTimeStamp(MS_U32 u32Stamp)
2626 {
2627 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2628 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_WLD));
2629 _HAL_REG32_W(&_TspCtrl[0].LPcr1,u32Stamp);
2630 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2631 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_WLD));
2632 }
2633
HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId,MS_U32 u32ClkSrc)2634 MS_BOOL HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId, MS_U32 u32ClkSrc)
2635 {
2636 if(u32ClkSrc == 0x0) // 90K
2637 {
2638 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2639 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PVR1_CLK_STAMP_27_EN));
2640 }
2641 else // 27M
2642 {
2643 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2644 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PVR1_CLK_STAMP_27_EN));
2645 }
2646 return TRUE;
2647 }
2648
HAL_TSP_GetPlayBackTimeStamp(void)2649 MS_U32 HAL_TSP_GetPlayBackTimeStamp(void)
2650 {
2651 MS_U32 u32lpcr;
2652
2653 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2654 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_RLD));
2655 u32lpcr = _HAL_REG32_R(&_TspCtrl[0].LPcr2);
2656 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2657 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_RLD));
2658
2659 return u32lpcr;
2660 }
2661
HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp)2662 void HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp)
2663 {
2664 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2665 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_WLD));
2666 _HAL_REG32_W(&_TspCtrl[0].LPcr2,u32Stamp);
2667 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2668 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_WLD));
2669 }
2670
HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id,MS_U32 u32ClkSrc)2671 MS_BOOL HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id, MS_U32 u32ClkSrc)
2672 {
2673 if(u32ClkSrc == 0x0) // 90K
2674 {
2675 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2676 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_TSIF0_CLK_STAMP_27_EN));
2677 }
2678 else // 27M
2679 {
2680 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2681 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_TSIF0_CLK_STAMP_27_EN));
2682 }
2683 return TRUE;
2684 }
2685
HAL_TSP_GetFileInTimeStamp(void)2686 MS_U32 HAL_TSP_GetFileInTimeStamp(void)
2687 {
2688 return _HAL_REG32_R(&_TspCtrl[0].TimeStamp_FileIn);
2689 }
2690
HAL_TSP_GetFilinReadAddr(MS_PHY * pphyReadAddr)2691 MS_BOOL HAL_TSP_GetFilinReadAddr(MS_PHY* pphyReadAddr)
2692 {
2693 *pphyReadAddr = ((MS_PHY)_HAL_REG32_R(&_TspCtrl[0].TsFileIn_RPtr) << MIU_BUS) + _phyFIBufMiuOffset;
2694
2695 return TRUE;
2696 }
2697
HAL_TSP_SetDMABurstLen(MS_U32 u32Len)2698 void HAL_TSP_SetDMABurstLen(MS_U32 u32Len)
2699 {
2700 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2701 _HAL_REG32_R(&_TspCtrl[0].Hw_Config4) | ((u32Len<<TSP_HW_DMA_MODE_SHIFT)&TSP_HW_DMA_MODE_MASK));
2702 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2703 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_SEC_DMA_BURST_EN));
2704 }
2705
HAL_TSP_PVR_PacketMode(MS_BOOL bSet)2706 void HAL_TSP_PVR_PacketMode(MS_BOOL bSet)
2707 {
2708 if (bSet)
2709 {
2710 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2711 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RECORD192_EN));
2712 }
2713 else
2714 {
2715 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2716 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RECORD192_EN));
2717 }
2718 }
2719
HAL_ResetAll(void)2720 void HAL_ResetAll(void)
2721 {
2722 printf("Reset ALL registers\n");
2723 //_HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2724 // SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_CPU_EN));
2725 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2726 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2727 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2728 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2729 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2730 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
2731
2732 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2733 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2734 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2735 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2736 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2737 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
2738 }
2739
2740
2741 #define CKG_TS0_TS1 0x16A0UL //0x28
2742 #define CLK_TS0_DISABLE 0x0001UL
2743 #define CLK_TS0_INVERT 0x0002UL
2744 #define CLK_TS0_CLK_MASK 0x001CUL
2745 #define CLK_TS1_DISABLE 0x0100UL
2746 #define CLK_TS1_INVERT 0x0200UL
2747 #define CLK_TS1_CLK_MASK 0x1C00UL
2748 #define CKG_TSP_STC0 0x16A8UL //0x2a
2749 #define CLK_TSP_DISABLE 0x0001UL
2750 #define CLK_TSP_INVERT 0x0002UL
2751 #define CLK_TSP_CLK_MASK 0x000CUL
2752 #define CLK_PAR_DISABLE 0x0010UL
2753 #define CLK_PAR_INVERT 0x0020UL
2754 #define CLK_PAR_CLK_MASK 0x0040UL
2755 #define CLK_STC_DISABLE 0x0100UL
2756 #define CLK_STC_INVERT 0x0200UL
2757 #define CLK_STC_CLK_MASK 0x0C00UL
2758 #define CKG_TSP_STAMP 0x16ACUL //0x2b
2759 #define CLK_SYN_STC0_MASK 0x0007UL
2760 #define CLK_SYN_STC0_432M 0x0001UL
2761 #define CLK_STAM_DISABLE 0x0100UL
2762 #define CLK_STAM_INVERT 0x0200UL
2763 #define CLK_STAM_CLK_MASK 0x0C00UL
2764 #define CKG2_TSP_TS_SAMPLE 0x1464UL //0x019
2765 #define CKG2_TSP_TS_SAMPLE_DISABLE 0x0010UL
2766 #define CKG2_TSP_TS_SAMPLE_INVERT 0x0020UL
2767 #define CKG2_TSP_TS_SAMPLE_CLK_MASK 0x00C0UL
2768 #define CHIP_TSP_BOOT_CLK_SEL 0x3D68 //0x5a
2769 #define CHIP_TSP_BOOT_CLK_SEL_MASK 0x0020
2770
HAL_TSP_PowerCtrl(MS_BOOL bOn)2771 void HAL_TSP_PowerCtrl(MS_BOOL bOn)
2772 {
2773 if (bOn)
2774 {
2775 //Set PE Pad
2776 //TSP_TOP_REG(REG_TOP_TS0_PE) |= REG_TOP_TS0_PE_MASK;
2777
2778 // Enable TSP Clock
2779 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2780 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_TSP_DISABLE|CLK_TSP_INVERT|CLK_TSP_CLK_MASK)));
2781
2782 // Enable CLK_PARSER clock
2783 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2784 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_DISABLE|CLK_PAR_INVERT|CLK_PAR_CLK_MASK)));
2785
2786 //TSP select SRAM
2787 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL)), CHIP_TSP_BOOT_CLK_SEL_MASK));
2788
2789 //Select SRAM
2790 _HAL_REG32_W(&(_TspCtrl2[0].Qmem_Config), SET_FLAG1(_HAL_REG32_R(&(_TspCtrl2[0].Qmem_Config)), TSP_TSP_SEL_SRAM));
2791
2792 // Enable TS0 clock
2793 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),
2794 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS0_DISABLE|CLK_TS0_INVERT|CLK_TS0_CLK_MASK)));
2795
2796 // Enable TS1 clock
2797 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),
2798 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS1_DISABLE|CLK_TS1_INVERT|CLK_TS1_CLK_MASK)));
2799
2800 // Set SYN_STC to be 432MHz
2801 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),
2802 SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), CLK_SYN_STC0_432M));
2803
2804 // Enable STC clock
2805 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2806 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_STC_DISABLE|CLK_STC_INVERT|CLK_STC_CLK_MASK)));
2807
2808 // Enable TIMESTAMP clock
2809 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),
2810 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INVERT|CLK_STAM_CLK_MASK)));
2811
2812 // Enable Sample clock
2813 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE),
2814 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), (CKG2_TSP_TS_SAMPLE_DISABLE|CKG2_TSP_TS_SAMPLE_INVERT|CKG2_TSP_TS_SAMPLE_CLK_MASK)));
2815
2816 }
2817 else
2818 {
2819 // Disable TSP clock
2820 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_TSP_DISABLE));
2821
2822 // Disable TS0 clock
2823 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), CLK_TS0_DISABLE));
2824
2825 // Disable TS1 clock
2826 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), CLK_TS1_DISABLE));
2827
2828 // Disable STC clock
2829 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_STC_DISABLE));
2830
2831 // Disable CLK_PARSER clock
2832 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_PAR_DISABLE));
2833
2834 // Disable TIMESTAMP clock
2835 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), CLK_STAM_DISABLE));
2836
2837 // Disable Sample clock
2838 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), CKG2_TSP_TS_SAMPLE_DISABLE));
2839
2840 //Reset PE Pad
2841 // ts0 pad is null
2842 if(_bTsPadUsed[1] == TRUE)
2843 {
2844 TSP_TOP_REG(REG_TOP_TS1_PE) &= ~REG_TOP_TS_PE_MASK;
2845 _bTsPadUsed[1] = FALSE;
2846 }
2847 if(_bTsPadUsed[2] == TRUE)
2848 {
2849 TSP_TOP_REG(REG_TOP_TS2_PE) &= ~REG_TOP_TS_PE_MASK;
2850 _bTsPadUsed[2] = FALSE;
2851 }
2852
2853 }
2854 }
2855
2856 #undef CKG_TS0_TS1
2857 #undef CLK_TS0_DISABLE
2858 #undef CLK_TS0_INVERT
2859 #undef CLK_TS0_CLK_MASK
2860 #undef CKG_TSP_STC0
2861 #undef CLK_TSP_DISABLE
2862 #undef CLK_TSP_INVERT
2863 #undef CLK_TSP_CLK_MASK
2864 #undef CLK_PAR_DISABLE
2865 #undef CLK_PAR_INVERT
2866 #undef CLK_PAR_CLK_MASK
2867 #undef CLK_STC_DISABLE
2868 #undef CLK_STC_INVERT
2869 #undef CLK_STC_CLK_MASK
2870 #undef CKG_TSP_STAMP
2871 #undef CLK_SYN_STC0_MASK
2872 #undef CLK_SYN_STC0_432M
2873 #undef CLK_STAM_DISABLE
2874 #undef CLK_STAM_INVERT
2875 #undef CLK_STAM_CLK_MASK
2876 #undef CKG2_TSP_TS_SAMPLE
2877 #undef CKG2_TSP_TS_SAMPLE_DISABLE
2878 #undef CKG2_TSP_TS_SAMPLE_INVERT
2879 #undef CKG2_TSP_TS_SAMPLE_CLK_MASK
2880 #undef CHIP_TSP_BOOT_CLK_SEL
2881 #undef CHIP_TSP_BOOT_CLK_SEL_MASK
2882
2883
HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel)2884 MS_U32 HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel)
2885 {
2886 _HAL_REG32_W(&_TspCtrl[0].PKT_CNT, TSP_DBG_SEL_MASK&(u32dbgsel<<TSP_DBG_SEL_SHIFT));
2887 return (_HAL_REG32_R(&_TspCtrl[0].TSP_Debug)&TSP_DEBUG_MASK);
2888 }
2889
HAL_TSP_Enable_ValidSync_Dectect(void)2890 void HAL_TSP_Enable_ValidSync_Dectect(void)
2891 {
2892 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2893 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_VALID_FALLING_DETECT));
2894 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2895 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_SYNC_RISING_DETECT));
2896 }
2897
HAL_Reset_WB(void)2898 void HAL_Reset_WB(void)
2899 {
2900 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2901 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2902 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2903 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2904 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2905 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2906 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2907 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2908 }
2909
HAL_TSP_Get_FW_VER(void)2910 MS_U32 HAL_TSP_Get_FW_VER(void)
2911 {
2912 MS_U32 i = 0;
2913 MS_U32 u32Data = 0;
2914
2915 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2916 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_VERSION_GET);
2917 while (i< 4)
2918 {
2919 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2920 {
2921 u32Data = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2922 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2923 return u32Data;
2924 }
2925 i++;
2926 _delay();
2927 }
2928 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2929 return u32Data;
2930 }
2931
HAL_TSP_Check_FW_VER(void)2932 MS_BOOL HAL_TSP_Check_FW_VER(void)
2933 {
2934 MS_U32 u32FWVer;
2935
2936 u32FWVer = HAL_TSP_Get_FW_VER();
2937 if((u32FWVer >> 16) != TSP_FW_DEVICE_ID)
2938 {
2939 printf("\nWarning: TSP FW not match!! FW version: 0x%08x\n\n", (unsigned int)u32FWVer);
2940 return FALSE;
2941 }
2942
2943 return TRUE;
2944 }
2945
HAL_TSP_SetFwDbgMem(MS_PHY phyAddr,MS_U32 u32Size)2946 MS_BOOL HAL_TSP_SetFwDbgMem(MS_PHY phyAddr, MS_U32 u32Size)
2947 {
2948 MS_U32 i = 0;
2949
2950 if(IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_SIZE) ||
2951 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE) ||
2952 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZE) ||
2953 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_QMEM_ADDR, OPENRISC_QMEM_ADDR + OPENRISC_QMEM_SIZE))
2954 {
2955 printf("[%s][%d] invalid physical address 0x%x\n", __FUNCTION__, __LINE__, (unsigned int)phyAddr);
2956 return FALSE;
2957 }
2958 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, phyAddr);
2959 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, u32Size);
2960 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DBG_MEM);
2961 while(i<4)
2962 {
2963 if(0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2964 {
2965 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2966 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2967 return TRUE;
2968 }
2969 i++;
2970 _delay();
2971 }
2972 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2973 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2974 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2975
2976 return FALSE;
2977 }
2978
HAL_TSP_SetFwDbgWord(MS_U32 u32Word)2979 MS_BOOL HAL_TSP_SetFwDbgWord(MS_U32 u32Word)
2980 {
2981 MS_U32 i = 0;
2982
2983 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Word);
2984 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DBG_WORD);
2985 while(i<4)
2986 {
2987 if(0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2988 {
2989 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2990 return TRUE;
2991 }
2992 i++;
2993 _delay();
2994 }
2995 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2996 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2997 return FALSE;
2998 }
2999
3000 //0: VQ0, 1: VQ_file
HAL_TSP_SetVQBuffer(MS_PHY phyBaseAddr,MS_U32 u32BufLen)3001 void HAL_TSP_SetVQBuffer(MS_PHY phyBaseAddr, MS_U32 u32BufLen)
3002 {
3003 MS_PHY phyAddr = phyBaseAddr;
3004 MS_U32 u32Size = 0, u32OneBufSize = 0, u32temp = 0;
3005 MS_PHY phyVqBufOffset = _HAL_TSP_MIU_OFFSET(phyBaseAddr);
3006
3007 u32OneBufSize = ((u32BufLen >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment
3008 u32Size = u32OneBufSize / TSP_VQ_PITCH;
3009
3010 _HAL_REG32_W(&(_TspCtrl[0].VQ0_BASE), (MS_U32)((phyAddr-phyVqBufOffset) >> MIU_BUS));
3011 u32temp = (u32Size << TSP_VQ0_SIZE_192PK_SHIFT) | (_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL) & ~TSP_VQ0_SIZE_192PK_MASK);
3012 _HAL_REG32_W(&(_TspCtrl[0].VQ0_CTRL), u32temp);
3013
3014 phyAddr += u32OneBufSize;
3015 _HAL_REG32_W(&(_TspCtrl[0].VQ1_Base), (MS_U32)((phyAddr-phyVqBufOffset) >> MIU_BUS));
3016 u32temp = (u32Size << TSP_VQ1_SIZE_192BYTE_SHIFT) | (_HAL_REG32_R(&_TspCtrl[0].VQ1_Size) & ~TSP_VQ1_SIZE_192BYTE_MASK);
3017 _HAL_REG32_W(&(_TspCtrl[0].VQ1_Size), u32temp);
3018 }
3019
HAL_TSP_VQueue_Enable(MS_BOOL bEnable)3020 void HAL_TSP_VQueue_Enable(MS_BOOL bEnable)
3021 {
3022 if (bEnable)
3023 {
3024 // Reset VQ before VQ enable.
3025 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3026 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3027
3028 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3029 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3030
3031 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3032 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS), (TSP_VQ0_EN|TSP_VQ_FILE_EN|TSP_VQ_PINGPONG_EN)));
3033 }
3034 else
3035 {
3036 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3037 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS), (TSP_VQ0_EN|TSP_VQ_FILE_EN|TSP_VQ_PINGPONG_EN)));
3038 }
3039
3040 }
3041
HAL_TSP_VQueue_Reset(void)3042 void HAL_TSP_VQueue_Reset(void)
3043 {
3044 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3045 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3046 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3047 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3048
3049 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3050 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3051 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3052 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3053 }
3054
HAL_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable)3055 void HAL_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable)
3056 {
3057 if (bEnable)
3058 {
3059 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3060 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_OVERFLOW_INT_EN));
3061 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3062 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_OVF_INT_EN));
3063
3064 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3065 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L)|0xFF00 , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8));
3066 }
3067 else
3068 {
3069 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3070 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_OVERFLOW_INT_EN));
3071 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3072 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_OVF_INT_EN));
3073
3074 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3075 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8));
3076 }
3077 }
3078
HAL_TSP_VQueue_Clr_OverflowInt(void)3079 void HAL_TSP_VQueue_Clr_OverflowInt(void)
3080 {
3081 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL);
3082
3083 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, u32data | TSP_VQ0_CLR_OVERFLOW_INT);
3084 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, u32data & ~TSP_VQ0_CLR_OVERFLOW_INT);
3085
3086 u32data = _HAL_REG32_R(&_TspCtrl[0].VQ1_Config);
3087 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, u32data | TSP_VQ1_CLR_OVF_INT);
3088 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, u32data & ~TSP_VQ1_CLR_OVF_INT);
3089
3090 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3091 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L), TSP_HWINT2_VQ_OVERFLOW_STATUS));
3092 }
3093
HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len)3094 void HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len)
3095 {
3096 MS_U32 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN1;
3097
3098 switch(u8req_len)
3099 {
3100 case 1:
3101 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN1;
3102 break;
3103 case 2:
3104 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN2;
3105 break;
3106 case 4:
3107 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN4;
3108 break;
3109 case 8:
3110 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN8;
3111 break;
3112 default:
3113 break;
3114 }
3115
3116 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3117 (_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value);
3118
3119
3120 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3121 (_HAL_REG32_R(&_TspCtrl[0].VQ1_Config) & ~TSP_VQ1_WR_THRESHOLD_MASK) | u32Value);
3122 }
3123
HAL_TSP_VQ_INT_STATUS(void)3124 MS_U32 HAL_TSP_VQ_INT_STATUS(void)
3125 {
3126 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_VQ_OVERFLOW_STATUS);
3127 }
3128
HAL_TSP_Get_VQStatus(void)3129 MS_U32 HAL_TSP_Get_VQStatus(void)
3130 {
3131 return (_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS) & TSP_VQ0_STATUS_MASK);
3132 }
3133
HAL_TSP_GetPidFltReg(MS_U32 u32EngId,MS_U32 u32PidFltId)3134 REG_PidFlt* HAL_TSP_GetPidFltReg(MS_U32 u32EngId, MS_U32 u32PidFltId)
3135 {
3136 return (&(_TspPid[u32EngId].Flt[u32PidFltId]));
3137 }
3138
HAL_TSP_Read_DropPktCnt(MS_U16 * pu16ADropCnt,MS_U16 * pu16VDropCnt)3139 MS_BOOL HAL_TSP_Read_DropPktCnt(MS_U16* pu16ADropCnt, MS_U16* pu16VDropCnt)
3140 {
3141 return FALSE;
3142 }
3143
HAL_TSP_TSIF0_Enable(MS_BOOL bEnable)3144 void HAL_TSP_TSIF0_Enable(MS_BOOL bEnable)
3145 {
3146 if (bEnable)
3147 {
3148 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3149 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
3150 }
3151 else
3152 {
3153 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3154 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
3155 }
3156 }
3157
HAL_TSP_TSIF1_Enable(MS_BOOL bEnable)3158 void HAL_TSP_TSIF1_Enable(MS_BOOL bEnable)
3159 {
3160 if (bEnable)
3161 {
3162 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3163 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
3164 }
3165 else
3166 {
3167 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3168 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
3169 }
3170 }
3171
3172 // (Section DMA + PVR) , total 5 set
3173 // Default value of low bound is 0, default value of up bound is 0xFFFFFFFF, means no protection
3174 // If set both low bound and up bound to be 0, means protection all
3175 // MIU bus is 4, Max MIU address is 512MB, should append 1 zero
3176 // The range can be written: u32StartAddr <= x < u32EndAddr
3177 // Protection range: x >= u32EndAddr && x < u32StartAddr
HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable,MS_PHY * pphyStartAddr,MS_PHY * pphyEndAddr)3178 void HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY* pphyStartAddr, MS_PHY* pphyEndAddr)
3179 {
3180 MS_U32 u32value;
3181 MS_U32 u32lbnd, u32ubnd;
3182
3183 if (bEnable)
3184 {
3185 if(pphyStartAddr[0] == pphyEndAddr[0])
3186 pphyEndAddr[0] += (1UL << MIU_BUS);
3187
3188 u32lbnd = (MS_U32)(((pphyStartAddr[0]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[0])) >> MIU_BUS) >> TSP_DMAW_BND_ALI_SHIFT) & TSP_DMAW_LBND_LSB8;
3189 u32ubnd = (MS_U32)((((pphyEndAddr[0]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[0])) >> MIU_BUS) >> TSP_DMAW_BND_ALI_SHIFT) & TSP_DMAW_LBND_LSB8) << TSP_DMAW_UBND_LSB8_SHIFT;
3190 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16C4) & ~(TSP_DMAW_LBND_LSB8|TSP_DMAW_UBND_LSB8));
3191 _HAL_REG32_W(&_TspCtrl[0].reg16C4, u32value);
3192 u32lbnd = (MS_U32)(((pphyStartAddr[0]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[0])) >> MIU_BUS) >> TSP_DMAWP_BND_ALI_SHIFT) & TSP_DMAWP_LBND_MASK;
3193 u32ubnd = (MS_U32)((((pphyEndAddr[0]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[0])) >> MIU_BUS) >> TSP_DMAWP_BND_ALI_SHIFT) & TSP_DMAWP_HBND_MASK) << TSP_DMAWP_HBND_SHFT;
3194 u32value = u32lbnd + u32ubnd;
3195 _HAL_REG32_W(&_TspCtrl[0].TSP_DMAWP_BND, u32value);
3196
3197 if(pphyStartAddr[1] == pphyEndAddr[1])
3198 pphyStartAddr[1] += (1UL << MIU_BUS);
3199
3200 u32lbnd = (MS_U32)(((pphyStartAddr[1]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[1])) >> MIU_BUS) >> TSP_DMAW1_BND_ALI_SHIFT) & TSP_DMAW1_LBND_LSB8;
3201 u32ubnd = (MS_U32)((((pphyEndAddr[1]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[1])) >> MIU_BUS) >> TSP_DMAW1_BND_ALI_SHIFT) & TSP_DMAW1_LBND_LSB8) << TSP_DMAW1_UBND_LSB8_SHIFT;
3202 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16C8) & ~(TSP_DMAW1_LBND_LSB8|TSP_DMAW1_UBND_LSB8));
3203 _HAL_REG32_W(&_TspCtrl[0].reg16C8, u32value);
3204 u32lbnd = (MS_U32)(((pphyStartAddr[1]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[1])) >> MIU_BUS) >> TSP_DMAW1_ALI_SHIFT) & TSP_DMAW1_LBND_MASK1;
3205 u32ubnd = (MS_U32)((((pphyEndAddr[1]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[1])) >> MIU_BUS) >> TSP_DMAW1_ALI_SHIFT) & TSP_DMAW1_UBND_MASK1) << TSP_DMAW1_UBND_SHIFT1;
3206 u32value = u32lbnd + u32ubnd;
3207 _HAL_REG32_W(&_TspCtrl[0].DMAW1_1, u32value);
3208
3209 if(pphyStartAddr[2] == pphyEndAddr[2])
3210 pphyStartAddr[2] += (1UL << MIU_BUS);
3211
3212 u32lbnd = (MS_U32)(((pphyStartAddr[2]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[2])) >> MIU_BUS) >> TSP_DMAW2_BND_ALI_SHIFT) & TSP_DMAW2_LBND_LSB8;
3213 u32ubnd = (MS_U32)((((pphyEndAddr[2]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[2])) >> MIU_BUS) >> TSP_DMAW2_BND_ALI_SHIFT) & TSP_DMAW2_LBND_LSB8) << TSP_DMAW2_UBND_LSB8_SHIFT;
3214 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16CC) & ~(TSP_DMAW2_LBND_LSB8|TSP_DMAW2_UBND_LSB8));
3215 _HAL_REG32_W(&_TspCtrl[0].reg16CC, u32value);
3216 u32lbnd = (MS_U32)(((pphyStartAddr[2]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[2])) >> MIU_BUS) >> TSP_DMAW2_ALI_SHIFT) & TSP_DMAW2_LBND_MASK1;
3217 u32ubnd = (MS_U32)((((pphyEndAddr[2]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[2])) >> MIU_BUS) >> TSP_DMAW2_ALI_SHIFT) & TSP_DMAW2_UBND_MASK1) << TSP_DMAW2_UBND_SHIFT1;
3218 u32value = u32lbnd + u32ubnd;
3219 _HAL_REG32_W(&_TspCtrl[0].DMAW2_1, u32value);
3220
3221 if(pphyStartAddr[3] == pphyEndAddr[3])
3222 pphyStartAddr[3] += (1UL << MIU_BUS);
3223
3224 u32lbnd = (MS_U32)(((pphyStartAddr[3]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[3])) >> MIU_BUS) >> TSP_DMAW3_BND_ALI_SHIFT) & TSP_DMAW3_LBND_MASK;
3225 u32ubnd = (MS_U32)(((pphyEndAddr[3]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[3])) >> MIU_BUS) >> TSP_DMAW3_BND_ALI_SHIFT) & TSP_DMAW3_UBND_MASK;
3226 _HAL_REG32_W(&_TspCtrl[0].DMAW3_LBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW3_LBND) & ~TSP_DMAW3_LBND_MASK) | u32lbnd);
3227 _HAL_REG32_W(&_TspCtrl[0].DMAW3_UBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW3_UBND) & ~TSP_DMAW3_UBND_MASK) | u32ubnd);
3228
3229 if(pphyStartAddr[4] == pphyEndAddr[4])
3230 pphyStartAddr[4] += (1UL << MIU_BUS);
3231
3232 u32lbnd = (MS_U32)(((pphyStartAddr[4]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[4])) >> MIU_BUS) >> TSP_DMAW4_BND_ALI_SHIFT) & TSP_DMAW4_LBND_MASK;
3233 u32ubnd = (MS_U32)(((pphyEndAddr[4]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[4])) >> MIU_BUS) >> TSP_DMAW4_BND_ALI_SHIFT) & TSP_DMAW4_UBND_MASK;
3234 _HAL_REG32_W(&_TspCtrl[0].DMAW4_LBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW4_LBND) & ~TSP_DMAW4_LBND_MASK) | u32lbnd);
3235 _HAL_REG32_W(&_TspCtrl[0].DMAW4_UBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW4_UBND) & ~TSP_DMAW4_UBND_MASK) | u32ubnd);
3236
3237 _HAL_REG32_W(&_TspCtrl[0].reg15b4, _HAL_REG32_R(&_TspCtrl[0].reg15b4) | TSP_DMAW_PROTECT_EN);
3238 }
3239 else
3240 {
3241 _HAL_REG32_W(&_TspCtrl[0].reg15b4, _HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_DMAW_PROTECT_EN);
3242 }
3243 }
3244
HAL_TSP_MOBF_Set_PVRKey(MS_U32 u32Key0,MS_U32 u32Key1)3245 MS_BOOL HAL_TSP_MOBF_Set_PVRKey(MS_U32 u32Key0, MS_U32 u32Key1)
3246 {
3247 _HAL_REG32_W(&_TspCtrl[0].MOBF_PVR_KEY, (_HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_MOBF_PVR_KEY0_MASK) | ((u32Key0 << TSP_MOBF_PVR_KEY0_SHIFT) & TSP_MOBF_PVR_KEY0_MASK));
3248 _HAL_REG32_W(&_TspCtrl[0].MOBF_PVR_KEY, (_HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_MOBF_PVR_KEY1_MASK) | ((u32Key0 << TSP_MOBF_PVR_KEY1_SHIFT) & TSP_MOBF_PVR_KEY1_MASK));
3249 return TRUE;
3250 }
3251
HAL_TSP_MOBF_Set_FileinKey(MS_U32 u32Key)3252 MS_BOOL HAL_TSP_MOBF_Set_FileinKey(MS_U32 u32Key)
3253 {
3254 MS_U32 u32Data = 0;
3255
3256 u32Data = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_MOBF_FILE_KEY0_L_MASK) |
3257 ((u32Key << TSP_MOBF_FILE_KEY0_L_SHIFT) & TSP_MOBF_FILE_KEY0_L_MASK);
3258 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32Data);
3259 return TRUE;
3260 }
3261
HAL_TSP_MOBF_Filein_Enable(MS_BOOL bEnable)3262 MS_BOOL HAL_TSP_MOBF_Filein_Enable(MS_BOOL bEnable)
3263 {
3264 return FALSE;
3265 }
3266
HAL_TSP_MOBF_PVR_Enable(MS_BOOL bEnable)3267 MS_BOOL HAL_TSP_MOBF_PVR_Enable(MS_BOOL bEnable)
3268 {
3269 return FALSE;
3270 }
3271
HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable)3272 MS_BOOL HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable)
3273 {
3274 if (bEnable)
3275 {
3276 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3277 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_BD_AUDIO_EN));
3278 }
3279 else
3280 {
3281 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3282 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_BD_AUDIO_EN));
3283 }
3284
3285 return TRUE;
3286 }
3287
HAL_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,MS_U32 * pData)3288 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData)
3289 {
3290 switch (u32Cmd)
3291 {
3292 default:
3293 return FALSE;
3294 }
3295
3296 return TRUE;
3297 }
3298
HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId)3299 MS_U8 HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId)
3300 {
3301 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_SCMSTS_GET | (MS_U32)(u8FltId & 0xFF));
3302 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3303 return (MS_U8)(_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3304 }
3305
HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId)3306 MS_U8 HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId)
3307 {
3308 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_SCMSTS_GET | (MS_U32)(u8FltId & 0xFF));
3309 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3310 return (MS_U8)(_HAL_REG32_R(&_TspCtrl[0].MCU_Data0) >> 8);
3311 }
3312
3313 //-------------------------------------------------------------------------------
3314 // @u16Mode : TSP_DEBUG_MODE_DIS_CONT => discontinuous packet count
3315 // TSP_DEBUG_MODE_DROP_COUNT => drop packet count
3316 // @u16Src : TBD
3317 // @u16Fifo : TBD
3318 //-------------------------------------------------------------------------------
_HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE u16Mode,TSP_DEBUG_SRC TspSrc,TSP_DEBUG_FIFO TspFifo)3319 static MS_U32 _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE u16Mode, TSP_DEBUG_SRC TspSrc, TSP_DEBUG_FIFO TspFifo)
3320 {
3321 REG16* pReg = NULL;
3322 MS_U16 u16Mask = 0;
3323 MS_U16 u16Shft = 0;
3324 MS_U16 u16Cfg = 0;
3325
3326 switch (TspSrc)
3327 {
3328 case TSP_DEBUG_SRC_TS0: // TS0
3329 pReg = &(_TspCtrl2[0].PktCnt_TS0);
3330 break;
3331 case TSP_DEBUG_SRC_TS1: // TS1
3332 pReg = &(_TspCtrl2[0].PktCnt_TS1);
3333 break;
3334 case TSP_DEBUG_SRC_FILE: // FILE
3335 pReg = &(_TspCtrl2[0].PktCnt_File);
3336 break;
3337 default:
3338 return 0;
3339 }
3340
3341 switch (TspFifo)
3342 {
3343 case TSP_DEBUG_FIFO_VIDEO: // VIDEO
3344 u16Mask = DISCONTI_CNT_VIDEO_MASK;
3345 u16Shft = DISCONTI_CNT_VIDEO_SHFT;
3346 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2; // discontinuous packet count : drop packet count
3347 break;
3348 case TSP_DEBUG_FIFO_AUDIO: // AUDIO
3349 u16Mask = DISCONTI_CNT_AUDIO_MASK;
3350 u16Shft = DISCONTI_CNT_AUDIO_SHFT;
3351 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2;
3352 break;
3353 case TSP_DEBUG_FIFO_VIDEO3D: // VIDEO3D
3354 u16Mask = DISCONTI_CNT_V3D_MASK;
3355 u16Shft = DISCONTI_CNT_V3D_SHFT;
3356 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2;
3357 break;
3358 default:
3359 return 0;
3360 }
3361
3362 _HAL_REG16_W(&(_TspCtrl2[0].HwCfg1),
3363 (_HAL_REG16_R(&(_TspCtrl2[0].HwCfg1)) & ~HW_INFO_SRC_MODE_MASK) | u16Cfg);
3364
3365 return (MS_U32)(_HAL_REG16_R(pReg) & u16Mask) >> u16Shft;
3366 }
3367
3368 //-------------------------------------------------------------------------------
3369 // @ u16Src : TBD
3370 // @ u16Fifo : TBD
3371 // @ return value : 0 ~ 15
3372 //-------------------------------------------------------------------------------
HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info * TspDisconPktCntInfo)3373 MS_U32 HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info* TspDisconPktCntInfo)
3374 {
3375 if(TspDisconPktCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3376 {
3377 // Set the clear source
3378 if(TspDisconPktCntInfo->TspSrc == TSP_DEBUG_SRC_TS0)
3379 {
3380 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3381 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_0<<TSP_CLR_SRC_SHIFT));
3382 }
3383 else if(TspDisconPktCntInfo->TspSrc == TSP_DEBUG_SRC_FILE)
3384 {
3385 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3386 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_FILE<<TSP_CLR_SRC_SHIFT));
3387 }
3388
3389 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3390 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) | (TSP_DISCONTI_VD_CLR | TSP_DISCONTI_V3D_CLR | TSP_DISCONTI_AUD_CLR|TSP_DISCONTI_AUDB_CLR));
3391 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3392 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~(TSP_DISCONTI_VD_CLR | TSP_DISCONTI_V3D_CLR | TSP_DISCONTI_AUD_CLR|TSP_DISCONTI_AUDB_CLR));
3393 }
3394 return _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE_DIS_CONT, TspDisconPktCntInfo->TspSrc, TspDisconPktCntInfo->TspFifo);
3395 }
3396
3397 //-------------------------------------------------------------------------------
3398 // @ u16Src : TBD
3399 // @ u16Fifo : TBD
3400 // @ return value : 0 ~ 15
3401 //-------------------------------------------------------------------------------
HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info * TspDropCntInfo)3402 MS_U32 HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info* TspDropCntInfo)
3403 {
3404 if(TspDropCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3405 {
3406 // Set the clear source
3407 if(TspDropCntInfo->TspSrc == TSP_DEBUG_SRC_TS0)
3408 {
3409 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3410 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_0<<TSP_CLR_SRC_SHIFT));
3411 }
3412 else if(TspDropCntInfo->TspSrc == TSP_DEBUG_SRC_FILE)
3413 {
3414 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3415 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_FILE<<TSP_CLR_SRC_SHIFT));
3416 }
3417
3418 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3419 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) | (TSP_DUP_PKT_CNT_CLR));
3420 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3421 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~(TSP_DUP_PKT_CNT_CLR));
3422 }
3423 return _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE_DROP_CONT, TspDropCntInfo->TspSrc, TspDropCntInfo->TspFifo);
3424 }
3425
3426 //-------------------------------------------------------------------------------
3427 // @u16Tsif : TBD
3428 // @ return value : 0 ~ 15
3429 //-------------------------------------------------------------------------------
HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info * TspLockCntInfo)3430 MS_U32 HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info* TspLockCntInfo)
3431 {
3432 if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3433 {
3434 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3435 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_CLR_LOCKED_PKT_CNT));
3436 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3437 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_CLR_LOCKED_PKT_CNT));
3438 }
3439 else if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_ENABLE)
3440 {
3441 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3442 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_DIS_LOCKED_PKT_CNT));
3443 }
3444 else if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_DISABLE)
3445 {
3446 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3447 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_DIS_LOCKED_PKT_CNT));
3448 }
3449
3450 switch (TspLockCntInfo->TspTsif)
3451 {
3452 case TSP_DEBUG_TSIF0: // TS0
3453 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].LockPktCnt)) & TS0_LOCK_CNT_MASK) >> TS0_LOCK_CNT_SHFT;
3454 case TSP_DEBUG_TSIF1: // TS1
3455 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].LockPktCnt)) & TS1_LOCK_CNT_MASK) >> TS1_LOCK_CNT_SHFT;
3456 default:
3457 return 0;
3458 }
3459 }
3460
3461 //-------------------------------------------------------------------------------
3462 // @ u16Fifo : TBD
3463 // @ return value : 0 ~ 15
3464 //-------------------------------------------------------------------------------
HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info * TspAVCntInfo)3465 MS_U32 HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info* TspAVCntInfo)
3466 {
3467 if(TspAVCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3468 {
3469 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3470 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_CLR_AV_PKT_CNT));
3471 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3472 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_CLR_AV_PKT_CNT));
3473 }
3474
3475 switch (TspAVCntInfo->TspFifo)
3476 {
3477 case TSP_DEBUG_FIFO_VIDEO: // VIDEO
3478 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].AVPktCnt)) & VIDEO_PKT_CNT_MASK) >> VIDEO_PKT_CNT_SHFT;
3479 case TSP_DEBUG_FIFO_AUDIO: // AUDIO
3480 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].AVPktCnt)) & AUDIO_PKT_CNT_MASK) >> AUDIO_PKT_CNT_SHFT;
3481 default:
3482 return 0;
3483 }
3484 }
3485
3486
HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc)3487 MS_U32 HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc)
3488 {
3489 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_TEI_COUNT_GET | u32PktSrc);
3490 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3491 return (_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3492 }
3493
HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc)3494 MS_BOOL HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc)
3495 {
3496 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_TEI_COUNT_GET | TSP_MCU_CMD_TEI_COUNT_OPTION_RESET | u32PktSrc);
3497 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3498 return TRUE;
3499 }
3500
HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId)3501 MS_U32 HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId)
3502 {
3503 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DISCONT_COUNT_GET | u32FltId);
3504 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3505 return (_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3506 }
3507
HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId)3508 MS_BOOL HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId)
3509 {
3510 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DISCONT_COUNT_GET | TSP_MCU_CMD_DISCONT_COUNT_OPTION_RESET | u32FltId);
3511 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3512 return TRUE;
3513 }
3514
HAL_TSP_SetPacketMode(MS_U32 u32TSIf,MS_U32 u32PktMode)3515 MS_BOOL HAL_TSP_SetPacketMode(MS_U32 u32TSIf, MS_U32 u32PktMode)
3516 {
3517 return FALSE;
3518 }
3519
HAL_TSP_SetMergeStrSyncByte(MS_U32 u32SrcID,MS_U8 u8SyncByte)3520 MS_BOOL HAL_TSP_SetMergeStrSyncByte(MS_U32 u32SrcID, MS_U8 u8SyncByte)
3521 {
3522 return FALSE;
3523 }
3524
HAL_TSP_MOBF_Set_PVRKey_EX(MS_U32 u32PvrEng,MS_U32 u32Key0,MS_U32 u32Key1)3525 void HAL_TSP_MOBF_Set_PVRKey_EX(MS_U32 u32PvrEng, MS_U32 u32Key0, MS_U32 u32Key1)
3526 {
3527 return;
3528 }
3529
3530