1 #ifndef _TSP2_REG_H_ 2 #define _TSP2_REG_H_ 3 4 typedef struct _REG32 5 { 6 volatile MS_U16 low; 7 volatile MS_U16 _null_l; 8 volatile MS_U16 high; 9 volatile MS_U16 _null_h; 10 } REG32; 11 12 typedef struct _REG16 13 { 14 volatile MS_U16 data; //[jerry] not to name "low" 15 volatile MS_U16 _null; 16 } REG16; 17 18 typedef struct _TSP32 19 { 20 volatile MS_U32 reg32; 21 } TSP32; 22 23 24 //######################################################################### 25 //#### Hardware Capability Macro Start 26 //######################################################################### 27 28 #define TSP_TSIF_NUM 7 29 #define TSP_PVRENG_NUM 10 30 #define TSP_PVR_IF_NUM 7 31 #define TSP_OTVENG_NUM 8 32 #define STC_ENG_NUM 8 33 #define TSP_PCRFLT_NUM STC_ENG_NUM 34 35 #define TSP_PIDFLT_NUM 768 36 #define TSP_SECFLT_NUM 512 37 #define TSP_SECBUF_NUM 512 38 39 #define TSP_MERGESTREAM_NUM 32 40 41 //@NOTE: accroding to width of FW/VQ/SEC buffer base addr , lower / upper bound may be different 42 #define TSP_FW_BUF_LOW_BUD 0 43 #define TSP_FW_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:4] , unit: 16-bytes (bits[3:0]) 44 // base addr = {reg_dma_raddr_msb(8-bits),reg_dma_raddr(16-bits),4'b0(4-bits)} 45 #define TSP_VQ_BUF_LOW_BUD 0 46 #define TSP_VQ_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:0] , unit: 1-byte 47 #define TSP_SEC_BUF_LOW_BUD 0 48 #define TSP_SEC_BUF_UP_BUD ((1ULL << 32) - 1) // base addr: bits[31:0] , unit: 1-byte 49 50 51 52 //######################################################################### 53 //#### Hardware Capability Macro End 54 //######################################################################### 55 56 57 // PID Filter 58 typedef TSP32 REG_PidFlt; // 0x210000 59 60 #define TSP_FILTER_DEPTH 16 61 62 63 //######################################################################### 64 //#### CLKGEN0 Bank:0x100B 65 //######################################################################### 66 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x1600 + ((addr)<<2)))) 67 68 #define REG_CLKGEN0_DC0_SYTNTH 0x05 69 #define REG_CLKGEN0_STC_CW_SEL 0x0002 70 #define REG_CLKGEN0_STC_CW_EN 0x0004 71 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 72 #define REG_CLKGEN0_STC1_CW_EN 0x0400 73 74 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 75 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 76 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 77 #define REG_CLKGEN0_DC0_STC1_CW_H 0x09 78 79 #define REG_CLKGEN0_S2P_IN_CLK_SRC 0x0C 80 #define REG_CLKGEN0_S2P_IN_CLK_SHIFT 0 81 #define REG_CLKGEN0_S2P1_IN_CLK_SHIFT 8 82 #define REG_CLKGEN0_S2P_IN_CLK_MASK 0x1F 83 #define REG_CLKGEN0_S2P_IN_CLK_DISABLE 0x0001 84 #define REG_CLKGEN0_S2P_IN_CLK_INVERT 0x0002 85 #define REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT 2 86 #define REG_CLKGEN0_S2P_IN_CLK_SRC_MASK 0x7 87 88 #define REG_CLKGEN0_TSO0_CLK 0x27 // TSO #0 89 #define REG_CLKGEN0_TSO0_SHIFT 0 90 91 #define REG_CLKGEN0_TS0_CLK 0x28 92 #define REG_CLKGEN0_TS0_SHIFT 0 93 #define REG_CLKGEN0_TS1_CLK 0x28 94 #define REG_CLKGEN0_TS1_SHIFT 8 95 #define REG_CLKGEN0_TS2_CLK 0x29 96 #define REG_CLKGEN0_TS2_SHIFT 0 97 #define REG_CLKGEN0_TS3_CLK 0x29 98 #define REG_CLKGEN0_TS3_SHIFT 8 99 #define REG_CLKGEN0_TS4_CLK 0x6B 100 #define REG_CLKGEN0_TS4_SHIFT 0 101 #define REG_CLKGEN0_TS5_CLK 0x6B 102 #define REG_CLKGEN0_TS5_SHIFT 8 103 #define REG_CLKGEN0_TS6_CLK 0x6C 104 #define REG_CLKGEN0_TS6_SHIFT 0 105 106 #define REG_CLKGEN0_TS_MASK 0x003F // 4 bit each 107 #define REG_CLKGEN0_TS_DISABLE 0x0001 108 #define REG_CLKGEN0_TS_INVERT 0x0002 109 #define REG_CLKGEN0_TS_SRC_SHIFT 2 110 #define REG_CLKGEN0_TS_SRC_MASK 0x000F 111 #define REG_CLKGEN0_TS_SRC_EXT0 0x0000 112 #define REG_CLKGEN0_TS_SRC_EXT1 0x0001 113 #define REG_CLKGEN0_TS_SRC_EXT2 0x0002 114 #define REG_CLKGEN0_TS_SRC_EXT3 0x0003 115 #define REG_CLKGEN0_TS_SRC_EXT4 0x0004 116 #define REG_CLKGEN0_TS_SRC_EXT5 0x0005 117 #define REG_CLKGEN0_TS_SRC_EXT6 0x0006 118 #define REG_CLKGEN0_TS_SRC_EXT7 0x0007 119 #define REG_CLKGEN0_TS_SRC_EXT8 0x0008 120 #define REG_CLKGEN0_TS_SRC_TSO0 0x0009 121 #define REG_CLKGEN0_TS_SRC_TSO1 0x000A 122 #define REG_CLKGEN0_TS_SRC_TSIO0 0x000B 123 #define REG_CLKGEN0_TS_SRC_CILINK 0x000C 124 //@NOTE Not support internal demod in K7U 125 126 //get TSP Clk Gen bank 127 #define REG_CLKGEN0_TSP_CLK 0x2A 128 #define REG_CLKGEN0_TSP_CLK_MASK 0x001F 129 #define REG_CLKGEN0_TSP_SHIFT 0 130 #define REG_CLKGEN0_TSP_DISABLE 0x0001 131 #define REG_CLKGEN0_TSP_INVERT 0x0002 132 //SRC 133 #define REG_CLKGEN0_TSP_SRC_SHIFT 2 134 #define REG_CLKGEN0_TSP_SRC_MASK 0x0007 135 #define REG_CLKGEN0_TSP_SRC_288MHZ 0x0000 136 #define REG_CLKGEN0_TSP_SRC_240MHZ 0x0001 137 #define REG_CLKGEN0_TSP_SRC_216MHZ 0x0002 138 #define REG_CLKGEN0_TSP_SRC_192MHZ 0x0003 139 #define REG_CLKGEN0_TSP_SRC_172MHZ 0x0004 140 #define REG_CLKGEN0_TSP_SRC_144MHZ 0x0005 141 #define REG_CLKGEN0_TSP_SRC_108MHZ 0x0006 142 #define REG_CLKGEN0_TSP_SRC_XTAL 0x0007 143 144 //get STC0/1 Clk Gen bank 145 #define REG_CLKGEN0_STC0_CLK 0x2A 146 #define REG_CLKGEN0_STC0_MASK 0x0F00 147 #define REG_CLKGEN0_STC0_SHIFT 8 148 #define REG_CLKGEN0_STC1_CLK 0x2A 149 #define REG_CLKGEN0_STC1_MASK 0xF000 150 #define REG_CLKGEN0_STC1_SHIFT 12 151 #define REG_CLKGEN0_STC_DISABLE 0x0001 152 #define REG_CLKGEN0_STC_INVERT 0x0002 153 //SRC 154 #define REG_CLKGEN0_STC_SRC_SHIFT 2 155 #define REG_CLKGEN0_STC_SRC_MASK 0x0003 156 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 157 #define REG_CLKGEN0_STC_SRC_ONE 0x0001 // reserved 158 #define REG_CLKGEN0_STC_SRC_27M 0x0002 159 #define REG_CLKGEN0_STC_SRC_XTAL 0x0003 // reserved 160 161 #define REG_CLKGEN0_STAMP_CLK 0x2F 162 #define REG_CLKGEN0_STAMP_MASK 0x0F00 163 #define REG_CLKGEN0_STAMP_SHIFT 8 164 #define REG_CLKGEN0_STAMP_DISABLE 0x0001 165 #define REG_CLKGEN0_STAMP_INVERT 0x0002 166 167 #define REG_CLKGEN0_PARSER_CLK 0x39 168 #define REG_CLKGEN0_PARSER_MASK 0x0F00 169 #define REG_CLKGEN0_PARSER_SHIFT 8 170 #define REG_CLKGEN0_PARSER_DISABLE 0x0001 171 #define REG_CLKGEN0_PARSER_INVERT 0x0002 172 173 //######################################################################### 174 //#### CLKGEN1 Bank:0x1033 175 //######################################################################### 176 #define TSP_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x6600 + ((addr)<<2)))) 177 #define REG_CLKGEN1_DC0_SYTNTH 0x5A 178 #define REG_CLKGEN1_STC4_CW_SEL 0x0002 179 #define REG_CLKGEN1_STC4_CW_EN 0x0004 180 #define REG_CLKGEN1_STC5_CW_SEL 0x0200 181 #define REG_CLKGEN1_STC5_CW_EN 0x0400 182 183 #define REG_CLKGEN1_DC0_STC4_CW_L 0x5B 184 #define REG_CLKGEN1_DC0_STC4_CW_H 0x5C 185 #define REG_CLKGEN1_DC0_STC5_CW_L 0x5D 186 #define REG_CLKGEN1_DC0_STC5_CW_H 0x5E 187 188 #define REG_CLKGEN1_STC4_CLK 0x5F 189 #define REG_CLKGEN1_STC4_MASK 0x000F 190 #define REG_CLKGEN1_STC4_SHIFT 0 191 #define REG_CLKGEN1_STC5_CLK 0x5F 192 #define REG_CLKGEN1_STC5_MASK 0x00F0 193 #define REG_CLKGEN1_STC5_SHIFT 4 194 #define REG_CLKGEN1_STC_DISABLE 0x0001 195 #define REG_CLKGEN1_STC_INVERT 0x0002 196 //SRC 197 #define REG_CLKGEN1_STC_SRC_SHIFT 2 198 #define REG_CLKGEN1_STC_SRC_MASK 0x0003 199 #define REG_CLKGEN1_STC_SRC_SYNTH 0x0000 200 #define REG_CLKGEN1_STC_SRC_ONE 0x0001 // reserved 201 #define REG_CLKGEN1_STC_SRC_27M 0x0002 202 #define REG_CLKGEN1_STC_SRC_XTAL 0x0003 // reserved 203 204 #define REG_CLKGEN1_DC1_SYTNTH 0x6A 205 #define REG_CLKGEN1_STC6_CW_SEL 0x0002 206 #define REG_CLKGEN1_STC6_CW_EN 0x0004 207 #define REG_CLKGEN1_STC7_CW_SEL 0x0200 208 #define REG_CLKGEN1_STC7_CW_EN 0x0400 209 210 #define REG_CLKGEN1_DC1_STC6_CW_L 0x6B 211 #define REG_CLKGEN1_DC1_STC6_CW_H 0x6C 212 #define REG_CLKGEN1_DC1_STC7_CW_L 0x6D 213 #define REG_CLKGEN1_DC1_STC7_CW_H 0x6E 214 215 #define REG_CLKGEN1_STC6_CLK 0x6F 216 #define REG_CLKGEN1_STC6_MASK 0x000F 217 #define REG_CLKGEN1_STC6_SHIFT 0 218 #define REG_CLKGEN1_STC7_CLK 0x6F 219 #define REG_CLKGEN1_STC7_MASK 0x00F0 220 #define REG_CLKGEN1_STC7_SHIFT 4 221 222 223 //######################################################################### 224 //#### CLKGEN2 Bank:0x100A 225 //######################################################################### 226 #define TSP_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x1400 + ((addr)<<2)))) 227 #define REG_CLKGEN2_DC0_SYTNTH 0x4A 228 #define REG_CLKGEN2_STC2_CW_SEL 0x0002 229 #define REG_CLKGEN2_STC2_CW_EN 0x0004 230 #define REG_CLKGEN2_STC3_CW_SEL 0x0200 231 #define REG_CLKGEN2_STC3_CW_EN 0x0400 232 233 #define REG_CLKGEN2_DC0_STC2_CW_L 0x4B 234 #define REG_CLKGEN2_DC0_STC2_CW_H 0x4C 235 #define REG_CLKGEN2_DC0_STC3_CW_L 0x4D 236 #define REG_CLKGEN2_DC0_STC3_CW_H 0x4E 237 238 //get STC2/3 Clk Gen bank 239 #define REG_CLKGEN2_STC2_CLK 0x4F 240 #define REG_CLKGEN2_STC2_MASK 0x000F 241 #define REG_CLKGEN2_STC2_SHIFT 0 242 #define REG_CLKGEN2_STC3_CLK 0x4F 243 #define REG_CLKGEN2_STC3_MASK 0x00F0 244 #define REG_CLKGEN2_STC3_SHIFT 4 245 #define REG_CLKGEN2_STC_DISABLE 0x0001 246 #define REG_CLKGEN2_STC_INVERT 0x0002 247 //SRC 248 #define REG_CLKGEN2_STC_SRC_SHIFT 2 249 #define REG_CLKGEN2_STC_SRC_MASK 0x0003 250 #define REG_CLKGEN2_STC_SRC_SYNTH 0x0000 251 #define REG_CLKGEN2_STC_SRC_ONE 0x0001 // reserved 252 #define REG_CLKGEN2_STC_SRC_27M 0x0002 253 #define REG_CLKGEN2_STC_SRC_XTAL 0x0003 // reserved 254 255 //######################################################################### 256 //#### CHIPTOP Bank:0x101E 257 //######################################################################### 258 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x3c00UL + ((addr)<<2)))) 259 260 #define REG_TOP_TS_PADMUX_MODE 0x02 261 #define REG_TOP_TS0MODE_MASK 0x1 262 #define REG_TOP_TS0MODE_SHIFT 0 263 #define REG_TOP_TS0MODE_PARALLEL 1 264 #define REG_TOP_TS1MODE_MASK 0x3 265 #define REG_TOP_TS1MODE_SHIFT 1 266 #define REG_TOP_TS1MODE_INPUT 1 267 #define REG_TOP_TS2MODE_MASK 0x3 268 #define REG_TOP_TS2MODE_SHIFT 3 269 #define REG_TOP_TS2MODE_PARALLEL 1 270 #define REG_TOP_TS2MODE_4WIRED 2 271 #define REG_TOP_TS2MODE_3WIRED 3 272 273 #define REG_TOP_TS_OUTPUT_MODE 0x07 274 #define REG_TOP_TS_OUT_MODE_MASK 0x3 275 #define REG_TOP_TS_OUT_MODE_SHIFT 14 276 #define REG_TOP_TS_OUT_MODE_TSO 1 277 #define REG_TOP_TS_OUT_MODE_S2P 2 278 #define REG_TOP_TS_OUT_MODE_S2P1 3 279 280 #define REG_TOP_TSP_BOOT_CLK_SEL 0x54 281 #define REG_TOP_TSP_BOOT_CLK_SEL_MASK 0x0100 282 #define REG_TOP_TSP_BOOT_CLK_SEL_TSP 0x0000 283 284 285 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x27E00 + ((addr)<<2)))) 286 #define REG_MMFI_TSP_SEL_SRAM 0x70 287 #define REG_MMFI_TSP_SEL_SRAM_EN 0x0002 288 289 #define TSP_TSO_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0xE0C00 + ((addr)<<2)))) 290 #define REG_TSO_TSP_CONFIG0 0x1C 291 #define REG_TSO_TSP_S2P_MASK 0x001F 292 #define REG_TSO_TSP_S2P_EN 0x0001 293 #define REG_TSO_TSP_S2P_TS_SIN_C0 0x0002 294 #define REG_TSO_TSP_S2P_TS_SIN_C1 0x0004 295 #define REG_TSO_TSP_S2P_3WIRE 0x0008 296 #define REG_TSO_TSP_BYPASS_S2P 0x0010 297 298 #define REG_TSO_TSP_S2P1_MASK 0x1F00 299 #define REG_TSO_TSP_S2P1_EN 0x0100 300 #define REG_TSO_TSP_S2P1_TS_SIN_C0 0x0200 301 #define REG_TSO_TSP_S2P1_TS_SIN_C1 0x0400 302 #define REG_TSO_TSP_S2P1_3WIRE 0x0800 303 #define REG_TSO_TSP_BYPASS_S2P1 0x1000 304 305 306 typedef struct _REG_SecFlt 307 { 308 TSP32 Ctrl; 309 // Software Usage Flags 310 #define TSP_SECFLT_USER_MASK 0x00000007 311 #define TSP_SECFLT_USER_SHFT 0 312 #define TSP_SECFLT_USER_NULL 0x0 313 #define TSP_SECFLT_USER_SEC 0x1 314 #define TSP_SECFLT_USER_PES 0x2 315 #define TSP_SECFLT_USER_PKT 0x3 316 #define TSP_SECFLT_USER_PCR 0x4 317 #define TSP_SECFLT_USER_TTX 0x5 318 /* 319 #define TSP_SECFLT_USER_EMM 0x6 320 #define TSP_SECFLT_USER_ECM 0x7 321 #define TSP_SECFLT_USER_OAD 0x8 322 */ 323 324 #define TSP_SEC_MATCH_INV 0x00000008 // HW 325 326 // for 327 // TSP_SECFLT_TYPE_SEC 328 // TSP_SECFLT_TYPE_PES 329 // TSP_SECFLT_TYPE_PKT 330 // TSP_SECFLT_TYPE_TTX 331 // TSP_SECFLT_TYPE_OAD 332 #define TSP_SECFLT_MODE_MASK 0x00000030 // software implementation 333 #define TSP_SECFLT_MODE_SHFT 4 334 #define TSP_SECFLT_MODE_CONTI 0x0 // SEC 335 #define TSP_SECFLT_MODE_ONESHOT 0x1 336 #define TSP_SECFLT_MODE_CRCCHK 0x2 337 // for TSP_SECFLT_TYPE_PCR 338 #define TSP_SECFLT_PCRRST 0x00000010 //[OBSOLETED] PCR 339 340 341 //[NOTE] update section filter 342 // It's not recommended for user updating section filter control register 343 // when filter is enable. There may be race condition. 344 #define TSP_SECFLT_STATE_MASK 0x000000C0 // software implementation 345 #define TSP_SECFLT_STATE_SHFT 6 346 #define TSP_SECFLT_STATE_OVERFLOW 0x1 347 #define TSP_SECFLT_STATE_DISABLE 0x2 348 349 #define TSP_SECFLT_BEMASK 0x0000FF00 //[Reserved] 350 351 352 // for 353 // TSP_SECFLT_SEL_BUF 354 #define TSP_SECFLT_SECBUF_MASK 0xFF000000 // [31:24] secbuf id (secbuf id low field) 355 #define TSP_SECFLT_SECBUF_SHFT 24 356 #define TSP_SECFLT_SECBUF_MAX 0x1FF // software usage 357 358 TSP32 Match[TSP_FILTER_DEPTH/sizeof(TSP32)]; 359 TSP32 Mask[TSP_FILTER_DEPTH/sizeof(TSP32)]; 360 /* 361 TSP32 BufStart; 362 TSP32 BufEnd; 363 TSP32 BufRead; 364 TSP32 BufWrite; 365 TSP32 BufCur; 366 */ 367 TSP32 _x24[(0x38-0x24)/sizeof(TSP32)]; // (0x00211024-0x0021103B)/4 368 369 TSP32 RmnCnt; 370 #define TSP_SECFLT_ALLOC_MASK 0x80000000 371 #define TSP_SECFLT_ALLOC_SHFT 31 372 #define TSP_SECFLT_OWNER_MASK 0x70000000 373 #define TSP_SECFLT_OWNER_SHFT 24 374 375 #define TSP_SECFLT_MODE_AUTO_CRCCHK 0x00100000 //sec flt mode bits are not enough, arbitrarily occupy here 376 377 #define TSP_SECBUF_RMNCNT_MASK 0x0000FFFF // TS/PES length 378 #define TSP_SECBUF_RMNCNT_SHFT 0 379 380 /* 381 // for 382 // TSP_SECFLT_TYPE_ECM 383 #define TSP_SECFLT_ECM_IDX_SHFT 16 384 #define TSP_SECFLT_ECM_IDX_MASK 0x00070000 385 #define TSP_SECFLT_ECM_IDX_NULL 0x00000007 // only alow 0 .. 5 386 */ 387 388 TSP32 CRC32; 389 390 TSP32 NMask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 391 392 TSP32 Ctrl_1; 393 #define TSP_SECFLT_SECBUF_H_MASK 0x00000001 // secbuf id high field (bit[8]) 394 #define TSP_SECFLT_SECBUF_H_SHFT 0 395 396 TSP32 _x54[(0x80-0x54)/sizeof(TSP32)]; // (0x00211054-0x0021107F)/4 397 398 } REG_SecFlt; 399 400 typedef struct _REG_SecBuf 401 { 402 TSP32 Start; 403 #define TSP_SECBUF_START_MASK 0x1FFFFFF0 //section buffers of kaiser and keltic are "4" bits aligment 404 #define TSP_SECBUF_OWNER_MASK 0x60000000 405 #define TSP_SECBUF_OWNER_SHFT 29 406 #define TSP_SECBUF_ALLOC_MASK 0x80000000 407 #define TSP_SECBUF_ALLOC_SHFT 31 408 TSP32 End; 409 TSP32 Read; 410 TSP32 Write; 411 TSP32 Cur; 412 TSP32 _x38[(0xA4-0x38)/sizeof(TSP32)]; // (0x0021103C-0x002110A4)/4 413 } REG_SecBuf; 414 415 typedef struct _REG_Pid 416 { // CPU(byte) RIU(index) MIPS(0x1500/2+RIU)*4 417 REG_PidFlt Flt[TSP_PIDFLT_NUM]; // 0x00210000-0x00210007C 418 } REG_Pid; 419 420 typedef struct _REG_Sec 421 { // CPU(byte) RIU(index) MIPS(0x1500/2+RIU)*4 422 REG_SecFlt Flt[TSP_SECFLT_NUM]; 423 } REG_Sec; 424 425 426 typedef struct _REG_Buf 427 { 428 REG_SecBuf Buf[TSP_SECFLT_NUM]; 429 } REG_Buf; 430 431 432 //@NOTE TSP 0~1 433 typedef struct _REG_Ctrl 434 { 435 //---------------------------------------------- 436 // 0xBF802A00 MIPS direct access 437 //---------------------------------------------- 438 // Type Name Index(word) CPU(byte) MIPS(0x1500/2+index)*4 439 REG16 _xbf202a00; // 0xbf802a00 0x00 440 REG32 Str2mi_head2pvr1; // 0xbf802a04 0x01 441 #define TSP_HW_PVR1_BUF_HEAD2_MASK 0x0FFFFFFF 442 REG32 Str2mi_mid2pvr1; // 0xbf802a0c 0x03 ,wptr & mid share same register 443 #define TSP_HW_PVR1_BUF_MID2_MASK 0x0FFFFFFF 444 REG32 Str2mi_tail2pvr1; // 0xbf802a14 0x05 445 #define TSP_HW_PVR1_BUF_TAIL2_MASK 0x0FFFFFFF 446 447 REG32 Pcr_L; // 0xbf802a1c 0x07_0x08 448 #define TSP_PCR64_L32_MASK 0xFFFFFFFF 449 REG32 Pcr_H; // 0xbf802a24 0x09_0x0a 450 #define TSP_PCR64_H32_MASK 0xFFFFFFFF // PCR64 Middle 64 451 452 REG16 Mobf_Filein_Idx; // 0xbf802a2c 0x0b 453 #define TSP_MOBF_FILEIN_MASK 0x0000001F 454 455 REG32 _xbf202a2c; // 0xbf802a30 0x0c_0x0d 456 457 REG32 PVR2_Config; // 0xbf802a38 0x0e_0x0f 458 #define TSP_PVR2_LPCR1_WLD 0x00000001 459 #define TSP_PVR2_LPCR1_RLD 0x00000002 460 #define TSP_PVR2_STR2MIU_DSWAP 0x00000004 461 #define TSP_PVR2_STR2MIU_EN 0x00000008 462 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 463 #define TSP_PVR2_STR2MIU_BT_ORDER 0x00000020 464 #define TSP_PVR2_STR2MIU_PAUSE 0x00000040 465 #define TSP_PVR2_REG_PINGPONG_EN 0x00000080 466 #define TSP_PVR2_PVR_ALIGN_EN 0x00000100 467 #define TSP_PVR2_DMA_FLUSH_EN 0x00000200 468 #define TSP_PVR2_PKT192_EN 0x00000400 469 #define TSP_PVR2_BURST_LEN_MASK 0x00001800 470 #define TSP_PVR2_BURST_LEN_SHIFT 11 471 #define TSP_REC_DATA2_INV 0x00002000 472 #define TSP_V_BLOCK_DIS 0x00004000 473 #define TSP_V3d_BLOCK_DIS 0x00008000 474 #define TSP_A_BLOCK_DIS 0x00010000 475 #define TSP_AD_BLOCK_DIS 0x00020000 476 #define TSP_PVR1_BLOCK_DIS 0x00040000 477 #define TSP_PVR2_BLOCK_DIS 0x00080000 478 #define TSP_TS_IF2_EN 0x00100000 479 #define TSP_TS_DATA2_SWAP 0x00200000 480 #define TSP_P_SEL2 0x00400000 481 #define TSP_EXT_SYNC_SEL2 0x00800000 482 #define TSP_BYPASS_TSIF2 0x01000000 483 #define TSP_TEI_SKIP_PKT2 0x02000000 484 #define TSP_AC_BLOCK_DIS 0x04000000 485 #define TSP_ADD_BLOCK_DIS 0x08000000 486 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000 487 #define TSP_CLR_PKT_CNT 0x40000000 488 #define TSP_CLR_PVR_OVERFLOW 0x80000000 489 490 REG32 PVR2_LPCR1; // 0xbf802a40 0x10_0x11 491 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFF 492 493 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12_0x13 494 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14_0x15 495 REG32 Str2mi_tail1_pvr2; // 0xbf802a58 0x16_0x17 496 REG32 Str2mi_head2_pvr2; // 0xbf802a60 0x18_0x19 497 REG32 Str2mi_mid2_pvr2; // 0xbf802a68 0x1a_0x1b, PVR2 mid address & write point 498 REG32 Str2mi_tail2_pvr2; // 0xbf802a70 0x1c_0x1d 499 REG32 Hw_SyncByte2; // 0xbf802a78 0x1e_0x1f 500 #define TSP_HW_CFG2_PACKET_SYNCBYTE2_MASK 0x000000FF 501 #define TSP_HW_CFG2_PACKET_SYNCBYTE2_SHFT 0 502 #define TSP_HW_CFG2_PACKET_SIZE2_MASK 0x0000FF00 503 #define TSP_HW_CFG2_PACKET_SIZE2_SHFT 8 504 #define TSP_HW_CFG2_PACKET_CHK_SIZE2_MASK 0x00FF0000 505 #define TSP_HW_CFG2_PACKET_CHK_SIZE2_SHFT 16 506 507 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 508 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 509 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 510 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 511 REG32 Pkt_CacheIdx; // 0xbf802aa0 0x28 512 513 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 514 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FF 515 #define TSP_SEC_DMAFIL_NUM_SHIFT 0 516 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00 517 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8 518 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000 519 #define TSP_SEC_DMADES_LEN_SHIFT 16 520 521 REG16 Hw_Config0; // 0xbf802ab0 0x2c 522 #define TSP_HW_CFG0_DATA_PORT_SEL 0x0001 //TSIF0 data port output select. 0: select live TS to be TSIF output 1: select data port to be TSIF output 523 #define TSP_HW_CFG0_TSIFO_SERL 0x0000 524 #define TSP_HW_CFG0_TSIF0_PARL 0x0002 525 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x0004 526 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x0008 527 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x0010 528 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x0020 529 #define TSP_HW_CFG0_WB_DMA_RESET 0x0040 530 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0xFF00 531 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8 532 533 REG16 Hw_PktSize0; // 0xbf802ab4 0x2d 534 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF 535 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 0 536 #define TSP_HW_CFG0_PACKET_CHK_SIZE_MASK 0xFF00 537 #define TSP_HW_CFG0_PACKET_CHK_SIZE_SHFT 8 538 539 REG16 STC_Config; // 0xbf802ab8 0x2e 540 #define TSP_STC_CFG_SET_TIME_BASE_64b_3 0x0001 541 #define TSP_STC_CFG_CNT64b_3_EN 0x0002 542 #define TSP_STC_CFG_CNT64b_3_LD 0x0004 543 #define TSP_STC_CFG_SET_TIME_BASE_64b_4 0x0010 544 #define TSP_STC_CFG_CNT64b_4_EN 0x0020 545 #define TSP_STC_CFG_CNT64b_4_LD 0x0040 546 547 REG16 TSP_DBG_PORT; // 0xbf802ab8 0x2f 548 #define TSP_DNG_DATA_PORT_MASK 0x00FF 549 #define TSP_DNG_DATA_PORT_SHIFT 0 550 551 REG32 Pcr_L_CmdQ; // 0xbf802ac0 0x30 552 REG16 Pcr_H_CmdQ; // 0xbf802ac8 0x32 553 #define TSP_REG_PCR_CMDQ_H 0x0001 554 555 REG16 Vd_Pid_Hit; // 0xbf802acc 0x33 556 #define TSP_VPID_MASK 0x1FFF 557 558 REG16 Aud_Pid_Hit; // 0xbf802ad0 0x34 559 #define TSP_APID_MASK 0x1FFF 560 561 REG16 Pkt_Info; // 0xbf802ad4 0x35 562 #define TSP_PKT_PID_8_12_CP_MASK 0x001F 563 #define TSP_PKT_PID_8_12_CP_SHIFT 0 564 #define TSP_PKT_PRI_MASK 0x0020 565 #define TSP_PKT_PRI_SHIFT 5 566 #define TSP_PKT_PLST_MASK 0x0040 567 #define TSP_PKT_PLST_SHIFT 6 568 #define TSP_PKT_ERR 0x0080 569 #define TSP_PKT_ERR_SHIFT 7 570 571 REG16 Pkt_Info2; // 0xbf802ad8 0x36 572 #define TSP_PKT_INFO_CC_MASK 0x000F 573 #define TSP_PKT_INFO_CC_SHFT 0 574 #define TSP_PKT_INFO_ADPCNTL_MASK 0x0030 575 #define TSP_PKT_INFO_ADPCNTL_SHFT 4 576 #define TSP_PKT_INFO_SCMB 0x00C0 577 #define TSP_PKT_INFO_SCMB_SHFT 6 578 #define TSP_PKT_PID_0_7_CP_MASK 0xFF00 579 #define TSP_PKT_PID_0_7_CP_SHIFT 8 580 581 REG16 AVFifoSts; // 0xbf802adc 0x37 582 #define TSP_VFIFO3D_EMPTY 0x0001 583 #define TSP_VFIFO3D_EMPTY_SHFT 0 584 #define TSP_VFIFO3D_FULL 0x0002 585 #define TSP_VFIFO3D_FULL_SHFT 1 586 #define TSP_VFIFO3D_LEVEL 0x000C 587 #define TSP_VFIFO3D_LEVEL_SHFT 2 588 #define TSP_VFIFO_EMPTY 0x0010 589 #define TSP_VFIFO_EMPTY_SHFT 4 590 #define TSP_VFIFO_FULL 0x0020 591 #define TSP_VFIFO_FULL_SHFT 5 592 #define TSP_VFIFO_LEVEL 0x00C0 593 #define TSP_VFIFO_LEVEL_SHFT 6 594 #define TSP_AFIFO_EMPTY 0x0100 595 #define TSP_AFIFO_EMPTY_SHFT 8 596 #define TSP_AFIFO_FULL 0x0200 597 #define TSP_AFIFO_FULL_SHFT 9 598 #define TSP_AFIFO_LEVEL 0x0C00 599 #define TSP_AFIFO_LEVEL_SHFT 10 600 #define TSP_AFIFOB_EMPTY 0x1000 601 #define TSP_AFIFOB_EMPTY_SHFT 12 602 #define TSP_AFIFOB_FULL 0x2000 603 #define TSP_AFIFOB_FULL_SHFT 13 604 #define TSP_AFIFOB_LEVEL 0xC000 605 #define TSP_AFIFOB_LEVEL_SHFT 14 606 607 REG32 SwInt_Stat; // 0xbf802ae0 0x38 608 #define TSP_SWINT_INFO_SEC_MASK 0x00000FFF 609 #define TSP_SWINT_INFO_SEC_SHFT 0 610 #define TSP_SWINT_INFO_ENG_MASK 0x0000F000 611 #define TSP_SWINT_INFO_ENG_SHFT 12 612 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000 613 #define TSP_SWINT_STATUS_CMD_SHFT 16 614 #define TSP_SWINT_STATUS_SEC_RDY 0x0001 615 #define TSP_SWINT_STATUS_REQ_RDY 0x0002 616 #define TSP_SWINT_STATUS_SEC_RDY_CRCERR 0x0003 617 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006 618 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007 619 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008 620 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010 621 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020 622 #define TSP_SWINT_STATUS_DEBUG 0x0030 623 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100 624 #define TSP_SWINT_CMD_DMA_RESUME 0x0200 625 #define TSP_SWINT_STATUS_SEC_GROUP 0x000F 626 #define TSP_SWINT_STATUS_GROUP 0x00FF 627 #define TSP_SWINT_CMD_GROUP 0x7F00 628 #define TSP_SWINT_CMD_STC_UPD 0x0400 629 #define TSP_SWINT_CTRL_FIRE 0x80000000 630 631 REG32 TsDma_Addr; // 0xbf802ae8 0x3a 632 REG32 TsDma_Size; // 0xbf802af0 0x3c 633 REG16 TsDma_Ctrl; // 0xbf802af8 0x3e 634 #define TSP_TSDMA_CTRL_START 0x0001 635 #define TSP_TSDMA_FILEIN_DONE 0x0002 636 #define TSP_TSDMA_INIT_TRUST 0x0004 637 #define TSP_TSDMA_STAT_ABORT 0x0080 638 639 REG16 TsDma_mdQ; // 0xbf802af8 0x3f 640 #define TSP_CMDQ_CNT_MASK 0x001F 641 #define TSP_CMDQ_CNT_SHFT 0 642 #define TSP_CMDQ_FULL 0x0040 643 #define TSP_CMDQ_EMPTY 0x0080 644 #define TSP_CMDQ_SIZE 16 645 #define TSP_CMDQ_WR_LEVEL_MASK 0x0300 646 #define TSP_CMDQ_WR_LEVEL_SHFT 8 647 648 REG32 MCU_Cmd; // 0xbf802b00 0x40 649 #define TSP_MCU_CMD_MASK 0x0000FFFF 650 #define TSP_MCU_CMD_NULL 0x00000000 651 #define TSP_MCU_CMD_READ 0x00000001 652 #define TSP_MCU_CMD_WRITE 0x00000002 653 #define TSP_MCU_CMD_ALIVE 0x00000100 654 #define TSP_MCU_CMD_DBG 0x00000200 655 #define TSP_MCU_CMD_BUFRST 0x00000400 656 #define TSP_MCU_CMD_SECRDYINT_DISABLE 0x00000800 657 #define TSP_MCU_CMD_SEC_CC_CHECK_DISABLE 0x00001000 658 #define TSP_MCU_CMD_INFO 0x00008000 659 #define INFO_FW_VERSION 0x0001 660 #define INFO_FW_DATE 0x0002 661 662 REG16 PktSize1; // 0xbf802b08 0x42 663 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x00FF 664 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0 665 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0xFF00 666 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8 667 668 REG16 Hw_Config2; // 0xbf802b0C 0x43 669 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF 670 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 0 671 #define TSP_HW_CFG2_TSIF1_SERL 0x0000 672 #define TSP_HW_CFG2_TSIF1_PARL 0x0100 673 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x0200 674 #define TSP_HW_CFG2_TSIF1_TS_BYPASS 0x1000 675 676 REG16 Hw_PVRCfg; // 0xbf802b10 0x44 677 #define TSP_HW_CFG4_SECDMA_PRI_HIGH 0x0001 678 #define TSP_HW_CFG4_PVR_ENABLE 0x0002 679 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x0004 // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 680 #define TSP_HW_CFG4_TSIF1_ENABLE 0x0008 // 1: enable ts interface 1 and vice versa 681 #define TSP_HW_CFG4_PVR_FLUSH 0x0010 // 1: str2mi_wadr <- str2mi_miu_head 682 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x0020 // Byte order of 8-byte recoding buffer to MIU. 683 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 684 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x0080 // 32-bit data byte order read from 8x64 FIFO when playing file. 685 #define TSP_HW_CFG4_TSIF0_ENABLE 0x0100 // 1: enable ts interface 0 and vice versa 686 #define TSP_SYNC_RISING_DETECT 0x0200 // Reset bit count when data valid signal of TS interface is low. 687 #define TSP_VALID_FALLING_DETECT 0x0400 // Reset bit count on the rising sync signal of TS interface. 688 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x0800 // Set 1 to swap the bit order of TS0 DATA bus 689 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x1000 // Set 1 to swap the bit order of TS1 DATA bus 690 #define TSP_HW_TSP2OUTAEON_INT_EN 0x4000 // Set 1 to force interrupt to outside AEON 691 #define TSP_HW_HK_INT_FORCE 0x8000 // Set 1 to force interrupt to HK_MCU 692 693 REG16 Hw_Config4; // 0xbf802b14 0x45 694 #define TSP_HW_CFG4_ALT_TS_SIZE 0x0001 // enable TS packets in 204 mode 695 #define TSP_HW_CFG4_PS_AUDC_EN 0x0002 // program stream audiodC enable 696 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000D // prevent from byte enable bug, bit1~3 must enable togather 697 #define TSP_HW_DMA_MODE_MASK 0x0030 // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 698 #define TSP_HW_DMA_MODE_SHIFT 4 699 #define TSP_HW_CFG4_WSTAT_CH_EN 0x0040 700 #define TSP_HW_CFG4_PS_VID_EN 0x0080 // program stream video enable 701 #define TSP_HW_CFG4_PS_AUD_EN 0x0100 // program stream audio enable 702 #define TSP_HW_CFG4_PS_AUDB_EN 0x0200 // program stream audioB enable 703 #define TSP_HW_CFG4_APES_ERR_RM_EN 0x0400 // Set 1 to enable removing APES error packet 704 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x0800 // Set 1 to enable removing VPES error packet 705 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x1000 // Set 1 to enable removing section error packet 706 #define TSP_HW_CFG4_PS_AUDD_EN 0x2000 // program stream audioD enable 707 #define TSP_HW_CFG4_DATA_CHK_2T 0x8000 // Set 1 to enable the patch of internal sync in "tsif" 708 709 REG32 NOEA_PC; // 0xbf802b18 0x46 710 711 REG16 Idr_Ctrl; // 0xbf802b20 0x48 712 #define TSP_IDR_START 0x0001 713 #define TSP_IDR_READ 0x0000 714 #define TSP_IDR_WRITE 0x0002 715 #define TSP_IDR_WR_ENDIAN_BIG 0x0004 716 #define TSP_IDR_WR_ADDR_AUTO_INC 0x0008 // Set 1 to enable address auto-increment after finishing read/write 717 #define TSP_IDR_WDAT0_TRIG_EN 0x0010 // WDAT0_TRIG_EN 718 #define TSP_IDR_MCUWAIT 0x0020 719 #define TSP_IDR_SOFT_RST 0x0080 // Set 1 to soft-reset the IND32 module 720 #define TSP_IDR_AUTO_INC_VAL_MASK 0x0F00 721 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8 722 723 REG32 Idr_Addr; // 0xbf802b24 0x49 724 REG32 Idr_Write; // 0xbf802b2c 0x4b 725 REG32 Idr_Read; // 0xbf802b34 0x4d 726 727 REG16 Fifo_Status; // 0xbf802b3c 0x4f 728 #define TSP_V3D_FIFO_DISCON 0x0010 729 #define TSP_V3D_FIFO_OVERFLOW 0x0020 730 #define TSP_VD_FIFO_DISCON 0x0200 731 #define TSP_VD_FIFO_OVERFLOW 0x0800 732 #define TSP_AUB_FIFO_OVERFLOW 0x1000 733 #define TSP_AU_FIFO_OVERFLOW 0x2000 734 735 // only 25 bits supported in PVR address. 8 bytes address 736 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFF 737 REG32 TsRec_Head; // 0xbf802b40 0x50 738 REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid address & write point 739 REG32 TsRec_Tail; // 0xbf802b50 0x54 740 REG32 _xbf802b58[2]; // 0xbf802b58 ~ 0xbf802b60 0x56~0x59 741 742 REG16 reg15b4; // 0xbf802b68 0x5a 743 #define TSP_VQ_DMAW_PROTECT_EN 0x0001 744 #define TSP_SEC_CB_PVR2_DAMW_PROTECT_EN 0x0002 745 #define TSP_PVR_PID_BYPASS 0x0008 // Set 1 to bypass PID in record 746 #define TSP_PVR_PID_BYPASS2 0x0010 // Set 1 to bypass PID in record2 747 #define TSP_BD_AUD_EN 0x0020 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 748 #define TSP_BD2_AUD_EN 0x0200 // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) 749 #define TSP_AVFIFO_RD_EN 0x0080 // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 750 #define TSP_AVFIFO_RD 0x0100 // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 751 #define TSP_NMATCH_DISABLE 0x0800 752 #define TSP_PVR_INVERT 0x1000 // Set 1 to enable data payload invert for PVR record 753 #define TSP_PLY_FILE_INV_EN 0x2000 // Set 1 to enable data payload invert in pidflt0 file path 754 #define TSP_PLY_TS_INV_EN 0x4000 // Set 1 to enable data payload invert in pidflt0 TS path 755 #define TSP_FILEIN_BYTETIMER_ENABLE 0x8000 // Set 1 to enable byte timer in ts_if0 TS path 756 757 REG16 reg15b8; // 0xbf802b6C 0x5b 758 #define TSP_PVR1_PINGPONG 0x0001 // Set 1 to enable MIU addresses with pinpon mode 759 #define TSP_VQ_STATUS_SEL 0x0002 760 #define TSP_TEI_SKIPE_PKT_PID0 0x0004 // Set 1 to skip error packets in pidflt0 TS path 761 #define TSP_TEI_SKIPE_PKT_PID4 0x0008 // Set 1 to skip error packets in pidflt4 TS path 762 #define TSP_TEI_SKIPE_PKT_PID1 0x0010 // Set 1 to skip error packets in pidflt1 TS path 763 #define TSP_TEI_SKIPE_PKT_PID3 0x0020 // Set 1 to skip error packets in pidflt3 TS path 764 #define TSP_REMOVE_DUP_AV_PKT 0x0040 // Set 1 to remove duplicate A/V packet 765 #define TSP_64bit_PCR2_ld 0x0080 766 #define TSP_cnt_33b_ld 0x0100 767 #define TSP_FORCE_SYNCBYTE 0x0200 // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 768 #define TSP_SERIAL_EXT_SYNC_1T 0x0400 // Set 1 to detect serial-in sync without 8-cycle mode 769 #define TSP_BURST_LEN_MASK 0x1800 // 00,01: burst length = 4; 10,11: burst length = 1 770 #define TSP_BURST_LEN_SHIFT 11 771 #define TSP_MATCH_PID_SRC_MASK 0xE000 // Select the source of pid filter number with hit pid and match pid number with scramble information, 00 : from pkt_demux0, 01 : from pkt_demux_file, 10 : from pkt_demux1, 11 : from pkt_demux2 772 #define TSP_MATCH_PID_SRC_SHIFT 13 773 #define TSP_MATCH_PID_SRC_PKTDMX0 0 774 #define TSP_MATCH_PID_SRC_PKTDMX1 1 775 #define TSP_MATCH_PID_SRC_PKTDMX2 2 776 #define TSP_MATCH_PID_SRC_PKTDMX3 3 777 #define TSP_MATCH_PID_SRC_PKTDMX4 4 778 #define TSP_MATCH_PID_SRC_PKTDMX5 5 779 #define TSP_MATCH_PID_SRC_PKTDMX6 6 780 781 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 782 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 783 784 REG32 Cpu_Base; // 0xbf802b80 0x60 785 #define TSP_CPU_BASE_ADDR_MASK 0x0FFFFFFF 786 787 REG32 Qmem_Ibase; // 0xbf802b88 0x62 788 REG32 Qmem_Imask; // 0xbf802b90 0x64 789 REG32 Qmem_Dbase; // 0xbf802b98 0x66 790 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 791 792 REG32 TSP_Debug; // 0xbf802ba8 0x6a 793 #define TSP_DEBUG_MASK 0x00FFFFFF 794 795 REG32 _xbf802bb0; // 0xbf802bb0 0x6c 796 797 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 798 #define TSP_FILE_RPTR_MASK 0x0FFFFFFF 799 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 800 #define TSP_FILE_TIMER_MASK 0x00FFFFFF 801 REG32 TsFileIn_Head; // 0xbf802bc8 0x72 802 #define TSP_FILE_ADDR_MASK 0x0FFFFFFF 803 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 804 805 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 806 807 REG16 Dnld_Ctrl_Addr; // 0xbf802be0 0x78 808 #define TSP_DNLD_ADDR_MASK 0xFFFF 809 #define TSP_DNLD_ADDR_SHFT 0 810 #define TSP_DNLD_ADDR_ALI_SHIFT 4 // Bit [11:4] of DMA_RADDR[19:0] 811 812 REG16 Dnld_Ctrl_Size; // 0xbf802be4 0x79 813 #define TSP_DNLD_NUM_MASK 0xFFFF 814 #define TSP_DNLD_NUM_SHFT 0 815 816 REG16 TSP_Ctrl; // 0xbf802be8 0x7a 817 #define TSP_CTRL_CPU_EN 0x0001 818 #define TSP_CTRL_SW_RST 0x0002 819 #define TSP_CTRL_DNLD_START 0x0004 820 #define TSP_CTRL_DNLD_DONE 0x0008 // See 0x78 for related information 821 #define TSP_CTRL_TSFILE_EN 0x0010 822 #define TSP_CTRL_R_PRIO 0x0020 823 #define TSP_CTRL_W_PRIO 0x0040 824 #define TSP_CTRL_ICACHE_EN 0x0100 825 #define TSP_CTRL_CPU2MI_R_PRIO 0x0400 826 #define TSP_CTRL_CPU2MI_W_PRIO 0x0800 827 #define TSP_CTRL_I_EL 0x0000 828 #define TSP_CTRL_I_BL 0x1000 829 #define TSP_CTRL_D_EL 0x0000 830 #define TSP_CTRL_D_BL 0x2000 831 #define TSP_CTRL_NOEA_QMEM_ACK_DIS 0x4000 832 #define TSP_CTRL_MEM_TS_WORDER 0x8000 833 834 REG16 TSP_SyncByte; // 0xbf802bec 0x7b 835 #define TSP_SYNC_BYTE_MASK 0x00FF 836 #define TSP_SYNC_BYTE_SHIFT 0 837 838 REG16 PKT_CNT; // 0xbf802bf0 0x7c 839 #define TSP_PKT_CNT_MASK 0x00FF 840 841 REG16 DBG_SEL; // 0xbf802bf4 0x7d 842 #define TSP_DBG_SEL_MASK 0xFFFF 843 #define TSP_DBG_SEL_SHIFT 0 844 845 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 846 /* 847 6: DMA read done 848 5: HK_INT_FORCE. // it's trigger bit is at bank 15 39 bit[15] 849 4: STR2MI_WADR meets STR2MI_MID. 850 3: STR2MI_WADR meets STR2MI_TAIL. 851 2: dma_status1 852 1: dma_status2 853 0: dma_status3 854 */ 855 #define TSP_HWINT_EN_MASK 0x00FF // Tsp2hk_int enable bits. 856 #define TSP_HWINT_EN_SHIFT 0 857 #define TSP_HWINT_DMA_STATUS3_EN 0x0001 // currently not used in ISR 858 #define TSP_HWINT_DMA_STATUS2_EN 0x0002 // currently not used in ISR 859 #define TSP_HWINT_DMA_STATUS1_EN 0x0004 // currently not used in ISR 860 #define TSP_HWINT_TSP_FILEIN_MID_INT_EN 0x0008 // currently not used in ISR 861 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_EN 0x0010 // currently not used in ISR 862 #define TSP_HWINT_TSP_SW_INT_EN 0x0020 863 #define TSP_HWINT_TSP_DMA_READ_DONE_EN 0x0040 // currently not used in ISR 864 #define TSP_HWINT_PVR (TSP_HWINT_TSP_FILEIN_MID_INT_EN | TSP_HWINT_TSP_FILEIN_TAIL_INT_EN) 865 #define TSP_HWINT_TSP_SUPPORT_ALL (TSP_HWINT_TSP_SW_INT_EN) 866 #define TSP_HWINT_ALL TSP_HWINT_TSP_SUPPORT_ALL 867 868 #define TSP_HWINT_STATUS_MASK 0xFF00 869 #define TSP_HWINT_STATUS_SHIFT 8 870 #define TSP_HWINT_DMA_STATUS3_STATUS 0x0100 871 #define TSP_HWINT_DMA_STATUS2_STATUS 0x0200 872 #define TSP_HWINT_DMA_STATUS1_STATUS 0x0400 873 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800 874 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000 875 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000 876 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000 877 878 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 879 // 0x7f: TSP_CTRL1: hidden in HwInt_Stat 880 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001 881 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002 //Set 1 to enable TSP file data read without timer check 882 #define TSP_CTRL1_FILEIN_PAUSE 0x0004 //Set 1 to pause file-in engine fetch data 883 #define TSP_CTRL1_FILE_CHECK_WP 0x0008 884 #define TSP_CTRL1_FILE_WP_SEL_MASK 0x0030 885 #define TSP_CTRL1_FILE_WP_FI 0x0010 886 #define TSP_CTRL1_FILE_WP_PVR 0x0020 887 #define TSP_CTRL1_STANDBY 0x0080 888 #define TSP_CTRL1_INT2NOEA 0x0100 889 #define TSP_CTRL1_INT2NOEA_FORCE 0x0200 890 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400 891 #define TSP_CTRL1_CMDQ_RESET 0x0800 892 #define TSP_CTRL1_DLEND_EN 0x1000 // Set 1 to enable little-endian mode in TSP CPU 893 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000 894 #define TSP_CTRL1_FILEIN_RADDR_READ 0x4000 895 #define TSP_CTRL1_DMA_RST 0x8000 896 897 //---------------------------------------------- 898 // 0xBF802C00 MIPS direct access 899 //---------------------------------------------- 900 REG32 MCU_Data0; // 0xbf802c00 0x00 901 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 902 903 REG32 PVR1_LPcr1; // 0xbf802c08 0x02 904 REG32 LPcr2; // 0xbf802c10 0x04 905 906 REG16 reg160C; // 0xbf802c18 0x06 907 #define TSP_PVR1_LPCR1_WLD 0x0001 // Set 1 to load LPCR1 value (Default: 0) 908 #define TSP_PVR1_LPCR1_RLD 0x0002 // Set 1 to read LPCR1 value (Default: 1) 909 #define TSP_LPCR2_WLD 0x0004 // Set 1 to load LPCR2 value (Default: 0) 910 #define TSP_LPCR2_RLD 0x0008 // Set 1 to read LPCR2 value (Default: 1) 911 #define TSP_RECORD192_EN 0x0010 // 160C bit(5)enable TS packets with 192 bytes on record mode 912 #define TSP_FILEIN192_EN 0x0020 // 160C bit(5)enable TS packets with 192 bytes on file-in mode 913 #define TSP_ORZ_DMAW_PROT_EN 0x0080 // 160C bit(7) open RISC DMA write protection 914 #define TSP_CLR_PIDFLT_BYTE_CNT 0x0100 // Clear pidflt0_file byte counter 915 #define TSP_DOUBLE_BUF_DESC 0x4000 // 160d bit(6) remove buffer limitation, Force pinpong buffer to flush 916 #define TSP_TIMESTAMP_RESET 0x8000 // 160d bit(7) reset timestamp 917 918 REG16 reg160E; // 0xbf802c1C 0x07 919 #define TSP_VQTX0_BLOCK_DIS 0x0001 920 #define TSP_VQTX1_BLOCK_DIS 0x0002 921 #define TSP_VQTX2_BLOCK_DIS 0x0004 922 #define TSP_VQTX3_BLOCK_DIS 0x0008 923 #define TSP_DIS_MIU_RQ 0x0010 // Disable miu R/W request for reset TSP usage 924 #define TSP_RM_DMA_GLITCH 0x0080 // Fix sec_dma overflow glitch 925 #define TSP_RESET_VFIFO 0x0100 // Reset VFIFO -- ECO Done 926 #define TSP_RESET_AFIFO 0x0200 // Reset AFIFO -- ECO Done 927 #define TSP_RESET_AFIFO3 0x0400 // Reset AFIFOC -- ECO Done 928 #define TSP_CLR_ALL_FLT_MATCH 0x0800 // Set 1 to clean all flt_match in a packet 929 #define TSP_RESET_AFIFO2 0x1000 930 #define TSP_RESET_VFIFO3D 0x2000 931 #define TSP_PVR_WPRI_HIGH 0x4000 932 #define TSP_OPT_ORACESS_TIMING 0x8000 933 934 REG16 PktChkSizeFilein; // 0xbf802c20 0x08 935 #define TSP_PKT_SIZE_MASK 0x00ff 936 #define TSP_PKT192_BLK_DIS_FIN 0x0100 // Set 1 to disable file-in timestamp block scheme 937 #define TSP_AV_CLR 0x0200 // Clear AV FIFO overflow flag and in/out counter 938 #define TSP_HW_STANDBY_MODE 0x0400 // Set 1 to disable all SRAM in TSP for low power mode automatically 939 #define TSP_RESET_AFIFO4 0x4000 // Reset AFIFOC -- ECO Done 940 941 REG16 TSP_Cfg5; // 0xbf802c24 0x09 942 #define TSP_PREVENT_OVF_META 0x0001 943 #define TSP_OVF_META_SEL 0x0004 944 #define TSP_SYSTIME_MODE 0x0008 945 #define TSP_SEC_DMA_BURST_EN 0x0080 // Enable Section DMA burst 946 947 REG16 Dnld_AddrH; // 0xbf802c28 0x0a 948 #define TSP_DMA_RADDR_MSB_MASK 0x00FF 949 #define TSP_DMA_RADDR_MSB_SHIFT 0 950 951 REG16 TSP_Ctrl2; // 0xbf802c2c 0x0b 952 #define TSP_CMQ_WORD_EN 0x0040 // Set 1 to access CMDQ related registers in word. 953 #define TSP_AV_DIRECT_STOP 0x0080 //Set 1 to enable A/V fifo full pull back tsif0 file in 954 #define TSP_AV_DIRECT_STOP1 0x0100 //Set 1 to enable A/V fifo full pull back tsif1 file in 955 #define TSP_AV_DIRECT_STOP2 0x0200 //Set 1 to enable A/V fifo full pull back tsif2 file in 956 #define TSP_AV_DIRECT_STOP3 0x0400 //Set 1 to enable A/V fifo full pull back tsif3 file in 957 #define TSP_TS_OUT_EN 0x1000 // TS_CB out enable. for Serial input to parallel output 958 #define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D path in program stream mode 959 960 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 961 REG32 TsPidScmbStatFile; // 0xbf802c38 0x0e 962 963 REG32 PCR64_2_L; // 0xbf802c40 0x10 964 REG32 PCR64_2_H; // 0xbf802c48 0x12 965 #define TSP_DMAW_BND_MASK 0xFFFFFFFFUL 966 967 REG32 DMAW_LBND0; // 0xbf802c50 0x14 //sec1 protect 968 REG32 DMAW_UBND0; // 0xbf802c58 0x16 969 REG32 DMAW_LBND1; // 0xbf802c60 0x18 //sec2 protect 970 REG32 DMAW_UBND1; // 0xbf802c68 0x1A 971 972 REG32 HW2_CFG6; // 0xbf802c68 0x1C 973 REG32 HW2_CFG5; // 0xbf802c68 0x1E 974 975 REG32 VQ0_BASE; // 0xbf802c80 0x20 976 REG16 VQ0_SIZE; // 0xbf802c84 0x22 977 #define TSP_VQ0_SIZE_208PK_MASK 0xFFFF 978 #define TSP_VQ0_SIZE_208PK_SHIFT 0 979 980 REG16 VQ0_CTRL; // 0xbf802c88 0x23 981 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F 982 #define TSP_VQ0_WR_THRESHOLD_SHIFT 0 983 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F0 984 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 4 985 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F00 986 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 8 987 #define TSP_VQ0_RESET 0x1000 988 #define TSP_VQ0_OVERFLOW_INT_EN 0x4000 // Enable the interrupt for overflow happened on Virtual Queue path 989 #define TSP_VQ0_CLR_OVERFLOW_INT 0x8000 // Clear the interrupt and the overflow flag 990 991 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 992 993 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x000E 994 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 1 995 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x0000 996 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x0002 997 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x0004 998 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x0006 999 #define TSP_PIDFLT0_OVF_INT_EN 0x0040 1000 #define TSP_PIDFLT0_CLR_OVF_INT 0x0080 1001 #define TSP_PIDFLT1_OVF_INT_EN 0x0100 1002 #define TSP_PIDFLT1_CLR_OVF_INT 0x0200 1003 #define TSP_PIDFLT2_OVF_INT_EN 0x0400 1004 #define TSP_PIDFLT2_CLR_OVF_INT 0x0800 1005 1006 REG16 _xbf202c94 ; // 0xbf802c94 0x25 1007 1008 REG16 MOBF_PVR1_Index[2]; // 0xbf3a2c98 0x26 1009 #define TSP_MOBF_PVR1_INDEX_MASK 0x0000001F 1010 #define TSP_MOBF_PVR1_INDEX_SHIFT 0 1011 REG16 MOBF_PVR2_Index[2]; // 0xbf3a2cA0 0x28 1012 #define TSP_MOBF_PVR2_INDEX_MASK 0x0000001F 1013 #define TSP_MOBF_PVR2_INDEX_SHIFT 0 1014 1015 REG32 DMAW_LBND2; // 0xbf802ca8 0x2a //PVR protect 1016 #define TSP_PVR_MASK 0x0FFFFFFFUL 1017 REG32 DMAW_UBND2; // 0xbf802cb0 0x2c 1018 REG32 DMAW_LBND3; // 0xbf802cb8 0x2e //PVR 2 protect 1019 REG32 DMAW_UBND3; // 0xbf802cc0 0x30 1020 REG32 DMAW_LBND4; // 0xbf802cc8 0x32 //PVR 3 protect 1021 REG32 DMAW_UBND4; // 0xbf802cd0 0x34 1022 1023 REG32 ORZ_DMAW_LBND; // 0xbf802cd8 0x36 //CPU protect 1024 #define TSP_ORZ_DMAW_LBND_MASK 0xffffffffUL //protect address is base on MIU unit (16byte aligment) 1025 REG32 ORZ_DMAW_UBND; // 0xbf802ce0 0x38 1026 #define TSP_ORZ_DMAW_UBND_MASK 0xffffffffUL 1027 1028 REG16 PIDFLT_PCR0; // 0xbf802ce8 0x3a 1029 #define TSP_PIDFLT_PCR0_PID_MASK 0x1fff 1030 #define TSP_PIDFLT_PCR0_EN 0x8000 1031 1032 REG16 PIDFLT_PCR1; // 0xbf802ce8 0x3b 1033 #define TSP_PIDFLT_PCR1_PID_MASK 0x1fff 1034 #define TSP_PIDFLT_PCR1_EN 0x8000 1035 1036 REG32 HWPCR0_L; // 0xbf802cf0 0x3c 1037 REG32 HWPCR0_H; // 0xbf802cf8 0x3e 1038 1039 REG32 CA_CTRL; // 0xbf802d00 0x40 1040 #define TSP_CA_CTRL_MASK 0xffffffff 1041 #define TSP_CA0_INPUT_TSIF0_LIVEIN 0x00000001 1042 #define TSP_CA0_INPUT_TSIF0_FILEIN 0x00000002 1043 #define TSP_CA0_INPUT_TSIF1 0x00000004 1044 #define TSP_CA0_AVPAUSE 0x00000008 1045 #define TSP_CA0_OUTPUT_PKTDMX0_LIVE 0x00000010 1046 #define TSP_CA0_OUTPUT_PKTDMX0_FILE 0x00000020 1047 #define TSP_CA0_OUTPUT_PKTDMX1 0x00000040 //pkt_demux1 1048 #define TSP_CA0_INPUT_TSIF2 0x00001000 1049 #define TSP_CA0_OUTPUT_PKTDMX2 0x00002000 //pkt_demux2 1050 #define TSP_CA2_INPUT_TSIF2 0x00100000 1051 #define TSP_CA2_OUTPUT_REC2 0x00200000 //pkt_demux2 1052 #define TSP_CA2_INPUT_TSIF0_LIVEIN 0x01000000 1053 #define TSP_CA2_INPUT_TSIF0_FILEIN 0x02000000 1054 #define TSP_CA2_INPUT_TSIF1 0x04000000 1055 #define TSP_CA2_OUTPUT_PLAY_LIVE 0x10000000 1056 #define TSP_CA2_OUTPUT_PLAY_FILE 0x20000000 1057 #define TSP_CA2_OUTPUT_REC1 0x40000000 //pkt_demux1 1058 1059 REG16 OneWay; // 0xbf802d08 0x42 , 1060 #define TSP_ONEWAY_CAREC_DISABLE 0x0001 1061 #define TSP_ONEWAY_PVR 0x0002 1062 #define TSP_ONEWAY_PVR1 0x0004 1063 #define TSP_ONEWAY_FW 0x0008 1064 #define TSP_ONEWAY_QMEM 0x0010 1065 #define TSP_ONEWAY_PVR2 0x0020 1066 #define TSP_ONEWAY_FIQ 0x0040 1067 1068 REG16 _xbf202d0C; // 0xbf802d0C 0x43 1069 1070 REG32 HWPCR1_L; // 0xbf802d10 0x44 1071 REG32 HWPCR1_H; // 0xbf802d18 0x46 1072 1073 REG16 IND32_CMD; // 0xbf802d20 0x48 1074 REG32 IND32_ADDR; // 0xbf802d24 0x49, Indirect address to TSP CPU 1075 REG32 IND32_WDATA; // 0xbf802d2C 0x4B, Indirect write data to TSP CPUr 1076 REG32 IND32_RDATA; // 0xbf802d34 0x4D, IND32_WDATA 1077 1078 REG16 _xbf202d3c; // 0xbf802d3C 0x4F 1079 1080 REG16 FIFO_Src; // 0xbf802d40 0x50 1081 #define TSP_AUD_SRC_MASK 0x0007 1082 #define TSP_AUD_SRC_SHIFT 0 1083 #define TSP_AUDB_SRC_MASK 0x0038 1084 #define TSP_AUDB_SRC_SHIFT 3 1085 #define TSP_VID_SRC_MASK 0x01C0 1086 #define TSP_VID_SRC_SHIFT 6 1087 #define TSP_VID3D_SRC_MASK 0x0E00 1088 #define TSP_VID3D_SRC_SHIFT 9 1089 #define TSP_PVR1_SRC_MASK 0x7000 1090 #define TSP_PVR1_SRC_SHIFT 12 1091 #define TSP_PVR2_SRC_MASK_L 0x8000 1092 #define TSP_PVR2_SRC_SHIFT_L 15 1093 1094 REG16 PCR_Cfg; // 0xbf802d44 0x51 1095 #define TSP_PVR2_SRC_MASK_H 0x0003 1096 #define TSP_PVR2_SRC_SHIFT_H 0 1097 #define TSP_AUDC_SRC_MASK 0x001C 1098 #define TSP_AUDC_SRC_SHIFT 2 1099 #define TSP_AUDD_SRC_MASK 0x00E0 1100 #define TSP_AUDD_SRC_SHIFT 5 1101 #define TSP_TEI_SKIP_PKT_PCR0 0x0100 1102 #define TSP_PCR0_RESET 0x0200 1103 #define TSP_PCR0_INT_CLR 0x0400 1104 #define TSP_PCR0_READ 0x0800 1105 #define TSP_TEI_SKIP_PKT_PCR1 0x1000 1106 #define TSP_PCR1_RESET 0x2000 1107 #define TSP_PCR1_INT_CLR 0x4000 1108 #define TSP_PCR1_READ 0x8000 1109 1110 REG32 STC_DIFF_BUF; // 0xbf802d48 0x52 1111 1112 REG32 STC_DIFF_BUF_H; // 0xbf802d50 0x54 1113 #define TSP_STC_DIFF_BUF_H_MASK 0x0000000F 1114 #define TSP_STC_DIFF_BUF_H_AHIFT 0 1115 1116 REG32 VQ1_Base; // 0xbf802d58 0x56 1117 1118 REG32 _xbf202d60_6C[2]; // 0xbf802d60 0x58~0x5B 1119 1120 REG16 VQ1_Size; // 0xbf802d70 0x5C 1121 #define TSP_VQ1_SIZE_208PK_MASK 0xffff 1122 #define TSP_VQ1_SIZE_208PK_SHIFT 0 1123 1124 REG16 VQ1_Config; // 0xbf802d74 0x5d 1125 #define TSP_VQ1_WR_THRESHOLD_MASK 0x000F 1126 #define TSP_VQ1_WR_THRESHOLD_SHIFT 0 1127 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x00F0 1128 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 4 1129 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x0F00 1130 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 8 1131 #define TSP_VQ1_RESET 0x1000 1132 #define TSP_VQ1_OVF_INT_EN 0x4000 1133 #define TSP_VQ1_CLR_OVF_INT 0x8000 1134 1135 REG32 VQ2_Base; // 0xbf802d78 0x5E 1136 1137 REG32 TS_WatchDog_Cnt; // 0xbf802d80 0x60 1138 #define TSP_TS_WATCH_DOG_MASK 0xFFFF0000 1139 #define TSP_TS_WATCH_DOG_SHIFT 16 1140 1141 REG32 Bist_Fail; // 0xbf802d88 0x62 1142 #define TSP_BIST_FAIL_STATUS_MASK 0x00FF0000 1143 #define TSP_BIST_FAIL_STATUS_SRAM1P192x8_MASK 0x00070000 1144 #define TSP_BIST_FAIL_STATUS_SRAM2P512x32w8 0x00080000 1145 #define TSP_BIST_FAIL_STATUS_SRAM2P16x128_MASK 0x00600000 1146 #define TSP_BIST_FAIL_STATUS_SRAM1P2048x32w8 0x00800000 1147 #define TSP_BIST_FAIL_STATUS_SRAM1P1024x32w8 0x01000000 1148 #define TSP_BIST_FAIL_STATUS_SRAM1P512x20 0x00200000 1149 1150 REG16 VQ2_Size; // 0xbf802d90 0x64 1151 #define TSP_VQ2_SIZE_208PK_MASK 0xffff 1152 #define TSP_VQ2_SIZE_208PK_SHIFT 0 1153 1154 REG16 VQ2_Config; // 0xbf802d90 0x65 1155 #define TSP_VQ2_WR_THRESHOLD_MASK 0x000F 1156 #define TSP_VQ2_WR_THRESHOLD_SHIFT 0 1157 #define TSP_VQ2_PRI_THRESHOLD_MASK 0x00F0 1158 #define TSP_VQ2_PRI_THRESHOLD_SHIFT 4 1159 #define TSP_VQ2_FORCEFIRE_CNT_1K_MASK 0x0F00 1160 #define TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT 8 1161 #define TSP_VQ2_RESET 0x1000 1162 #define TSP_VQ2_OVF_INT_EN 0x4000 1163 #define TSP_VQ2_CLR_OVF_INT 0x8000 1164 1165 REG32 VQ_STATUS; // 0xbf802d98 0x66 1166 #define TSP_VQ_STATUS_MASK 0xFFFFFFFF 1167 #define TSP_VQ_STATUS_SHIFT 0 1168 #define TSP_VQ0_STATUS_READ_EVER_FULL 0x00001000 1169 #define TSP_VQ0_STATUS_READ_EVER_OVERFLOW 0x00002000 1170 #define TSP_VQ0_STATUS_EMPTY 0x00004000 1171 #define TSP_VQ0_STATUS_READ_BUSY 0x00008000 1172 #define TSP_VQ1_STATUS_READ_EVER_FULL 0x00010000 1173 #define TSP_VQ1_STATUS_READ_EVER_OVERFLOW 0x00020000 1174 #define TSP_VQ1_STATUS_EMPTY 0x00040000 1175 #define TSP_VQ1_STATUS_READ_BUSY 0x00080000 1176 #define TSP_VQ2_STATUS_READ_EVER_FULL 0x00100000 1177 #define TSP_VQ2_STATUS_READ_EVER_OVERFLOW 0x00200000 1178 #define TSP_VQ2_STATUS_EMPTY 0x00400000 1179 #define TSP_VQ2_STATUS_READ_BUSY 0x00800000 1180 #define TSP_VQ0_STATUS_TX_OVERFLOW 0x10000000 1181 #define TSP_VQ1_STATUS_TX_OVERFLOW 0x20000000 1182 #define TSP_VQ2_STATUS_TX_OVERFLOW 0x40000000 1183 1184 REG32 DM2MI_WAddr_Err; // 0xbf802da0 0x68 , DM2MI_WADDR_ERR0 1185 1186 REG32 ORZ_DMAW_WAddr_Err; // 0xbf802da8 0x6a , ORZ_WADDR_ERR0 1187 1188 REG16 HwInt2_Stat; // 0xbf802dB0 0x6c 1189 /* 1190 [5] : OTV HW interrupt 1191 [4] : all DMA write address not in the protect zone interrupt 1192 [3] : vq0~vq6 overflow interrupt 1193 [2] : aud_err 1194 [1] : vid_err 1195 [0] : reg_hk_int_force (it's trigger bit is at bank 15 44 bit[15]) 1196 */ 1197 #define TSP_HWINT2_EN_MASK 0x00FF 1198 #define TSP_HWINT2_EN_SHIFT 0 1199 #define TSP_HWINT2_TSP_HK_INT_FORCE_EN 0x0001 // currently not used in ISR 1200 #define TSP_HWINT2_TSP_VID_PKT_ERR_EN 0x0002 // currently not used in ISR 1201 #define TSP_HWINT2_TSP_AUD_PKT_ERR_EN 0x0004 // currently not used in ISR 1202 #define TSP_HWINT2_VQ0_TO_VQ6_OVERFLOW_EN 0x0008 // currently not used in ISR 1203 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z_EN 0x0010 // currently not used in ISR 1204 #define TSP_HWINT2_OTV_EN 0x0020 1205 #define TSP_HWINT2_SUPPORT_ALL 0x0000 1206 #define TSP_HWINT2_ALL TSP_HWINT2_SUPPORT_ALL 1207 1208 #define TSP_HWINT2_STATUS_MASK 0xFF00 1209 #define TSP_HWINT2_STATUS_SHIFT 8 1210 #define TSP_HWINT2_TSP_HK_INT_FORCE_STATUS 0x0100 1211 #define TSP_HWINT2_TSP_VID_PKT_ERR 0x0200 1212 #define TSP_HWINT2_TSP_AUD_PKT_ERR 0x0400 1213 #define TSP_HWINT2_VQ0_TO_VQ6_OVERFLOW 0x0800 1214 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z 0x1000 1215 #define TSP_HWINT2_OTV 0x2000 1216 1217 REG32 SwInt2_Stat; // 0xbf802dB4 0x6d 1218 REG16 HwInt3_Stat; // 0xbf802dBC 0x6f 1219 /* 1220 [7] : pcr filter 7 update finish 1221 [6] : pcr filter 6 update finish 1222 [5] : pcr filter 5 update finish 1223 [4] : pcr filter 4 update finish 1224 [3] : pcr filter 3 update finish 1225 [2] : pcr filter 2 update finish 1226 [1] : pcr filter 1 update finish 1227 [0] : pcr filter 0 update finish 1228 */ 1229 #define TSP_HWINT3_EN_MASK 0x00FF 1230 #define TSP_HWINT3_EN_SHIFT 0 1231 #define TSP_HWINT3_PCR0_UPDATE_END_EN 0x0001 1232 #define TSP_HWINT3_PCR1_UPDATE_END_EN 0x0002 1233 #define TSP_HWINT3_PCR2_UPDATE_END_EN 0x0004 1234 #define TSP_HWINT3_PCR3_UPDATE_END_EN 0x0008 1235 #define TSP_HWINT3_PCR4_UPDATE_END_EN 0x0010 1236 #define TSP_HWINT3_PCR5_UPDATE_END_EN 0x0020 1237 #define TSP_HWINT3_PCR6_UPDATE_END_EN 0x0040 1238 #define TSP_HWINT3_PCR7_UPDATE_END_EN 0x0080 1239 #define TSP_HWINT3_SUPPORT_ALL 0x00FF 1240 #define TSP_HWINT3_ALL TSP_HWINT3_SUPPORT_ALL 1241 1242 #define TSP_HWINT3_STATUS_MASK 0xFF00 1243 #define TSP_HWINT3_STATUS_SHIFT 8 1244 #define TSP_HWINT3_PCR0_UPDATE_END 0x0100 1245 #define TSP_HWINT3_PCR1_UPDATE_END 0x0200 1246 #define TSP_HWINT3_PCR2_UPDATE_END 0x0400 1247 #define TSP_HWINT3_PCR3_UPDATE_END 0x0800 1248 #define TSP_HWINT3_PCR4_UPDATE_END 0x1000 1249 #define TSP_HWINT3_PCR5_UPDATE_END 0x2000 1250 #define TSP_HWINT3_PCR6_UPDATE_END 0x4000 1251 #define TSP_HWINT3_PCR7_UPDATE_END 0x8000 1252 1253 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 1254 1255 REG16 HW2_Config3; // 0xbf802dC8 0x72 1256 #define TSP_PVR_DMAW_PROTECT_EN 0x0001 1257 #define TSP_WADDR_ERR_SRC_SEL_MASK 0x0006 1258 #define TSP_WADDR_ERR_SRC_SEL_SHIFT 1 1259 #define TSP_WADDR_ERR_SRC_PVR 0x0000 1260 #define TSP_WADDR_ERR_SRC_VQ 0x0002 1261 #define TSP_WADDR_ERR_SRC_SEC_CB 0x0004 1262 #define TSP_RM_OVF_GLITCH 0x0008 1263 #define TSP_FILEIN_RADDR_READ 0x0010 1264 #define TSP_DUP_PKT_CNT_CLR 0x0040 1265 #define TSP_DMA_FLUSH_EN 0x0080 //PVR1, PVR2 dma flush 1266 #define TSP_REC_AT_SYNC_DIS 0x0100 1267 #define TSP_PVR1_ALIGN_EN 0x0200 1268 #define TSP_REC_FORCE_SYNC_EN 0x0400 1269 #define TSP_RM_PKT_DEMUX_PIPE 0x0800 1270 #define TSP_VQ_EN 0x4000 1271 #define TSP_VQ2PINGPONG_EN 0x8000 1272 1273 REG16 PVRConfig; // 0xbf802dCC 0x73 1274 #define TSP_PVR1_REC_ALL_EN 0x0001 1275 #define TSP_PVR2_REC_ALL_EN 0x0002 1276 #define TSP_REC_NULL 0x0004 1277 #define TSP_REC_ALL_OLD 0x0008 1278 #define TSP_MATCH_PID_SEL_MASK 0x1F00 1279 #define TSP_MATCH_PID_SEL_SHIFT 8 1280 #define TSP_MATCH_PID_LD 0x8000 1281 1282 REG32 VQ3_Base; // 0x74~75 1283 REG16 VQ3_Size; // 0x76 1284 #define TSP_VQ3_SIZE_208PK_MASK 0xffff 1285 #define TSP_VQ3_SIZE_208PK_SHIFT 0 1286 1287 REG16 VQ3_Config; //0x77 1288 #define TSP_VQ3_WR_THRESHOLD_MASK 0x000F 1289 #define TSP_VQ3_WR_THRESHOLD_SHIFT 0 1290 #define TSP_VQ3_PRI_THRESHOLD_MASK 0x00F0 1291 #define TSP_VQ3_PRI_THRESHOLD_SHIFT 4 1292 #define TSP_VQ3_FORCEFIRE_CNT_1K_MASK 0x0F00 1293 #define TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT 8 1294 #define TSP_VQ3_RESET 0x1000 1295 #define TSP_VQ3_OVF_INT_EN 0x4000 1296 #define TSP_VQ3_CLR_OVF_INT 0x8000 1297 1298 REG32 VQ_RX_Status; // 0xbf802de0 0x78 1299 #define VQ_RX_ARBITER_MODE_MASK 0x0000000F 1300 #define VQ_RX_ARBITER_MODE_SHIFT 0 1301 #define VQ_RX0_PRI_MASK 0x000000F0 1302 #define VQ_RX0_PRI_SHIFT 4 1303 #define VQ_RX1_PRI_MASK 0x00000F00 1304 #define VQ_RX1_PRI_SHIFT 8 1305 #define VQ_RX2_PRI_MASK 0x0000F000 1306 #define VQ_RX2_PRI_SHIFT 12 1307 1308 REG32 _xbf802de8; // 0xbf802dC0 0x7a 1309 1310 REG32 MCU_Data1; // 0xbf802dC0 0x7c 1311 } REG_Ctrl; 1312 1313 1314 // TSP_MULTI 1315 #include "regTSP_MULTI.h" 1316 1317 // TSP_SRC 1318 #include "regTSP_SRC.h" 1319 1320 // LIVE-IN 1321 #include "regPATH.h" 1322 1323 // FILE-IN 1324 #include "regFILE.h" 1325 1326 // SPS/SPD 1327 #include "regSPS_SPD.h" 1328 1329 // PVR 1330 #include "regPVR.h" 1331 1332 // AV 1333 #include "regAV.h" 1334 1335 // STC / PCR 1336 #include "regSTC.h" 1337 1338 // Other 1339 #include "regOTHER.h" 1340 1341 // TOP 1342 #include "regTOP.h" 1343 1344 #endif 1345