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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halTSP.c
97 // @brief Transport Stream Processer (TSP) HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "halTSP.h"
101 #include "halCHIP.h"
102
103 //--------------------------------------------------------------------------------------------------
104 // Driver Compiler Option
105 //--------------------------------------------------------------------------------------------------
106 #define TSP_HAL_REG_SAFE_MODE 1UL // Register protection access between 1 task and 1+ ISR
107
108 //[HWBUG]
109 #define MULTI_ACCESS_SW_PATCH 1UL // It's still risk becuase some registers like readaddr will
110
111 // @FIXME: remove the test later
112 #define LINUX_TEST 0UL
113 // cause overflow before patching to correct value.
114 #define MIU_BUS 4UL
115
116 #define VQ_PACKET_UNIT_LEN 192UL //192 bytes
117
118 //--------------------------------------------------------------------------------------------------
119 // TSP Hardware Abstraction Layer
120 //--------------------------------------------------------------------------------------------------
121 static REG_Ctrl* _TspCtrl = NULL; // TSP0 & TSP1
122 static REG_Ctrl2* _TspCtrl2 = NULL; // TSP2
123 static REG_Ctrl3* _TspCtrl3 = NULL; // TSP3
124
125 static MS_VIRT _virtRegBase = 0;
126
127 extern MS_BOOL _bIsHK;
128 static MS_S32 _s32HALTSPMutexId = -1;
129 static MS_BOOL _b64STCMode = FALSE;
130
131 static MS_PHY _phyOrLoadMiuOffset = 0;
132 static MS_PHY _phySecBufMiuOffset = 0;
133 static MS_PHY _phyFIBufMiuOffset = 0;
134 static MS_PHY _phyPVRBufMiuOffset[TSP_PVR_IF_NUM] = {[0 ... (TSP_PVR_IF_NUM-1)] = 0UL};
135
136 static MS_BOOL _bTsPadUsed[TSP_TS_PAD_NUM] = {[0 ... (TSP_TS_PAD_NUM-1)] = FALSE };
137
138 //[NOTE] Jerry
139 // Some register has write order, for example, writing PCR_L will disable PCR counter
140 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
141 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFFUL); \
142 (reg)->H = ((value) >> 16UL); } while(0)
143
144 #define _HAL_REG32L_W(reg, value) (reg)->data = ((value) & 0x0000FFFFUL);
145
146 #define _HAL_REG16_W(reg, value) (reg)->u16data = (value);
147
148
149 #define _HAL_HALTSP_ENTRY() do{ \
150 if(_s32HALTSPMutexId == -1) \
151 _s32HALTSPMutexId = MsOS_CreateMutex(E_MSOS_FIFO, "HALTSP_Mutex", MSOS_PROCESS_SHARED); \
152 }while(0)
153 #define _HAL_HALTSP_EXIT() do{ \
154 if(_s32HALTSPMutexId != -1) \
155 { \
156 MsOS_DeleteMutex(_s32HALTSPMutexId); _s32HALTSPMutexId = -1; \
157 } \
158 }while(0)
159
160 #define _HAL_HALTSP_LOCK() (MsOS_ObtainMutex(_s32HALTSPMutexId, MSOS_WAIT_FOREVER))
161 #define _HAL_HALTSP_UNLOCK() (MsOS_ReleaseMutex(_s32HALTSPMutexId))
162
163 //--------------------------------------------------------------------------------------------------
164 // Macro of bit operations
165 //--------------------------------------------------------------------------------------------------
166 #define HAS_FLAG(flag, bit) ((flag) & (bit))
167 #define SET_FLAG(flag, bit) ((flag)|= (bit))
168 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
169 #define SET_FLAG1(flag, bit) ((flag)| (bit))
170 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
171
172 //#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT)
173 //#define BIT(x) (1<<(x))
174 //#define BMASK(bits) (BIT(((1)?bits)+1)-BIT(((0)?bits)))
175 // #define BMASK_L(bits) (BMASK(bits)&0xFFFF)
176 // #define BMASK_H(bits) (BMASK(bits)>>16)
177 //#define BITS(bits,value) ((BIT(((1)?bits)+1)-BIT(((0)?bits))) & (value<<((0)?bits)))
178
179 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
180
181 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
182 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL
183 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL
184 #define REG_CLKGEN0_STC_CW_EN 0x0004UL
185 #define REG_CLKGEN0_STC_REF_DIV2_EN 0x0008UL
186 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL
187 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL
188
189 #define REG_CLKGEN0_TSN_CLK 0x28UL
190 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL
191 #define REG_CLKGEN0_TSN_CLK_DEMOD 0x1CUL
192 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL
193 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL
194 //#define TSP_CLK_TS0 0
195 //#define TSP_CLK_INDEMOD 7
196 // bit[4:0] -> ts0 -> 0: disable clock
197 // 1: invert clock
198 // bit [4:2] -> 0: TS0
199 // 7: Internal Demmod
200 // bit[12:8] -> ts1 -> 0: disable clock
201 // 1: invert clock
202 // bit [4:2] -> 0: TS0
203 // 7: Internal Demmod
204 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
205 #define REG_TOP_TS0_PE 0x0EUL
206 #define REG_TOP_TS0_PE_MASK 0x07FFUL
207 #define REG_TOP_TS1_PE 0x06UL
208 #define REG_TOP_TS1_PE_MASK 0x07FFUL
209
210 #define REG_TOP_TSN_MUX 0x11UL
211 #define REG_TOP_TSN_MUX_MASK 0x0FUL
212 #define REG_TOP_TSN_MUX_TS0_SHIFT 0UL
213 #define REG_TOP_TSN_MUX_TS1_SHIFT 8UL
214 // bit[3:0] -> ts0 -> 0: TS0
215 // 1: TS1
216 // 7: Demod
217 // bit[10:8] -> ts1 -> 0: TS0
218 // 1: TS1
219 // 7: Demod
220 #define REG_TOP_TSCONFIG 0x57UL
221 #define REG_TOP_TS_TS0_CFG_MASK 0x0700UL
222 #define REG_TOP_TS_TS0_CFG_PARALLEL 0x0100UL
223 #define REG_TOP_TS_TS0_CFG_SERIAL 0x0200UL
224
225 #define REG_TOP_TS_TS1_CFG_MASK 0x3800UL
226 #define REG_TOP_TS_TS1_CFG_PARALLEL 0x0800UL
227 #define REG_TOP_TS_TS1_CFG_SERIAL 0x1800UL
228 // bit[10:8] -> 0: Disable
229 // 1: use all PAD_TS0 pads
230 // 2: e PAD_TS0_VLD, PAD_TS0_SYNC, PAD_TS0_CLK and PAD_TS0_D0 pads
231 // 3: mspi mode
232 // 4: 3 wire mode
233
234 #define ABS_DIFF(x1, x2) (((x1) > (x2))? ((x1) - (x2)) : ((x2) - (x1)))
235 #define IsCover(_start1, _end1, _start2, _end2) (ABS_DIFF(_end1, _end2) < (((_end1) > (_end2))?((_end1)-(_start1)):((_end2)-(_start2))) )?TRUE:FALSE
236 //--------------------------------------------------------------------------------------------------
237 // Forward declaration
238 //--------------------------------------------------------------------------------------------------
239 static void _HAL_TSP_FW_load(
240 MS_PHY phyFwAddrPhys,
241 MS_U32 u32FwSize,
242 MS_BOOL bFwDMA,
243 MS_BOOL bIQmem,
244 MS_BOOL bDQmem);
245
246 static void _HAL_TSP_tsif_select(MS_U8 u8_tsif);
247 // static void _HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 PadId);
248
249 //--------------------------------------------------------------------------------------------------
250 // Implementation
251 //--------------------------------------------------------------------------------------------------
_delay(void)252 static void _delay(void)
253 {
254 volatile MS_U32 i;
255 for (i = 0; i< 0xFFFFUL; i++);
256 }
257
_HAL_REG32_R(REG32 * reg)258 static MS_U32 _HAL_REG32_R(REG32 *reg)
259 {
260 MS_U32 value = 0UL;
261 value = (reg)->H << 16UL;
262 value |= (reg)->L;
263 return value;
264 }
265
_HAL_REG32L_R(REG32_L * reg)266 static MS_U16 _HAL_REG32L_R(REG32_L *reg)
267 {
268 MS_U16 value;
269 value = (reg)->data;
270 return value;
271 }
272
_HAL_REG16_R(REG16 * reg)273 static MS_U16 _HAL_REG16_R(REG16 *reg)
274 {
275 MS_U16 value = 0;
276 value = (reg)->u16data;
277 return value;
278 }
279
_HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)280 static MS_PHY _HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)
281 {
282 #ifdef HAL_MIU2_BASE
283 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
284 return (MS_PHY)HAL_MIU2_BASE;
285 else
286 #endif //HAL_MIU2_BUS_BASE
287 #ifdef HAL_MIU1_BASE
288 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
289 return (MS_PHY)HAL_MIU1_BASE;
290 else
291 #endif //HAL_MIU1_BUS_BASE
292 return (MS_PHY)HAL_MIU0_BASE;
293 }
294
295 #define REG16_T(addr) (*((volatile MS_U16*)(addr)))
296 #define ADDR_INDR_CTRL (_virtRegBase+ 0x2b20UL)
297 #define ADDR_INDR_ADDR0 (_virtRegBase+ 0x2b24UL)
298 #define ADDR_INDR_ADDR1 (_virtRegBase+ 0x2b28UL)
299 #define ADDR_INDR_WRITE0 (_virtRegBase+ 0x2b2cUL)
300 #define ADDR_INDR_WRITE1 (_virtRegBase+ 0x2b30UL)
301 #define ADDR_INDR_READ0 (_virtRegBase+ 0x2b34UL)
302 #define ADDR_INDR_READ1 (_virtRegBase+ 0x2b38UL)
303
304 #if 0
305 #define XBYTE_1591 (_virtRegBase+ 0x2a0cUL) // TsRec_Head21_Mid20
306 #define XBYTE_15A4 (_virtRegBase+ 0x2a10UL) // TsRec_Mid21_Tail20
307 #define XBYTE_15A6 (_virtRegBase+ 0x2b48UL) // TsRec_Mid
308
309 void HAL_TSP_HW_Lock_Init(void)
310 {
311 REG16_T(XBYTE_1591) = 0;
312 REG16_T(XBYTE_15A4) = 0;
313 REG16_T(XBYTE_15A6) = 0;
314 }
315
316 void _HAL_TSP_HW_Lock(void)
317 {
318 #ifdef MCU_HK
319 REG16_T(XBYTE_1591) = 0xFF;
320 REG16_T(XBYTE_15A4) = 0xFF;
321 while (REG16_T(XBYTE_15A4) && REG16_T(XBYTE_15A6));
322 REG16_T(XBYTE_1591) = 0xFF;
323 #else // MIPS HK
324 REG16_T(XBYTE_15A6) = 0xFF;
325 REG16_T(XBYTE_15A4) = 0x00;
326 while (REG16_T(XBYTE_1591) && (REG16_T(XBYTE_15A4)==0));
327 #endif
328 }
329
330 void _HAL_TSP_HW_Unlock(void)
331 {
332 #ifdef MCU_HK
333 REG16_T(XBYTE_1591) = 0x00;
334 #else
335 REG16_T(XBYTE_15A6) = 0x00;
336 #endif
337 }
338
339 #undef XBYTE_1591
340 #undef XBYTE_15A4
341 #undef XBYTE_15A6
342
343 #else
344
345 #define TSP_SEM_AEON (_virtRegBase+ 0xC1480UL) //TSP_HW_SEMAPHORE0, TS3 0x20
346 #define TSP_SEM_ORDER (_virtRegBase+ 0xC1484UL) // TSP_HW_SEMAPHORE1, TS3 0x21
347 #define TSP_SEM_MIPS (_virtRegBase+ 0xC1488UL) // TSP_HW_SEMAPHORE2, TS3 0x22
348
HAL_TSP_HW_Lock_Init(void)349 void HAL_TSP_HW_Lock_Init(void)
350 {
351 REG16_T(TSP_SEM_AEON) = 0;
352 REG16_T(TSP_SEM_MIPS) = 0;
353 REG16_T(TSP_SEM_ORDER) = 0;
354
355 _HAL_HALTSP_ENTRY();
356 }
357
_HAL_TSP_HW_TryLock(MS_BOOL bInit)358 static MS_BOOL _HAL_TSP_HW_TryLock(MS_BOOL bInit)
359 {
360 if (_bIsHK)
361 {
362 if (bInit)
363 {
364 REG16_T(TSP_SEM_AEON) = 0xFFFF;
365 REG16_T(TSP_SEM_ORDER) = 0xFFFF;
366 }
367 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS))
368 {
369 // REG16_T(TSP_SEM_AEON) = 0x0000;
370 return FALSE;
371 }
372 return TRUE;
373 }
374 else
375 {
376 if (bInit)
377 {
378 REG16_T(TSP_SEM_MIPS) = 0xFFFF;
379 REG16_T(TSP_SEM_ORDER) = 0x00;
380 }
381 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON)))
382 {
383 // REG16_T(TSP_SEM_MIPS) = 0x0000;
384 return FALSE;
385 }
386 return TRUE;
387 }
388 }
389
_HAL_TSP_HW_Lock(void)390 static void _HAL_TSP_HW_Lock(void)
391 {
392 if (FALSE == _HAL_TSP_HW_TryLock(TRUE))
393 {
394 while (FALSE == _HAL_TSP_HW_TryLock(FALSE));
395 }
396 }
397
_HAL_TSP_HW_Unlock(void)398 static void _HAL_TSP_HW_Unlock(void)
399 {
400 if (_bIsHK)
401 {
402 REG16_T(TSP_SEM_AEON) = 0x00;
403 }
404 else
405 {
406 REG16_T(TSP_SEM_MIPS) = 0x00;
407 }
408 }
409
HAL_TSP_HW_Lock_Release(void)410 void HAL_TSP_HW_Lock_Release(void)
411 {
412 REG16_T(TSP_SEM_AEON) = 0x00;
413 REG16_T(TSP_SEM_MIPS) = 0x00;
414
415 _HAL_HALTSP_EXIT();
416
417
418 }
419
HAL_TSP_TTX_IsAccess(MS_U32 u32Try)420 MS_BOOL HAL_TSP_TTX_IsAccess(MS_U32 u32Try)
421 {
422 if(u32Try == 0)
423 return FALSE;
424
425 if (_bIsHK)
426 {
427 if ( REG16_T(TSP_SEM_AEON))
428 {
429 return FALSE;
430 }
431 }
432 else
433 {
434 if (REG16_T(TSP_SEM_MIPS))
435 {
436 return FALSE;
437 }
438 }
439
440 if (_HAL_TSP_HW_TryLock(TRUE))
441 {
442 return TRUE;
443 }
444
445 _HAL_TSP_HW_Unlock();
446 return FALSE;
447 }
448
HAL_TSP_TTX_UnlockAccess(void)449 void HAL_TSP_TTX_UnlockAccess(void)
450 {
451 _HAL_TSP_HW_Unlock();
452 }
453
454 #undef TSP_SEM_AEON
455 #undef TSP_SEM_MIPS
456 #undef TSP_SEM_ORDER
457
458 #endif
459
HAL_REG32_IndR(REG32 * reg)460 MS_U32 HAL_REG32_IndR(REG32 *reg)
461 {
462 MS_VIRT virtReg = (MS_VIRT)reg;
463 MS_U32 u32Ret;
464
465 _HAL_TSP_HW_Lock();
466
467 _HAL_HALTSP_LOCK();
468
469 // set address
470 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
471 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
472
473 // set command
474 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
475 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
476 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
477
478 // get read value
479 u32Ret = ((MS_U32)(REG16_T(ADDR_INDR_READ0))| ((MS_U32)(REG16_T(ADDR_INDR_READ1)<< 16UL)));
480
481 _HAL_HALTSP_UNLOCK();
482 _HAL_TSP_HW_Unlock();
483 return u32Ret;
484 }
485
HAL_REG32_IndR_tmp(REG32 * reg)486 static MS_U32 HAL_REG32_IndR_tmp(REG32 *reg)
487 {
488 MS_VIRT virtReg = (MS_VIRT)reg;
489 MS_U32 u32Ret;
490
491 _HAL_HALTSP_LOCK();
492
493 // set address
494 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
495 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
496
497 // set command
498 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
499 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
500 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
501
502 // get read value
503 u32Ret = ((MS_U32)(REG16_T(ADDR_INDR_READ0))| ((MS_U32)(REG16_T(ADDR_INDR_READ1)<< 16)));
504
505 _HAL_HALTSP_UNLOCK();
506
507 return u32Ret;
508 }
HAL_REG32_IndW_tmp(REG32 * reg,MS_U32 value)509 static void HAL_REG32_IndW_tmp(REG32 *reg, MS_U32 value)
510 {
511 MS_VIRT virtReg = (MS_VIRT)reg;
512 _HAL_HALTSP_LOCK();
513
514 // set address
515 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
516 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
517
518 // set write value
519 REG16_T(ADDR_INDR_WRITE0)= (MS_U16)value;
520 REG16_T(ADDR_INDR_WRITE1)= (MS_U16)(value >> 16UL);
521
522 // set command
523 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
524 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
525 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
526
527 _HAL_HALTSP_UNLOCK();
528 }
529
HAL_REG32_IndW(REG32 * reg,MS_U32 value)530 void HAL_REG32_IndW(REG32 *reg, MS_U32 value)
531 {
532 MS_VIRT virtReg = (MS_VIRT)reg;
533 _HAL_TSP_HW_Lock();
534
535 _HAL_HALTSP_LOCK();
536
537 // set address
538 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
539 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
540
541 // set write value
542 REG16_T(ADDR_INDR_WRITE0)= (MS_U16)value;
543 REG16_T(ADDR_INDR_WRITE1)= (MS_U16)(value >> 16UL);
544
545 // set command
546 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
547 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
548 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
549
550 _HAL_HALTSP_UNLOCK();
551
552 _HAL_TSP_HW_Unlock();
553 }
554
555 static MS_U16 u16LastAddr0, u16LastAddr1, u16LastWrite0, u16LastWrite1, u16LastRead0, u16LastRead1;
556
557 static MS_U32 _u32PidFltBuf[(TSP_PIDFLT_NUM_ALL*sizeof(REG_PidFlt))>> 3];
558 static MS_U32 _u32SecFltBuf[TSP_SECFLT_NUM*((sizeof(REG_SecFlt)-sizeof((((REG_SecFlt*)0)->_x50)))>> 3)];
559 //[LEGACY] //[OBSOLETE]
560 MS_BOOL _bIsHK = TRUE;
561 //[LEGACY] //[OBSOLETE]
HAL_TSP_SaveFltState(void)562 void HAL_TSP_SaveFltState(void)
563 {
564 MS_U32 u32EngId;
565 MS_U32 i, j;
566 MS_U32 u32SecEnd = ((size_t)&(((REG_SecFlt*)0)->_x50))/sizeof(REG32);
567
568 for (u32EngId = 0; u32EngId < TSP_ENGINE_NUM; u32EngId++)
569 {
570 for (i = 0; i < TSP_PIDFLT_NUM_ALL; i++)
571 {
572 REG_PidFlt *pPidFilter = &(_TspPid[u32EngId].Flt[i]);
573 _u32PidFltBuf[i] = HAL_REG32_IndR(pPidFilter);
574 }
575 j = 0;
576 for (i = 0; i < TSP_SECFLT_NUM; i++)
577 {
578 REG32* pRegStart = (REG32*) &(_TspSec[u32EngId].Flt[i]);
579 // REG32* pRegEnd = (REG32*)&(_TspSec[u32EngId].Flt[i + 1]);
580 REG32* pRegEnd = pRegStart + u32SecEnd;
581 REG32* pReg = pRegStart;
582 while (pReg < pRegEnd)
583 {
584 _u32SecFltBuf[j] = HAL_REG32_IndR(pReg);
585 j++;
586 pReg++;
587 }
588 }
589 }
590 }
HAL_TSP_RestoreFltState(void)591 void HAL_TSP_RestoreFltState(void)
592 {
593 MS_U32 u32EngId;
594 MS_U32 i, j;
595 MS_U32 u32SecEnd = ((size_t)&(((REG_SecFlt*)0)->_x50))/sizeof(REG32);
596
597 for (u32EngId = 0; u32EngId < TSP_ENGINE_NUM; u32EngId++)
598 {
599 for (i = 0; i < TSP_PIDFLT_NUM_ALL; i++)
600 {
601 REG_PidFlt *pPidFilter = &(_TspPid[u32EngId].Flt[i]);
602 HAL_REG32_IndW(pPidFilter, _u32PidFltBuf[i]);
603 }
604 j = 0;
605 for (i = 0; i < TSP_SECFLT_NUM; i++)
606 {
607 REG32* pRegStart = (REG32*) &(_TspSec[u32EngId].Flt[i]);
608 REG32* pRegEnd = pRegStart + u32SecEnd;
609 REG32* pReg = pRegStart;
610 while (pReg < pRegEnd)
611 {
612 HAL_REG32_IndW(pReg, _u32SecFltBuf[j]);
613 j++;
614 pReg++;
615 }
616 }
617 }
618 }
619
620
HAL_TSP_ISR_SAVE_ALL(void)621 void HAL_TSP_ISR_SAVE_ALL(void)
622 {
623 // save address
624 u16LastAddr0= (MS_U16)REG16_T(ADDR_INDR_ADDR0);
625 u16LastAddr1= (MS_U16)REG16_T(ADDR_INDR_ADDR1);
626
627 // save write
628 u16LastWrite0= (MS_U16)REG16_T(ADDR_INDR_WRITE0);
629 u16LastWrite1= (MS_U16)REG16_T(ADDR_INDR_WRITE1);
630
631 // save read
632 u16LastRead0= (MS_U16)REG16_T(ADDR_INDR_READ0);
633 u16LastRead1= (MS_U16)REG16_T(ADDR_INDR_READ1);
634 }
635
HAL_TSP_ISR_RESTORE_ALL(void)636 void HAL_TSP_ISR_RESTORE_ALL(void)
637 {
638 // restore read
639 REG16_T(ADDR_INDR_READ0)= u16LastRead0;
640 REG16_T(ADDR_INDR_READ1)= u16LastRead1;
641
642 // restore write
643 REG16_T(ADDR_INDR_WRITE0)= u16LastWrite0;
644 REG16_T(ADDR_INDR_WRITE1)= u16LastWrite1;
645
646 // restore addr
647 REG16_T(ADDR_INDR_ADDR0)= u16LastAddr0;
648 REG16_T(ADDR_INDR_ADDR1)= u16LastAddr1;
649 }
650 #undef ADDR_INDR_CTRL
651 #undef ADDR_INDR_ADDR0
652 #undef ADDR_INDR_ADDR1
653 #undef ADDR_INDR_WRITE0
654 #undef ADDR_INDR_WRITE1
655 #undef ADDR_INDR_READ0
656 #undef ADDR_INDR_READ1
657
658 //--------------------------------------------------------------------------------------------------
659 // For MISC part
660 //--------------------------------------------------------------------------------------------------
HAL_TSP_Scmb_Detect(MS_BOOL bEnable)661 void HAL_TSP_Scmb_Detect(MS_BOOL bEnable)
662 {
663 if (bEnable)
664 {
665 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
666 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld));
667 }
668 else
669 {
670 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
671 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld));
672 }
673 }
674
HAL_TSP_CSA_Set_ScrmPath(MS_U32 u32ScrmPath)675 void HAL_TSP_CSA_Set_ScrmPath(MS_U32 u32ScrmPath)
676 {
677 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL, u32ScrmPath);
678 }
679
HAL_TSP_Set_AVPAUSE(MS_BOOL bSet)680 void HAL_TSP_Set_AVPAUSE(MS_BOOL bSet)
681 {
682 if (bSet)
683 {
684 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL,
685 SET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE));
686 }
687 else
688 {
689 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL,
690 RESET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE));
691 }
692 }
693
HAL_TSP_CSA_Get_ScrmPath(void)694 MS_U32 HAL_TSP_CSA_Get_ScrmPath(void)
695 {
696 return (MS_U32)(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL) & TSP_CA_CTRL_MASK);
697 }
698
699 //--------------------------------------------------------------------------------------------------
700 // For PID filter part
701 //--------------------------------------------------------------------------------------------------
HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt * pPidFilter)702 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFilter)
703 {
704 return (HAL_REG32_IndR((REG32 *)pPidFilter) & TSP_PIDFLT_OUT_MASK);
705 }
706
HAL_TSP_PidFlt_GetPid(REG_PidFlt * pPidFilter)707 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFilter)
708 {
709 return (HAS_FLAG(HAL_REG32_IndR((REG32 *)pPidFilter), TSP_PIDFLT_PID_MASK)>> TSP_PIDFLT_PID_SHFT);
710 }
711
HAL_TSP_PidFlt_SetPid(REG_PidFlt * pPidFilter,MS_U32 u32PID)712 void HAL_TSP_PidFlt_SetPid(REG_PidFlt *pPidFilter, MS_U32 u32PID)
713 {
714 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_PID_MASK) | ((u32PID << TSP_PIDFLT_PID_SHFT) & TSP_PIDFLT_PID_MASK));
715 }
716
HAL_TSP_PidFlt_SelFltOutput(REG_PidFlt * pPidFilter,MS_U32 u32FltOutput)717 void HAL_TSP_PidFlt_SelFltOutput(REG_PidFlt *pPidFilter, MS_U32 u32FltOutput)
718 {
719 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_OUT_MASK) | (u32FltOutput & TSP_PIDFLT_OUT_MASK));
720 }
721
HAL_TSP_PidFlt_SelSecFlt(REG_PidFlt * pPidFilter,MS_U32 u32SecFltId)722 void HAL_TSP_PidFlt_SelSecFlt(REG_PidFlt *pPidFilter, MS_U32 u32SecFltId)
723 {
724 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_SECFLT_MASK) | ((u32SecFltId << TSP_PIDFLT_SECFLT_SHFT) & TSP_PIDFLT_SECFLT_MASK));
725 }
726
HAL_TSP_PidFlt_PVREnable(REG_PidFlt * pPidFilter)727 void HAL_TSP_PidFlt_PVREnable(REG_PidFlt *pPidFilter)
728 {
729 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) | TSP_PIDFLT_PVR_ENABLE));
730 }
731
732
HAL_TSP_SecFlt_SetType(REG_SecFlt * pSecFilter,MS_U32 u32FltType)733 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFilter, MS_U32 u32FltType)
734 {
735 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, (HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~TSP_SECFLT_TYPE_MASK) | (u32FltType << TSP_SECFLT_TYPE_SHFT));
736 }
737
HAL_TSP_PidFlt_GetSecFlt(REG_PidFlt * pPidFilter)738 MS_U32 HAL_TSP_PidFlt_GetSecFlt(REG_PidFlt *pPidFilter)
739 {
740 return ((HAL_REG32_IndR((REG32 *)pPidFilter) & TSP_PIDFLT_SECFLT_MASK) >> TSP_PIDFLT_SECFLT_SHFT);
741 }
742
HAL_TSP_PidFlt_SelFltSource(REG_PidFlt * pPidFilter,MS_U32 u32FltSource)743 void HAL_TSP_PidFlt_SelFltSource(REG_PidFlt *pPidFilter, MS_U32 u32FltSource)
744 {
745 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_IN_MASK) | (u32FltSource & TSP_PIDFLT_IN_MASK));
746 }
747
748 //--------------------------------------------------------------------------------------------------
749 // For section filter part
750 //--------------------------------------------------------------------------------------------------
HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt * pSecFilter)751 MS_U32 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFilter)
752 {
753 return (pSecFilter - (REG_SecFlt*)REG_SECFLT_BASE)>> 8; // div 0x100
754 }
755
HAL_TSP_SecFlt_ResetState(REG_SecFlt * pSecFilter)756 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFilter)
757 {
758 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~(TSP_SECFLT_STATE_MASK));
759 }
760
HAL_TSP_SecFlt_SetRmnCount(REG_SecFlt * pSecFilter,MS_U32 u32RmnCount)761 void HAL_TSP_SecFlt_SetRmnCount(REG_SecFlt *pSecFilter, MS_U32 u32RmnCount)
762 {
763 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_RMNCNT_MASK) |
764 ((u32RmnCount << TSP_SECFLT_RMNCNT_SHFT) & TSP_SECFLT_RMNCNT_MASK));
765 }
766
HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt * pSecFilter)767 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFilter)
768 {
769 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, 0);
770 }
771
772
HAL_TSP_SW_INT_STATUS(void)773 MS_U32 HAL_TSP_SW_INT_STATUS(void)
774 {
775 if (_bIsHK)
776 {
777 return _HAL_REG32_R(&_TspCtrl[0].SwInt_Stat);
778 }
779 else
780 {
781 MS_U32 u32SwIntStatus = (MS_U32)_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_M);
782 u32SwIntStatus |= ((_HAL_REG32_R(&_TspCtrl[0].SwInt_Stat1_H) & TSP_SWINT1_H_MASK) >> TSP_SWINT1_H_SHFT)<< 16;
783 return u32SwIntStatus;
784 }
785 }
786
787 // match mask --> 0 will compare
HAL_TSP_SecFlt_SetMask(REG_SecFlt * pSecFilter,MS_U8 * pu8Mask)788 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFilter, MS_U8 *pu8Mask)
789 {
790 MS_U32 i;
791 MS_U32 u32Temp;
792 MS_U32 j;
793
794 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
795 {
796 j = (i<< 2);
797 u32Temp = (pu8Mask[j]) | (pu8Mask[j+ 1] << 8 ) | (pu8Mask[j+ 2] << 16 )| (pu8Mask[j+ 3] << 24);
798 HAL_REG32_IndW((REG32 *)&pSecFilter->Mask[i], u32Temp);
799 }
800 }
801
802 // not match mask --> 1 will compare
HAL_TSP_SecFlt_SetNMask(REG_SecFlt * pSecFilter,MS_U8 * pu8NMask)803 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFilter, MS_U8 *pu8NMask)
804 {
805 MS_U32 u32FltId;
806 MS_U32 u32Temp;
807 REG_SecFlt* ptempSecFlt = &(_TspSec[0].Flt[31]);
808
809 u32Temp = (pu8NMask[0x0]) | (pu8NMask[0x1] << 8 ) | (pu8NMask[0x2] << 16 )| (pu8NMask[0x3] << 24);
810 HAL_REG32_IndW(&(ptempSecFlt->Match[0]), u32Temp);
811
812 u32Temp = (pu8NMask[0x4]) | (pu8NMask[0x5] << 8 ) | (pu8NMask[0x6] << 16 )| (pu8NMask[0x7] << 24);
813 HAL_REG32_IndW(&(ptempSecFlt->Match[1]), u32Temp);
814
815 u32Temp = (pu8NMask[0x8]) | (pu8NMask[0x9] << 8 ) | (pu8NMask[0xa] << 16 )| (pu8NMask[0xb] << 24);
816 HAL_REG32_IndW(&(ptempSecFlt->Match[2]), u32Temp);
817
818 u32Temp = (pu8NMask[0xc]) | (pu8NMask[0xd] << 8 ) | (pu8NMask[0xe] << 16 )| (pu8NMask[0xf] << 24);
819 HAL_REG32_IndW(&(ptempSecFlt->Match[3]), u32Temp);
820
821 u32FltId = (MS_U32)(pSecFilter - (REG_SecFlt*)REG_SECFLT_BASE);
822
823 //printf("[%s][%d] u32FltId %d\n", __FUNCTION__, __LINE__, (unsigned int)u32FltId);
824
825 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_NMATCH | u32FltId);
826
827 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
828 }
829
HAL_TSP_SecFlt_SetMatch(REG_SecFlt * pSecFilter,MS_U8 * pu8Match)830 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFilter, MS_U8 *pu8Match)
831 {
832 MS_U32 i;
833 MS_U32 u32Temp;
834 MS_U32 j;
835
836 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
837 {
838 j = (i<< 2);
839 u32Temp = (pu8Match[j]) | (pu8Match[j+ 1] << 8 ) | (pu8Match[j+ 2] << 16 )| (pu8Match[j+ 3] << 24);
840 HAL_REG32_IndW((REG32 *)&pSecFilter->Match[i], u32Temp);
841 }
842 }
843
HAL_TSP_SecFlt_SetReqCount(REG_SecFlt * pSecFilter,MS_U32 u32ReqCount)844 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFilter, MS_U32 u32ReqCount)
845 {
846 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_REQCNT_MASK) |
847 ((u32ReqCount << TSP_SECFLT_REQCNT_SHFT) & TSP_SECFLT_REQCNT_MASK));
848 }
849
HAL_TSP_SecFlt_SetMode(REG_SecFlt * pSecFilter,MS_U32 u32SecFltMode)850 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFilter, MS_U32 u32SecFltMode)
851 {
852 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, (HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~TSP_SECFLT_MODE_MASK) | ((u32SecFltMode << TSP_SECFLT_MODE_SHFT) & TSP_SECFLT_MODE_MASK));
853 }
854
HAL_TSP_SecFlt_GetCRC32(REG_SecFlt * pSecFilter)855 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFilter)
856 {
857 return HAL_REG32_IndR((REG32 *)&pSecFilter->CRC32);
858 }
859
HAL_TSP_SecFlt_GetState(REG_SecFlt * pSecFilter)860 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFilter)
861 {
862 return ((HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & TSP_SECFLT_STATE_MASK) >> TSP_SECFLT_STATE_SHFT);
863 }
864
HAL_TSP_SecFlt_GetMode(REG_SecFlt * pSecFilter)865 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFilter)
866 {
867 return ((HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & TSP_SECFLT_MODE_MASK) >> TSP_SECFLT_MODE_SHFT);
868 }
869
HAL_TSP_SecFlt_PcrReset(REG_SecFlt * pSecFilter)870 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFilter)
871 {
872 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) | TSP_SECFLT_PCRRST);
873 }
874
HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId)875 void HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId)
876 {
877 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_VER_RESET | u32SecFltId);
878 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
879 }
880
HAL_TSP_SecFlt_SetDataAddr(MS_PHY phyDataAddr)881 void HAL_TSP_SecFlt_SetDataAddr(MS_PHY phyDataAddr)
882 {
883 MS_PHY phyAddr = phyDataAddr - _HAL_TSP_MIU_OFFSET(phyDataAddr);
884 MS_U32 u32cmd = TSP_MCU_CMD_MEM_HIGH_ADDR | ((MS_U32)(phyAddr & 0xFFFF0000UL) >> 16UL);
885
886 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32cmd);
887 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
888
889 u32cmd = TSP_MCU_CMD_MEM_LOW_ADDR | ((MS_U32)(phyAddr & 0xFFFFUL));
890 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32cmd);
891 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
892 }
893
894
895 //--------------------------------------------------------------------------------------------------
896 // For section buffer part
897 //--------------------------------------------------------------------------------------------------
898 // To avoid SW read hidden HW byte enable information.
899 #define _TSP_SEC_BUF_ADDR_START(pSecFilter) (TSP_SECFLT_BUFSTART_MASK & HAL_REG32_IndR((REG32 *)&((pSecFilter)->BufStart)))
900
HAL_TSP_SecBuf_SetBuffer(REG_SecFlt * pSecBuf,MS_PHY phyStartAddr,MS_U32 u32BufSize)901 void HAL_TSP_SecBuf_SetBuffer(REG_SecFlt *pSecBuf, MS_PHY phyStartAddr, MS_U32 u32BufSize)
902 {
903 MS_PHY phyAddr = 0UL;
904
905 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyStartAddr);
906 phyAddr = phyStartAddr - _phySecBufMiuOffset;
907
908 HAL_REG32_IndW((REG32 *)&pSecBuf->BufStart, (MS_U32)phyAddr);
909 HAL_REG32_IndW((REG32 *)&pSecBuf->BufEnd, ((MS_U32)phyAddr + u32BufSize));
910 }
911
HAL_TSP_SecBuf_SetBufRead(REG_SecFlt * pSecBuf,MS_PHY phyReadAddr)912 void HAL_TSP_SecBuf_SetBufRead(REG_SecFlt *pSecBuf, MS_PHY phyReadAddr)
913 {
914 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyReadAddr);
915
916 HAL_REG32_IndW((REG32 *)&pSecBuf->BufRead, (MS_U32)(phyReadAddr-_phySecBufMiuOffset));
917 }
918
HAL_TSP_SecBuf_GetBufStart(REG_SecFlt * pSecBuf)919 MS_PHY HAL_TSP_SecBuf_GetBufStart(REG_SecFlt *pSecBuf)
920 {
921 return (((MS_PHY)_TSP_SEC_BUF_ADDR_START(pSecBuf) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
922 }
923
HAL_TSP_SecBuf_GetBufEnd(REG_SecFlt * pSecBuf)924 MS_PHY HAL_TSP_SecBuf_GetBufEnd(REG_SecFlt *pSecBuf)
925 {
926 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufEnd) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
927 }
928
HAL_TSP_SecBuf_GetBufCur(REG_SecFlt * pSecBuf)929 MS_PHY HAL_TSP_SecBuf_GetBufCur(REG_SecFlt *pSecBuf)
930 {
931 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufCur) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
932 }
933
HAL_TSP_SecBuf_ResetBuffer(REG_SecFlt * pSecBuf)934 void HAL_TSP_SecBuf_ResetBuffer(REG_SecFlt *pSecBuf)
935 {
936 HAL_REG32_IndW((REG32 *)&pSecBuf->BufCur, _TSP_SEC_BUF_ADDR_START(pSecBuf));
937 HAL_REG32_IndW((REG32 *)&pSecBuf->BufRead, _TSP_SEC_BUF_ADDR_START(pSecBuf));
938 HAL_REG32_IndW((REG32 *)&pSecBuf->BufWrite, _TSP_SEC_BUF_ADDR_START(pSecBuf));
939 }
940
HAL_TSP_SecBuf_GetBufRead(REG_SecFlt * pSecBuf)941 MS_PHY HAL_TSP_SecBuf_GetBufRead(REG_SecFlt *pSecBuf)
942 {
943 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufRead) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
944 }
945
HAL_TSP_SecBuf_GetBufWrite(REG_SecFlt * pSecBuf)946 MS_PHY HAL_TSP_SecBuf_GetBufWrite(REG_SecFlt *pSecBuf)
947 {
948 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufWrite) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
949 }
950
951 #undef _TSP_SEC_BUF_ADDR_START
952
HAL_TSP_SecBuf_SetBufRead_tmp(REG_SecFlt * pSecBuf,MS_PHY phyReadAddr)953 void HAL_TSP_SecBuf_SetBufRead_tmp(REG_SecFlt *pSecBuf, MS_PHY phyReadAddr)
954 {
955 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyReadAddr);
956 HAL_REG32_IndW_tmp((REG32 *)&pSecBuf->BufRead, (MS_U32)(phyReadAddr-_phySecBufMiuOffset));
957 }
958
HAL_TSP_SecBuf_GetBufWrite_tmp(REG_SecFlt * pSecBuf)959 MS_PHY HAL_TSP_SecBuf_GetBufWrite_tmp(REG_SecFlt *pSecBuf)
960 {
961 return (((MS_PHY)HAL_REG32_IndR_tmp((REG32 *)&pSecBuf->BufWrite) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
962 }
963
964 //--------------------------------------------------------------------------------------------------
965 // For DMA part
966 //--------------------------------------------------------------------------------------------------
967 //[HW LIMIT][HW TODO] TsDma pause can not be access by TSP CPU
968 //[HW LIMIT][HW TODO] TsDma pause it hard to control because read/write in different register
969 //[HW LIMIT][HW TODO] When setting TsDma it should be disable interrupt
HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay)970 void HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay)
971 {
972 // Richard: the file in timer in Uranus is 24 bits.
973 // to simplify the process, writing 32 bits directly.
974 // HW will truncate the high 8 bits out, and use low 24 bits only (from Albert Lin)
975 _HAL_REG32_W(&_TspCtrl[0].TsFileIn_Timer, u32Delay);
976 }
977
HAL_TSP_CmdQ_TsDma_SetAddr(MS_PHY phyStreamAddr)978 void HAL_TSP_CmdQ_TsDma_SetAddr(MS_PHY phyStreamAddr)
979 {
980 _phyFIBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyStreamAddr);
981 _HAL_REG32_W(&_TspCtrl[0].TsDma_Addr, (MS_U32)(phyStreamAddr-_phyFIBufMiuOffset));
982 }
983
HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize)984 MS_BOOL HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize)
985 {
986 if (u32StreamSize < 16) // t2 HW limite, CMQ had some problem while bufsize < 16
987 {
988 return FALSE;
989 }
990 _HAL_REG32_W(&_TspCtrl[0].TsDma_Size, u32StreamSize);
991 return TRUE;
992 }
993
HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl)994 void HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl)
995 {
996 // enable filein byte timer
997 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
998 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_BYTE_TIMER_EN));
999
1000 _HAL_REG32_W(&_TspCtrl[0].TsDma_Ctrl_CmdQ, TSP_TSDMA_CTRL_START | (u32TsDmaCtrl & TSP_TSDMA_CTRL_PESMODE_MASK));
1001 }
1002
HAL_TSP_TsDma_Pause(void)1003 void HAL_TSP_TsDma_Pause(void)
1004 {
1005 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1006 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE));
1007 }
1008
HAL_TSP_TsDma_Resume(void)1009 void HAL_TSP_TsDma_Resume(void)
1010 {
1011 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1012 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE));
1013 }
1014
HAL_TSP_CmdQ_TsDma_GetState(void)1015 MS_U32 HAL_TSP_CmdQ_TsDma_GetState(void)
1016 {
1017 return (HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ), TSP_TSDMA_CTRL_START) |
1018 (MS_U32)(HAS_FLAG(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)));
1019 }
1020
HAL_TSP_CmdQ_EmptyCount(void)1021 MS_U32 HAL_TSP_CmdQ_EmptyCount(void)
1022 {
1023 return (TSP_CMDQ_SIZE - ((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_CNT_MASK)>>TSP_CMDQ_CNT_SHFT));
1024 }
1025
HAL_TSP_Get_CmdQFifoLevel(void)1026 MS_U8 HAL_TSP_Get_CmdQFifoLevel(void)
1027 {
1028 return (MS_U8)((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT);
1029 }
1030
HAL_TSP_SetCtrlMode(MS_U32 u32EngId,MS_U32 u32Mode,MS_U32 u32TsIfId)1031 void HAL_TSP_SetCtrlMode(MS_U32 u32EngId, MS_U32 u32Mode, MS_U32 u32TsIfId)
1032 {
1033 // Control bits:
1034 // TSP_CTRL_CPU_EN
1035 // TSP_CTRL_SW_RST
1036 // TSP_CTRL_MEM_DMA_EN
1037
1038 // for file in related setting
1039 if(u32Mode == 0)
1040 {
1041 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1042 (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl) & ~(TSP_CTRL_CPU_EN |
1043 TSP_CTRL_SW_RST |
1044 TSP_CTRL_TSFILE_EN)));
1045 HAL_TSP_filein_enable(FALSE);
1046 }
1047 else
1048 {
1049 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1050 (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl) & ~(TSP_CTRL_CPU_EN |
1051 TSP_CTRL_SW_RST |
1052 //TSP_CTRL_TSFILE_EN |
1053 //[URANUS] TSP_CTRL_CLK_GATING_DISABLE |
1054 // @FIXME: Richard ignore this at this stage
1055 0 )) | u32Mode);
1056
1057 if(HAS_FLAG(u32Mode, TSP_CTRL_TSFILE_EN))
1058 HAL_TSP_filein_enable(TRUE);
1059 }
1060
1061 if (TSP_IF_NUM > u32TsIfId)
1062 {
1063 _HAL_TSP_tsif_select(HAS_FLAG(u32Mode, (MS_U8)(u32TsIfId & 0xFF)));
1064 }
1065 }
1066
1067 //--------------------------------------------------------------------------------------------------
1068 // For PVR part
1069 //--------------------------------------------------------------------------------------------------
HAL_TSP_PVR_SetBuffer(MS_PHY phyBufStart0,MS_PHY phyBufStart1,MS_U32 u32BufSize0,MS_U32 u32BufSize1)1070 void HAL_TSP_PVR_SetBuffer(MS_PHY phyBufStart0, MS_PHY phyBufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1)
1071 {
1072 MS_PHY phyBufEnd;
1073
1074 _phyPVRBufMiuOffset[0] = _HAL_TSP_MIU_OFFSET(phyBufStart0);
1075
1076 // for buffer 0
1077 phyBufEnd= phyBufStart0+ u32BufSize0;
1078 _HAL_REG32_W(&_TspCtrl[0].TsRec_Head, ((MS_U32)(phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)); // 8 bytes unit
1079 _HAL_REG32_W(&_TspCtrl[0].TsRec_Tail, ((MS_U32)(phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)); // 8 bytes unit
1080
1081 // for buffer 1
1082 phyBufEnd= phyBufStart1+ u32BufSize1;
1083 #define ADDR_PVR_HEAD20 (_virtRegBase+ 0x2a04)
1084 #define ADDR_PVR_HEAD21 (_virtRegBase+ 0x2a08)
1085 #define ADDR_PVR_MID20 (_virtRegBase+ 0x2a0c)
1086 #define ADDR_PVR_MID21 (_virtRegBase+ 0x2a10)
1087 #define ADDR_PVR_TAIL20 (_virtRegBase+ 0x2a14)
1088 #define ADDR_PVR_TAIL21 (_virtRegBase+ 0x2a18)
1089 REG16_T(ADDR_PVR_HEAD20)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF;
1090 REG16_T(ADDR_PVR_HEAD21)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF;
1091 REG16_T(ADDR_PVR_TAIL20)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF;
1092 REG16_T(ADDR_PVR_TAIL21)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF;
1093 #undef ADDR_PVR_HEAD20
1094 #undef ADDR_PVR_HEAD21
1095 #undef ADDR_PVR_MID20
1096 #undef ADDR_PVR_MID21
1097 #undef ADDR_PVR_TAIL20
1098 #undef ADDR_PVR_TAIL21
1099
1100 // enable PVR ping pong buffer
1101 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1102 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_STR2MI_MIU_PINPON_EN));
1103
1104 // flush PVR buffer
1105 HAL_TSP_PVR_WaitFlush();
1106 }
1107
HAL_TSP_PVR_Enable(MS_BOOL bEnable)1108 void HAL_TSP_PVR_Enable(MS_BOOL bEnable)
1109 {
1110 //set burst len = 1
1111 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1112 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_burst_len_MASK));
1113
1114 // disable timeshift write protect -- it must enable while record/playback use the same buffer
1115 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1116 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP));
1117
1118 if (bEnable)
1119 {
1120 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1121 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE));
1122 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1123 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1124 }
1125 else
1126 {
1127 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1128 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE));
1129 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1130 // RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1131 }
1132 }
1133
HAL_TSP_PVR_Reset(void)1134 void HAL_TSP_PVR_Reset(void)
1135 {
1136 // Richard: @FIXME:
1137 // Don't know PVR "reset" definition. call flush instead.
1138 HAL_TSP_PVR_WaitFlush();
1139 }
1140
HAL_TSP_PVR_All(MS_BOOL bPvrAll)1141 void HAL_TSP_PVR_All(MS_BOOL bPvrAll)
1142 {
1143 if (bPvrAll)
1144 {
1145 // bypass mode
1146 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1147 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1148 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1149 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN));
1150 }
1151 else
1152 {
1153 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1154 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1155 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1156 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN));
1157 }
1158 }
1159
HAL_TSP_PVR_Filein_Enable(MS_BOOL bBypassHD,MS_BOOL bEnable,MS_BOOL bRecAll)1160 void HAL_TSP_PVR_Filein_Enable(MS_BOOL bBypassHD, MS_BOOL bEnable, MS_BOOL bRecAll)
1161 {
1162 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].reg15b4);
1163
1164 if(bBypassHD)
1165 u32data |= TSP_PVR_TS_HEADER;
1166 else
1167 u32data &= ~TSP_PVR_TS_HEADER;
1168
1169 if(bRecAll)
1170 {
1171 u32data |= TSP_REC_ALL_FILE;
1172 }
1173 else
1174 {
1175 u32data &= ~TSP_REC_ALL_FILE;
1176 }
1177
1178 if(bEnable)
1179 u32data |= TSP_PVR_FILEIN;
1180 else
1181 u32data &= ~TSP_PVR_FILEIN;
1182
1183 _HAL_REG32_W(&_TspCtrl[0].reg15b4, u32data);
1184 }
1185
HAL_TSP_PVR_Eng_IsEnabled(MS_U32 u32EngId)1186 MS_BOOL HAL_TSP_PVR_Eng_IsEnabled(MS_U32 u32EngId)
1187 {
1188 if(u32EngId == 0)
1189 {
1190 return ((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PVR_ENABLE) > 0);
1191 }
1192 else
1193 {
1194 return FALSE;
1195 }
1196 }
1197
HAL_TSP_LiveAB_En(MS_BOOL bPF_EN)1198 void HAL_TSP_LiveAB_En(MS_BOOL bPF_EN)
1199 {
1200 if (bPF_EN)
1201 {
1202 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_LIVEAB_SEL);
1203 }
1204 else
1205 {
1206 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_LIVEAB_SEL);
1207 }
1208 }
1209
HAL_TSP_IsLiveAB_Enable(void)1210 MS_BOOL HAL_TSP_IsLiveAB_Enable(void)
1211 {
1212 return ((_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & TSP_LIVEAB_SEL) != 0);
1213 }
1214
HAL_TSP_SetPKTSize(MS_U32 u32PKTSize)1215 void HAL_TSP_SetPKTSize(MS_U32 u32PKTSize)
1216 {
1217 if((u32PKTSize == 0x82) || (u32PKTSize == 0x86)) // RVU
1218 {
1219 printf("HAL_TSP_SetPKTSize: This chip not support RVU!\n"); // not support
1220 }
1221 else
1222 {
1223 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_ALT_TS_SIZE));
1224 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, (_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein)&~TSP_PKT_SIZE_MASK)|(TSP_PKT_SIZE_MASK&u32PKTSize));
1225 }
1226 }
1227
1228 // Set 1 to disable file-in timestamp block scheme, bypass timestamp
HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable)1229 void HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable)
1230 {
1231 if (!bEnable)
1232 {
1233 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_PKT192_BLK_DIS_FIN);
1234 }
1235 else
1236 {
1237 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_PKT192_BLK_DIS_FIN);
1238 }
1239 }
1240
1241
HAL_TSP_PVR_GetBufWrite(void)1242 MS_PHY HAL_TSP_PVR_GetBufWrite(void)
1243 {
1244 MS_PHY phyvalue;
1245
1246 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
1247 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD));
1248 phyvalue = (MS_PHY)(_HAL_REG32_R(&_TspCtrl[0].TsRec_WPtr)<< MIU_BUS) + _phyPVRBufMiuOffset[0];
1249 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
1250 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD));
1251
1252 return phyvalue;
1253
1254 }
1255
HAL_TSP_PVR_WaitFlush(void)1256 void HAL_TSP_PVR_WaitFlush(void)
1257 {
1258 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1259 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH));
1260 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1261 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH));
1262 }
1263
HAL_TSP_PVR_REC_FLT_Enable(MS_BOOL bEnable)1264 void HAL_TSP_PVR_REC_FLT_Enable(MS_BOOL bEnable)
1265 {
1266 if(bEnable)
1267 {
1268 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1269 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1270 }
1271 else
1272 {
1273 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1274 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1275 }
1276 }
1277
1278
1279 //--------------------------------------------------------------------------------------------------
1280 // For FW part
1281 //--------------------------------------------------------------------------------------------------
1282 /*
1283 void HAL_TSP_SetFwMsg(MS_U32 u32Mode)
1284 {
1285 _HAL_REG32_W(&_TspCtrl[0].Mcu_Msg, u32Mode);
1286 }
1287
1288 MS_U32 HAL_TSP_GetFwMsg(void)
1289 {
1290 return (_HAL_REG32_R(&_TspCtrl[0].Mcu_Msg));
1291 }
1292 */
1293
1294 static MS_U32 _u32FlowPadMap[2] = { 0x0, 0x0};
1295
1296 //--------------------------------------------------------------------------------------------------
1297 // For pad select part
1298 //--------------------------------------------------------------------------------------------------
HAL_TSP_SelPad(MS_U32 u32EngId,MS_U32 u32Flow,MS_U32 u32Pad)1299 void HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 u32Flow, MS_U32 u32Pad)
1300 {
1301
1302 MS_U32 u32Shft = 0;
1303
1304 MS_ASSERT(TSP_TS_PAD_NUM >= u32Pad);
1305
1306 if(u32Flow >= TSP_IF_NUM)
1307 {
1308 return;
1309 }
1310
1311 if (0 == u32Pad)
1312 {
1313 // internal demod
1314 u32Pad = TSP_MUX_INDEMOD;
1315 }
1316 else if(1 == u32Pad)
1317 {
1318 // external TS
1319 u32Pad = TSP_MUX_TS0;
1320
1321 if(_bTsPadUsed[0] == FALSE)
1322 {
1323 TSP_TOP_REG(REG_TOP_TS0_PE) = TSP_TOP_REG(REG_TOP_TS0_PE)| REG_TOP_TS0_PE_MASK;
1324 _bTsPadUsed[0] = TRUE;
1325 }
1326 }
1327 else
1328 {
1329 // external TS
1330 u32Pad = TSP_MUX_TS1;
1331
1332 if(_bTsPadUsed[1] == FALSE)
1333 {
1334 TSP_TOP_REG(REG_TOP_TS1_PE) = TSP_TOP_REG(REG_TOP_TS1_PE)| REG_TOP_TS1_PE_MASK;
1335 _bTsPadUsed[1] = TRUE;
1336 }
1337 }
1338 _u32FlowPadMap[u32Flow] = u32Pad;
1339
1340 if(u32Flow == 0)
1341 u32Shft= REG_TOP_TSN_MUX_TS0_SHIFT;
1342 else
1343 u32Shft = REG_TOP_TSN_MUX_TS1_SHIFT;
1344
1345 TSP_TOP_REG(REG_TOP_TSN_MUX) = (TSP_TOP_REG(REG_TOP_TSN_MUX) & ~(REG_TOP_TSN_MUX_MASK<< u32Shft)) | (u32Pad<< u32Shft);
1346
1347 }
1348
HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId,MS_U32 u32Flow,MS_BOOL bClkInv)1349 void HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bClkInv)
1350 {
1351 MS_U32 u32Clk = 0;
1352 MS_U32 u32Shft = 0;
1353
1354 if(u32Flow >= TSP_IF_NUM)
1355 {
1356 return;
1357 }
1358
1359 if(_u32FlowPadMap[u32Flow] == TSP_MUX_INDEMOD)
1360 u32Clk = TSP_CLK_INDEMOD;
1361 else if(_u32FlowPadMap[u32Flow] == TSP_MUX_TS1)
1362 u32Clk = TSP_CLK_TS1;
1363 else
1364 u32Clk = TSP_CLK_TS0;
1365
1366 if (bClkInv)
1367 {
1368 u32Clk |= TSP_CLK_INVERSE;
1369 }
1370
1371 u32Shft = (0 == u32Flow)? 0: 8;
1372 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< u32Shft)) | (u32Clk<< u32Shft);
1373 }
1374
HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId,MS_BOOL bExtSync,MS_U32 u32Flow)1375 void HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId, MS_BOOL bExtSync, MS_U32 u32Flow)
1376 {
1377 REG32* pReg = NULL;
1378 MS_U32 u32ExtSync = 0;
1379
1380 if (0 == u32Flow)
1381 {
1382 pReg = &(_TspCtrl[0].Hw_Config0);
1383 u32ExtSync = TSP_HW_CFG0_TSIF0_EXTSYNC;
1384 }
1385 else if (1 == u32Flow)
1386 {
1387 pReg = &(_TspCtrl[0].Hw_Config2);
1388 u32ExtSync = TSP_HW_CFG2_TSIF1_EXTSYNC;
1389 }
1390 else
1391 {
1392 //ASSERT(0);
1393 return;
1394 }
1395
1396 if (bExtSync)
1397 {
1398 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32ExtSync));
1399 }
1400 else
1401 {
1402 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32ExtSync));
1403 }
1404 }
1405
HAL_TSP_SelPad_Parl(MS_U32 u32EngId,MS_BOOL bParl,MS_U32 u32Flow)1406 void HAL_TSP_SelPad_Parl(MS_U32 u32EngId, MS_BOOL bParl, MS_U32 u32Flow)
1407 {
1408 REG32* pReg = NULL;
1409 MS_U32 u32Parl = 0;
1410 MS_U32 u32Pad = 0;
1411 if (0 == u32Flow) // TS_IF0
1412 {
1413 pReg = &(_TspCtrl[0].Hw_Config0);
1414 u32Parl = TSP_HW_CFG0_TSIF0_PARL;
1415 }
1416 else if (1 == u32Flow) // TS_IF1
1417 {
1418 pReg = &(_TspCtrl[0].Hw_Config2);
1419 u32Parl = TSP_HW_CFG2_TSIF1_PARL;
1420 }
1421 else
1422 {
1423 //ASSERT(0);
1424 return;
1425 }
1426
1427 u32Pad = _u32FlowPadMap[u32Flow];
1428 if (bParl) // parallel
1429 {
1430 switch (u32Pad)
1431 {
1432 case TSP_MUX_TS0:
1433 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~REG_TOP_TS_TS0_CFG_MASK) | REG_TOP_TS_TS0_CFG_PARALLEL;
1434 break;
1435 case TSP_MUX_TS1:
1436 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~REG_TOP_TS_TS1_CFG_MASK) | REG_TOP_TS_TS1_CFG_PARALLEL;
1437 break;
1438 default:
1439 break;
1440 }
1441 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32Parl));
1442 }
1443 else // serial
1444 {
1445 switch (u32Pad)
1446 {
1447 case TSP_MUX_TS0:
1448 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~REG_TOP_TS_TS0_CFG_MASK) | REG_TOP_TS_TS0_CFG_SERIAL;
1449 break;
1450 case TSP_MUX_TS1:
1451 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~REG_TOP_TS_TS1_CFG_MASK) | REG_TOP_TS_TS1_CFG_SERIAL;
1452 break;
1453 default:
1454 break;
1455 }
1456 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32Parl));
1457 }
1458 }
1459
HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId,MS_U32 u32Flow,MS_BOOL bInvert)1460 void HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bInvert)
1461 {
1462 REG32* pReg = &(_TspCtrl[0].Hw_Config4);
1463 MS_U32 u32Invert = 0;
1464
1465 if(0 == u32Flow)
1466 {
1467 u32Invert = TSP_HW_CFG4_TS_DATA0_SWAP;
1468 }
1469 else if(1 == u32Flow)
1470 {
1471 u32Invert = TSP_HW_CFG4_TS_DATA1_SWAP;
1472 }
1473 else
1474 {
1475 return;
1476 }
1477
1478 if(bInvert)
1479 {
1480 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32Invert));
1481 }
1482 else
1483 {
1484 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32Invert));
1485 }
1486 }
1487
HAL_TSP_GetCap(MS_U32 u32Cap,void * pData)1488 MS_BOOL HAL_TSP_GetCap(MS_U32 u32Cap, void* pData)
1489 {
1490 MS_BOOL bRet = TRUE;
1491
1492 switch (u32Cap)
1493 {
1494 case HAL_TSP_CAP_PID_FILTER_NUM:
1495 *((MS_U32*)pData) = TSP_PIDFLT_NUM_ALL;
1496 break;
1497 case HAL_TSP_CAP_SEC_FILTER_NUM:
1498 *((MS_U32*)pData) = TSP_SECFLT_NUM;
1499 break;
1500 case HAL_TSP_CAP_SEC_BUF_NUM:
1501 *((MS_U32*)pData) = TSP_SECBUF_NUM;
1502 break;
1503 case HAL_TSP_CAP_PVR_ENG_NUM:
1504 *((MS_U32*)pData) = TSP_PVR_IF_NUM;
1505 break;
1506 case HAL_TSP_CAP_PVR_FILTER_NUM:
1507 *((MS_U32*)pData) = TSP_PIDFLT1_NUM;
1508 break;
1509 case HAL_TSP_CAP_MMFI_AUDIO_FILTER_NUM:
1510 *((MS_U32*)pData) = TSP_MMFI_AUDIO_FILTER_NUM;
1511 break;
1512 case HAL_TSP_CAP_MMFI_V3D_FILTER_NUM:
1513 *((MS_U32*)pData) = TSP_MMFI_V3D_FILTER_NUM;
1514 break;
1515 case HAL_TSP_CAP_TSIF_NUM:
1516 *((MS_U32*)pData) = TSP_IF_NUM;
1517 break;
1518 case HAL_TSP_CAP_DEMOD_NUM:
1519 *((MS_U32*)pData) = TSP_DEMOD_NUM;
1520 break;
1521 case HAL_TSP_CAP_VFIFO_NUM:
1522 *((MS_U32*)pData) = TSP_VFIFO_NUM;
1523 break;
1524 case HAL_TSP_CAP_AFIFO_NUM:
1525 *((MS_U32*)pData) = TSP_AFIFO_NUM;
1526 break;
1527 case HAL_TSP_CAP_TS_PAD_NUM:
1528 *((MS_U32*)pData) = TSP_TS_PAD_NUM;
1529 break;
1530 case HAL_TSP_CAP_VQ_NUM:
1531 *((MS_U32*)pData) = TSP_VQ_NUM;
1532 break;
1533 case HAL_TSP_CAP_CA_FLT_NUM:
1534 *((MS_U32*)pData) = TSP_CA_FLT_NUM;
1535 break;
1536 case HAL_TSP_CAP_CA_KEY_NUM:
1537 *((MS_U32*)pData) = TSP_CA_KEY_NUM;
1538 break;
1539 case HAL_TSP_CAP_FW_ALIGN:
1540 *((MS_U32*)pData) = (1L << (MIU_BUS+TSP_DNLD_ADDR_ALI_SHIFT));
1541 break;
1542 case HAL_TSP_CAP_VQ_ALIGN:
1543 case HAL_TSP_CAP_SEC_BUF_ALIGN:
1544 case HAL_TSP_CAP_PVR_ALIGN:
1545 *((MS_U32*)pData) = (1L << MIU_BUS);
1546 break;
1547 case HAL_TSP_CAP_VQ_PITCH:
1548 *((MS_U32*)pData) = VQ_PACKET_UNIT_LEN;
1549 break;
1550 case HAL_TSP_CAP_PVRCA_PATH_NUM:
1551 *((MS_U32*)pData) = 1;
1552 break;
1553 case HAL_TSP_CAP_PVRCA0_FLT_RANGE:
1554 *((MS_U32*)pData) = TSP_SECFLT_NUM;
1555 *((MS_U32*)pData + 1) = TSP_SECFLT_NUM + TSP_PIDFLT1_NUM - 1;
1556 break;
1557 case HAL_TSP_CAP_PVRCA1_FLT_RANGE:
1558 case HAL_TSP_CAP_PVR1_FILTER_NUM:
1559 case HAL_TSP_CAP_SHAREKEY_FLT_RANGE:
1560 *((MS_U32*)pData) = 0;
1561 break;
1562 case HAL_TSP_CAP_HW_TYPE:
1563 *((MS_U32*)pData) = 0x00001001;
1564 break;
1565
1566 case HAL_TSP_CAP_HWPCR_SUPPORT:
1567 *((MS_U32*)pData) = 0;
1568 break;
1569
1570 case HAL_TSP_CAP_HWWP_SET_NUM:
1571 *((MS_U32*)pData) = TSP_WP_SET_NUM;
1572 break;
1573
1574 case HAL_TSP_CAP_DSCMB_ENG_NUM:
1575 *((MS_U32*)pData) = 1;
1576 break;
1577 case HAL_TSP_CAP_MAX_SEC_FLT_DEPTH:
1578 *((MS_U32*)pData) = TSP_SEC_FLT_DEPTH;
1579 break;
1580 case HAL_TSP_CAP_FW_BUF_SIZE:
1581 *((MS_U32*)pData) = TSP_FW_BUF_SIZE;
1582 break;
1583 case HAL_TSP_CAP_FW_BUF_RANGE:
1584 *((MS_U32*)pData) = TSP_FW_BUF_LOW_BUD;
1585 *((MS_U32*)pData+1) = TSP_FW_BUF_UP_BUD;
1586 break;
1587 case HAL_TSP_CAP_VQ_BUF_RANGE:
1588 *((MS_U32*)pData) = TSP_VQ_BUF_LOW_BUD;
1589 *((MS_U32*)pData+1) = TSP_VQ_BUF_UP_BUD;
1590 break;
1591 case HAL_TSP_CAP_SEC_BUF_RANGE:
1592 *((MS_U32*)pData) = TSP_SEC_BUF_LOW_BUD;
1593 *((MS_U32*)pData+1) = TSP_SEC_BUF_UP_BUD;
1594 break;
1595 case HAL_TSP_CAP_FIQ_NUM:
1596 *((MS_U32*)pData) = TSP_FIQ_NUM;
1597 break;
1598 default:
1599 *((MS_U32*)pData) = 0xFFFFFFFF;
1600 bRet = FALSE;
1601 break;
1602 }
1603 return bRet;
1604
1605 }
1606
HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable)1607 void HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable)
1608 {
1609 if(bEnable)
1610 {
1611 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1612 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | (TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV));
1613 }
1614 else
1615 {
1616 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1617 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~(TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV));
1618 }
1619 }
1620
HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId,MS_BOOL bEnable)1621 void HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId, MS_BOOL bEnable)
1622 {
1623 MS_U32 u32Flag[4] = {TSP_DUP_PKT_SKIP_VD, TSP_DUP_PKT_SKIP_AV, 0, TSP_DUP_PKT_SKIP_V3D};
1624
1625 if(u32StreamId == 2)
1626 return;
1627
1628 if(bEnable)
1629 {
1630 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1631 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | u32Flag[u32StreamId]);
1632 }
1633 else
1634 {
1635 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1636 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~u32Flag[u32StreamId]);
1637 }
1638 }
1639
HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId,MS_U16 * pu16Pad,MS_U16 * pu16Clk,MS_BOOL * pbExtSync,MS_BOOL * pbParl)1640 MS_BOOL HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId, MS_U16* pu16Pad, MS_U16* pu16Clk, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
1641 {
1642 MS_U16 u16pad;
1643 MS_U32 u32data;
1644
1645 *pu16Pad = 0xFFFF;
1646 *pu16Clk = TSP_CLK_DISABLE;
1647 *pbExtSync = FALSE;
1648 *pbParl = FALSE;
1649
1650 u16pad = TSP_TOP_REG(REG_TOP_TSN_MUX);
1651
1652 switch(u8TsIfId)
1653 {
1654 case 0:
1655 u16pad >>= REG_TOP_TSN_MUX_TS0_SHIFT;
1656 *pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK;
1657 u32data = _HAL_REG32_R(&_TspCtrl[0].Hw_Config0);
1658 *pbExtSync = ((u32data & TSP_HW_CFG0_TSIF0_EXTSYNC) == TSP_HW_CFG0_TSIF0_EXTSYNC);
1659 *pbParl = ((u32data & TSP_HW_CFG0_TSIF0_PARL) == TSP_HW_CFG0_TSIF0_PARL);
1660 break;
1661 case 1:
1662 u16pad >>= REG_TOP_TSN_MUX_TS1_SHIFT;
1663 *pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK;
1664 u32data = _HAL_REG32_R(&_TspCtrl[0].Hw_Config2);
1665 *pbExtSync = ((u32data & TSP_HW_CFG2_TSIF1_EXTSYNC) == TSP_HW_CFG2_TSIF1_EXTSYNC);
1666 *pbParl = ((u32data & TSP_HW_CFG2_TSIF1_PARL) == TSP_HW_CFG2_TSIF1_PARL);
1667 break;
1668 default:
1669 return FALSE;
1670 }
1671
1672 *pu16Pad = u16pad & REG_TOP_TSN_MUX_MASK;
1673
1674 return TRUE;
1675 }
1676
HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId)1677 MS_BOOL HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId)
1678 {
1679 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].Idr_Read1);
1680
1681 switch (u32StreamId)
1682 {
1683 case 0: // return VFifo status
1684 return ((u32data & TSP_VD_FIFO_OVERFLOW) == TSP_VD_FIFO_OVERFLOW);
1685 case 1: // return AFifo 0 status
1686 return ((u32data & TSP_AU_FIFO_OVERFLOW) == TSP_AU_FIFO_OVERFLOW);
1687 case 3: // return V3D Fifo status
1688 return ((u32data & TSP_V3D_FIFO_OVERFLOW) == TSP_V3D_FIFO_OVERFLOW);
1689 default:
1690 return FALSE;
1691 }
1692 }
1693
1694 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1695 // Macro function
1696 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
_HAL_TSP_FW_load(MS_PHY phyFwAddrPhys,MS_U32 u32FwSize,MS_BOOL bFwDMA,MS_BOOL bIQmem,MS_BOOL bDQmem)1697 static void _HAL_TSP_FW_load(
1698 MS_PHY phyFwAddrPhys,
1699 MS_U32 u32FwSize,
1700 MS_BOOL bFwDMA,
1701 MS_BOOL bIQmem,
1702 MS_BOOL bDQmem)
1703 {
1704 MS_U32 u32Value = 0x0;
1705
1706 // bDQmem is always true
1707 MS_ASSERT(bDQmem);
1708
1709 _phyOrLoadMiuOffset = _HAL_TSP_MIU_OFFSET(phyFwAddrPhys);
1710
1711 _HAL_REG32_W(&_TspCtrl2[0].Qmem_Config,
1712 SET_FLAG1(_HAL_REG32_R(&_TspCtrl2[0].Qmem_Config), TSP_TSP_SEL_SRAM));
1713
1714 // @FIXME: Richard: Only allow TSP FW running in DRAM at this first stage.
1715 // improve this afterward.
1716 MS_ASSERT(phyFwAddrPhys & TSP_CPU_BASE_ADDR_MASK);
1717 _HAL_REG32_W(&_TspCtrl[0].Cpu_Base, 0/*u32FwAddrPhys >> 3*/); // 16 bytes address unit
1718
1719 if (bFwDMA)
1720 {
1721 MS_U32 u32DnldCtrl = 0;
1722 MS_U32 u32DnldCtrl1 = 0;
1723 u32DnldCtrl = (MS_U32)(((phyFwAddrPhys-_phyOrLoadMiuOffset) >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT) & TSP_DNLD_ADDR_MASK;
1724 u32DnldCtrl1 = (MS_U32)((((phyFwAddrPhys-_phyOrLoadMiuOffset) >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT) & TSP_DNLD_ADDR_MASK1) >> TSP_DNLD_ADDR_SHFT1;
1725 printf("firmware 111 0x%08lx 0x%08lx 0x%08lx\n", (unsigned long)phyFwAddrPhys, (unsigned long)u32DnldCtrl1, (unsigned long)u32DnldCtrl);
1726
1727 u32DnldCtrl |= (_TSP_QMEM_SIZE << TSP_DNLD_NUM_SHFT);
1728
1729 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl, u32DnldCtrl);
1730 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2, (_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2) & ~(TSP_DNLD_ADDR_MASK1 >> TSP_DNLD_ADDR_SHFT1)) | u32DnldCtrl1);
1731 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1732 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE));
1733 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1734 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START));
1735 while (!HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_DONE));//printf(".");
1736 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1737 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE));
1738 }
1739
1740 _HAL_REG32_W(&_TspCtrl[0].Qmem_Imask, _TSP_QMEM_I_MASK);
1741
1742 if (bIQmem)
1743 {
1744 _HAL_REG32_W(&_TspCtrl[0].Qmem_Ibase,
1745 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Qmem_Ibase), _TSP_QMEM_I_ADDR_HIT));
1746 }
1747 else
1748 {
1749 _HAL_REG32_W(&_TspCtrl[0].Qmem_Ibase, _TSP_QMEM_I_ADDR_MISS);
1750 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1751 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_ICACHE_EN));
1752 }
1753
1754 u32Value = _HAL_REG32_R(&_TspCtrl[0].Qmem_Dmask) | _TSP_QMEM_D_MASK;
1755 _HAL_REG32_W(&_TspCtrl[0].Qmem_Dmask, u32Value);
1756
1757 u32Value = _HAL_REG32_R(&_TspCtrl[0].Qmem_Dbase) | _TSP_QMEM_D_ADDR_HIT;
1758 _HAL_REG32_W(&_TspCtrl[0].Qmem_Dbase, u32Value);
1759 }
1760
HAL_TSP_filein_enable(MS_BOOL b_enable)1761 void HAL_TSP_filein_enable(MS_BOOL b_enable)
1762 {
1763 // disable timeshift write protect -- it must enable while record/playback use the same buffer
1764 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1765 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP));
1766
1767 // Richard: enable/disable file in timer as well
1768 // file in could only walk through pid filter set 0.
1769 if (b_enable)
1770 {
1771 // Set Data port enable for audio bypass
1772 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1773 // SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1774 //_HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1775 // SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_ENABLE| TSP_CTRL1_FILEIN_TIMER_ENABLE));
1776
1777 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1778 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
1779 }
1780 else
1781 {
1782 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1783 // RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1784 //_HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1785 // RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_ENABLE| TSP_CTRL1_FILEIN_TIMER_ENABLE));
1786
1787 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1788 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
1789 }
1790 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1791 //RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1792 }
1793
_HAL_TSP_tsif_select(MS_U8 u8_tsif)1794 static void _HAL_TSP_tsif_select(MS_U8 u8_tsif)
1795 {
1796 if (u8_tsif == 1)
1797 {
1798 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1799 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1800 }
1801 else
1802 {
1803 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1804 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
1805 }
1806 }
1807
1808 /*
1809 static void _HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 PadId)
1810 {
1811 if (PadId) // TS1
1812 {
1813 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1814 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_PAD1_SEL));
1815 }
1816 else // TS0
1817 {
1818 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1819 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_PAD1_SEL));
1820 }
1821 }
1822 */
1823
HAL_TSP_PS_Path_Disable(void)1824 void HAL_TSP_PS_Path_Disable(void)
1825 {
1826 // set PS VID/AUD enable while video/audio/audio2 bypass mode
1827 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1828 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN)));
1829 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1830 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1831 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1832 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1833 }
1834
HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl)1835 void HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl)
1836 {
1837 switch (u32TsDmaCtrl)
1838 {
1839 case TSP_TSDMA_CTRL_VPES0:
1840 if((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PS_VID_EN) == 0)
1841 {
1842 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1843 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_AUD_EN));
1844 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1845 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1846
1847 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1848 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1849 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1850 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_VID_EN));
1851 }
1852 break;
1853 case TSP_TSDMA_CTRL_APES0:
1854 if((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PS_AUD_EN) == 0)
1855 {
1856 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1857 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_VID_EN));
1858 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1859 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1860
1861 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1862 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1863 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1864 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_AUD_EN));
1865 }
1866 break;
1867 case TSP_TSDMA_CTRL_V3DPES0:
1868 if((_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2) & TSP_PS_VID3D_EN) == 0)
1869 {
1870 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1871 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN)));
1872
1873 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1874 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1875 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1876 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1877 }
1878 break;
1879 default:
1880 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1881 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN)));
1882 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1883 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1884 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1885 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1886 break;
1887 }
1888 }
1889
HAL_TSP_GetCtrlMode(MS_U32 u32EngId)1890 MS_U32 HAL_TSP_GetCtrlMode(MS_U32 u32EngId)
1891 {
1892 return (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl));
1893 }
1894
HAL_TSP_DoubleBuf_En(MS_BOOL bBuf_Sel)1895 void HAL_TSP_DoubleBuf_En(MS_BOOL bBuf_Sel)
1896 {
1897 if (bBuf_Sel)
1898 {
1899 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | (TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_DESC));
1900 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~TSP_DOUBLE_BUF_SWITCH);
1901 }
1902 else
1903 {
1904 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE));
1905 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | (TSP_DOUBLE_BUF_SWITCH|TSP_DOUBLE_BUF_DESC));
1906 }
1907 //_HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | TSP_DOUBLE_BUF_DESC);
1908 }
1909
HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId,MS_BOOL bFlush)1910 void HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId, MS_BOOL bFlush)
1911 {
1912 MS_U32 u32Flag;
1913
1914 switch(u32StreamId)
1915 {
1916 case 0:
1917 u32Flag = TSP_RESET_VFIFO;
1918 break;
1919 case 1:
1920 u32Flag = TSP_RESET_AFIFO;
1921 break;
1922 case 3:
1923 u32Flag = TSP_RESET_VFIFO3D;
1924 break;
1925 default:
1926 return;
1927 }
1928 if (bFlush)
1929 {
1930 _HAL_REG32_W(&_TspCtrl[0].reg160C,
1931 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), u32Flag));
1932 }
1933 else
1934 {
1935 _HAL_REG32_W(&_TspCtrl[0].reg160C,
1936 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), u32Flag));
1937 }
1938 }
1939
1940 #define ADDR_AVFIFO_STATUS (_virtRegBase+ 0x2adc)
HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId)1941 MS_U32 HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId)
1942 {
1943 switch (u32StreamId)
1944 {
1945 case 0: // return VFifo status
1946 return (((REG16_T(ADDR_AVFIFO_STATUS))>>4)&0x0f);
1947 case 1: // return AFifo 0 status
1948 return (((REG16_T(ADDR_AVFIFO_STATUS))>>8)&0x0f);
1949 case 3: // return V3D Fifo status
1950 return (REG16_T(ADDR_AVFIFO_STATUS)&0x0f);
1951 default:
1952 return -1;
1953 }
1954 }
1955 #undef ADDR_AVFIFO_STATUS
1956
HAL_TSP_Ind_Enable(void)1957 void HAL_TSP_Ind_Enable(void)
1958 {
1959 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1960 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
1961 }
1962
HAL_TSP_HW_INT_STATUS(void)1963 MS_U32 HAL_TSP_HW_INT_STATUS(void)
1964 {
1965 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat) & TSP_HWINT_STATUS_MASK);
1966 }
1967
HAL_TSP_SetBank(MS_VIRT u32NonPmBankAddr,MS_VIRT u32PmBankAddr)1968 void HAL_TSP_SetBank(MS_VIRT u32NonPmBankAddr, MS_VIRT u32PmBankAddr)
1969 {
1970 _virtRegBase = u32NonPmBankAddr;
1971 _TspCtrl = (REG_Ctrl*)(_virtRegBase + REG_CTRL_BASE);
1972 _TspCtrl2 = (REG_Ctrl2*)(_virtRegBase + REG_CTRL_MMFIBASE);
1973 _TspCtrl3 = (REG_Ctrl3*)(_virtRegBase + REG_CTRL_BASE_TS3);
1974 }
1975
HAL_TSP_Reset(MS_U32 u32EngId)1976 void HAL_TSP_Reset(MS_U32 u32EngId)
1977 {
1978 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl, 0);
1979 }
1980
HAL_TSP_HwPatch(void)1981 void HAL_TSP_HwPatch(void)
1982 {
1983 _HAL_REG32_W(&_TspCtrl2[0].Qmem_Config,
1984 SET_FLAG1(_HAL_REG32_R(&_TspCtrl2[0].Qmem_Config), TSP_TSP_SEL_SRAM));
1985
1986 // To prevent the race condition of accessing section filter registers from HW/CPU.
1987 // It's a HW bug.
1988 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1989 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_ISYNC_PATCH_EN));
1990
1991 // Bad initial value of TSP_CTRL1
1992 // Suppose Standby mode for TSP should NOT be enabled.
1993 // Enabling TSP standby mode cause TSP section registers (SRAM in AEON) malfunction.
1994 // Disable it by SW at this stage.
1995 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1996 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_STANDBY));
1997
1998 // @FIXME: disable not match mask
1999 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2000 _HAL_REG32_R(&_TspCtrl[0].reg15b4)|TSP_NMATCH_DIS);
2001
2002 // Jericho helps
2003 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2004 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), 0xFFFF0000));
2005 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2006 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), 0xBBBB0000));
2007
2008 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2009 #ifdef VQ_ENABLE
2010 _HAL_REG32_R(&_TspCtrl[0].reg160C)| (TSP_RM_DMA_GLITCH|TSP_DOUBLE_BUF_DESC));
2011 #else
2012 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RM_DMA_GLITCH));
2013 #endif
2014
2015 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2016 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) |
2017 (TSP_SYSTIME_MODE_STC64|TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV));
2018
2019 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2020 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PREVENT_OVF_META));
2021
2022 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
2023 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), (TSP_STR2MI_WP_LD|TSP_RM_OVERFLOW_GLITCH))); //improve pvr performance
2024
2025
2026 // Set match PID, default is AV FIFO
2027 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2028 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_AVPID_ST_AV));
2029
2030 // Set PUSI 3 byte mode for Audio
2031 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
2032 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_PUSI_3BYTE_MODE));
2033
2034 // 2p sram setting
2035 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2036 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_HW_STANDBY_MODE));
2037 _HAL_REG32_W(&_TspCtrl3[0].Hw_Config,
2038 SET_FLAG1(_HAL_REG32_R(&_TspCtrl3[0].Hw_Config), TSP_PREVENT_SRAM_COLLISION));
2039
2040 // Set filein segment bit to 0
2041 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2042 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
2043
2044 _HAL_REG16_W(&_TspCtrl2[0].HwCfg1,
2045 SET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg1), (AF_PKT_LOSS_BYTE_ECO|UPDATE_SCRAMBLE_PID_PUSI|NEW_OVERFLOW_MODE|FIX_PINPON_SYNC_IN_ECO)));
2046
2047 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0, _HAL_REG16_R(&_TspCtrl2[0].HwCfg0) | (PREVENT_SRAM_COLLISION|MASK_SCR_VID_EN|MASK_SCR_VID_3D_EN|MASK_SCR_AUD_EN));
2048
2049 _HAL_REG16_W(&_TspCtrl2[0].HwCfg2, _HAL_REG16_R(&_TspCtrl2[0].HwCfg2) | REG_RST_CC_MODE);
2050
2051 //_HAL_REG32_W(&_TspCtrl3[0].Hw_ECO, _HAL_REG32_R(&_TspCtrl3[0].Hw_ECO) | TSP_TIMESTAMP_RING | TSP_LPCR_RING);
2052 //_HAL_REG32_W(&_TspCtrl3[0].Hw_Semaphore1, _HAL_REG32_R(&_TspCtrl3[0].Hw_Semaphore1) | TSP_TIMESTAMP_ECO);
2053
2054 _b64STCMode = TRUE;
2055
2056 //VQ parameters
2057 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, (_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL) & ~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK) | (0x0C << TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT));
2058 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, (_HAL_REG32_R(&_TspCtrl[0].VQ1_Config) & ~TSP_VQ1_FORCEFIRE_CNT_1K_MASK) | (0x0C << TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT));
2059 }
2060
HAL_TSP_DoubleBuf_Disable(void)2061 void HAL_TSP_DoubleBuf_Disable(void)
2062 {
2063
2064 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2065 #ifdef VQ_ENABLE
2066 _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_SWITCH));
2067 #else
2068 _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_SWITCH|TSP_DOUBLE_BUF_DESC));
2069 #endif
2070 }
2071
2072 // Default value of low bound is 0, default value of up bound is 0xFFFFFFFF, means no protection
2073 // If set both low bound and up bound to be 0, means protection all
2074 // The range can be written: phyStartAddr <= x <= phyEndAddr
2075 // Protection range: x > phyEndAddr && x < phyStartAddr
HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable,MS_PHY phyStartAddr,MS_PHY phyEndAddr)2076 void HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY phyStartAddr, MS_PHY phyEndAddr)
2077 {
2078 MS_U32 lbnd1_8;
2079 MS_U32 ubnd1_8;
2080 MS_U32 lbnd9_24;
2081 MS_U32 ubnd9_24;
2082 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(phyStartAddr);
2083
2084 if (bEnable)
2085 {
2086 if(phyStartAddr == phyEndAddr)
2087 phyStartAddr += (1UL << MIU_BUS);
2088 else
2089 phyEndAddr -= (1UL << MIU_BUS);
2090
2091 phyStartAddr -= phyMiuOffset;
2092 phyEndAddr -= phyMiuOffset;
2093
2094 lbnd1_8 = (MS_U32)((phyStartAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) & 0x00FFUL;
2095 lbnd9_24 = (MS_U32)(((phyStartAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) >> 8UL) & 0xFFFFUL;
2096 ubnd1_8 = (MS_U32)((phyEndAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) & 0x00FFUL;
2097 ubnd9_24 = (MS_U32)(((phyEndAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) >> 8UL) & 0xFFFFUL;
2098
2099 _HAL_REG32_W(&_TspCtrl[0].reg16C0, (_HAL_REG32_R(&_TspCtrl[0].reg16C0) & ~(TSP_ORZ_DMAW_LBND_LSB8)) | lbnd1_8);
2100 _HAL_REG32_W(&_TspCtrl[0].ORZ_DMAW, (_HAL_REG32_R(&_TspCtrl[0].ORZ_DMAW) & ~(TSP_ORZ_DMAW_LBND)) | lbnd9_24);
2101 _HAL_REG32_W(&_TspCtrl[0].reg16C0, (_HAL_REG32_R(&_TspCtrl[0].reg16C0) & ~(TSP_ORZ_DMAW_UBND_LSB8)) | (ubnd1_8 << TSP_ORZ_DMAW_UBND_LSB8_SHIFT));
2102 _HAL_REG32_W(&_TspCtrl[0].ORZ_DMAW, (_HAL_REG32_R(&_TspCtrl[0].ORZ_DMAW) & ~(TSP_ORZ_DMAW_UBND)) | (ubnd9_24 << TSP_ORZ_DMAW_UBND_SHIFT));
2103
2104 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | TSP_ORZ_DMAW_PROT_EN);
2105 }
2106 else
2107 {
2108 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~TSP_ORZ_DMAW_PROT_EN);
2109 }
2110 }
2111
2112 //--------------------------------------------------------------------------------------------------
2113 // For STC part
2114 //--------------------------------------------------------------------------------------------------
HAL_TSP_Stc_ctrl(MS_U32 u32EngId,MS_U32 u32Sync)2115 void HAL_TSP_Stc_ctrl(MS_U32 u32EngId, MS_U32 u32Sync)
2116 {
2117 /////////////Set STC control by HK////////////////
2118 // select synth from chip top : bit 1 -> 0 -> controlled by HK
2119 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
2120
2121 // set HK STC synth CW
2122 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2123 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (u32Sync & 0xFFFF);
2124 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (u32Sync >> 16) & 0xFFFF;
2125
2126 // set STC synth
2127 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2128 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
2129 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2130
2131 /////////////Set STC control by TSP////////////////
2132 // select synth from TSP : bit 1 -> 1 -> controlled by TSP
2133 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;
2134
2135 // set TSP STC synth CW
2136 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2137 HAL_REG32_IndW((REG32 *)(0x0021024c<<1), u32Sync);
2138
2139 // t2 , t3 had no 0x0021025c, it was add after t4, synthesizer enable
2140 HAL_REG32_IndW((REG32 *)(0x0021025c<<1), HAL_REG32_IndR((REG32 *)(0x0021025c<<1))| 0x01);
2141 HAL_REG32_IndW((REG32 *)(0x0021025c<<1), HAL_REG32_IndR((REG32 *)(0x0021025c<<1))& ~0x01);
2142 }
2143
HAL_TSP_STC_Update_Disable(MS_U32 u32EngId,MS_BOOL bDisable)2144 void HAL_TSP_STC_Update_Disable(MS_U32 u32EngId, MS_BOOL bDisable)
2145 {
2146 if(bDisable)
2147 {
2148 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2149 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_cnt_33b_ld));
2150 }
2151 else
2152 {
2153 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2154 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_cnt_33b_ld));
2155 }
2156 }
2157
HAL_TSP_GetSTC(MS_U32 u32EngId)2158 MS_U32 HAL_TSP_GetSTC(MS_U32 u32EngId)
2159 {
2160 if(_b64STCMode)
2161 {
2162 MS_U32 u32temp;
2163
2164 u32temp = (_HAL_REG32_R(&_TspCtrl[0].TsRec_Tail2_Pcr1) & TSP_PCR1_L16_MASK) >> TSP_PCR1_L16_SHFT;
2165 u32temp |= ((_HAL_REG32_R(&_TspCtrl[0].Pcr1) & 0xFFFF) << 16);
2166 return u32temp ;
2167 }
2168 else
2169 {
2170 return HAL_REG32_IndR((REG32 *)(0x00210244<< 1));
2171 }
2172 }
2173
HAL_TSP_GetSTC_32(MS_U32 u32EngId)2174 MS_U32 HAL_TSP_GetSTC_32(MS_U32 u32EngId)
2175 {
2176 if(_b64STCMode)
2177 {
2178 MS_U32 u32temp;
2179
2180 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr1) >> 16)& 0xFFFF;
2181 u32temp |= (((_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & TSP_PCR64_H16_MASK) & 0xFFFF) << 16);
2182 return u32temp ;
2183 }
2184 else
2185 {
2186 return (HAL_REG32_IndR((REG32 *)(0x00210248<< 1)) & 0x01);
2187 }
2188 }
2189
HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)2190 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)
2191 {
2192 if (bEnable)
2193 {
2194 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_SYSTIME_MODE_STC64);
2195 }
2196 else
2197 {
2198 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_SYSTIME_MODE_STC64);
2199 }
2200
2201 _b64STCMode = bEnable;
2202 }
2203
HAL_TSP_SetSTC(MS_U32 u32EngId,MS_U32 u32STC,MS_U32 u32STC_32)2204 void HAL_TSP_SetSTC(MS_U32 u32EngId, MS_U32 u32STC, MS_U32 u32STC_32)
2205 {
2206 if(_b64STCMode)
2207 {
2208 MS_U32 u32temp;
2209
2210 u32temp = ((u32STC & 0xFFFF) << TSP_PCR1_L16_SHFT) |
2211 (_HAL_REG32_R(&_TspCtrl[0].TsRec_Tail2_Pcr1) & ~TSP_PCR1_L16_MASK);
2212 _HAL_REG32_W(&_TspCtrl[0].TsRec_Tail2_Pcr1, u32temp);
2213
2214 u32temp = ((u32STC >> 16) & 0xFFFF) | ((u32STC_32 & 0xFFFF) << 16);
2215 _HAL_REG32_W(&_TspCtrl[0].Pcr1, u32temp);
2216
2217 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_PCR64_H16_MASK) | ((u32STC_32 >> 16) & TSP_PCR64_H16_MASK);
2218 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32temp);
2219 }
2220 else
2221 {
2222 HAL_REG32_IndW((REG32 *)(0x00210244<< 1), u32STC);
2223 HAL_REG32_IndW((REG32 *)(0x00210248<< 1), u32STC_32 & 0x01);
2224 }
2225 }
2226
HAL_TSP_SetSTCOffset(MS_U32 u32EngId,MS_U32 u32Offset,MS_BOOL bAdd)2227 MS_BOOL HAL_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd)
2228 {
2229 #if 0
2230 MS_U32 u32opt = ((MS_U32)bAdd & 0xFF) << TSP_MCU_CMD_SET_STC_OFFSET_OPTION_SHIFT;
2231
2232 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Offset);
2233 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_SET_STC_OFFSET | u32opt | u32EngId);
2234
2235 while(_HAL_REG32_R(&_TspCtrl[0].MCU_Cmd) != 0);
2236
2237 return TRUE;
2238
2239 #endif
2240
2241 return FALSE;
2242 }
2243
2244
2245 #if 0
2246 void HAL_TSP_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32)
2247 {
2248 if(_b64STCMode)
2249 {
2250 MS_U32 u32temp;
2251
2252 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr1) & ~ 0xFFFF0000) | ((u32STC_32 & 0xFFFF) << 16);
2253 _HAL_REG32_W(&_TspCtrl[0].Pcr1, u32temp);
2254 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_PCR64_H16_MASK) | ((u32STC_32 >> 16) & TSP_PCR64_H16_MASK);
2255 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32temp);
2256 }
2257 else
2258 {
2259 HAL_REG32_IndW((REG32 *)(0x00210248<< 1), u32STC_32 & 0x01);
2260 }
2261 }
2262 #endif
2263
HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId,MS_U32 u32STC)2264 void HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId, MS_U32 u32STC)
2265 {
2266 _HAL_REG32_W(&_TspCtrl[0].Pcr.ML, u32STC);
2267 }
2268
HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId,MS_U32 u32STC_32)2269 void HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32)
2270 {
2271 _HAL_REG32L_W(&_TspCtrl[0].Pcr.H32, u32STC_32 & 0x01);
2272 }
2273
HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId)2274 MS_U32 HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId)
2275 {
2276 return (_HAL_REG32_R(&_TspCtrl[0].Pcr.ML));
2277 }
2278
HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId)2279 MS_U32 HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId)
2280 {
2281 return (_HAL_REG32L_R(&_TspCtrl[0].Pcr.H32) & 0x01);
2282 }
2283
HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng,MS_U8 u8Opt)2284 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Opt)
2285 {
2286 MS_U32 i = 0;
2287 MS_U32 u32Enable = 0;
2288 MS_U32 u32Cmd = 0;
2289
2290 if(u8Opt & HAL_TSP_STC_UPDATE_HK)
2291 {
2292 u32Enable = 1;
2293 }
2294 if(u8Opt & HAL_TSP_STC_UPDATE_UPDATEONCE)
2295 {
2296 u32Cmd = TSP_MCU_CMD_CTRL_STC_UPDATE_ONCE;
2297 }
2298
2299 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Enable);
2300
2301 if (u8Eng == 0)
2302 {
2303 u32Cmd |= TSP_MCU_CMD_CTRL_STC_UPDATE;
2304 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32Cmd);
2305 }
2306 else
2307 {
2308 return FALSE;
2309 }
2310
2311 while (i< 4)
2312 {
2313 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2314 {
2315 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2316 return TRUE;
2317 }
2318 i++;
2319 _delay();
2320 }
2321 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2322 return FALSE;
2323 }
HAL_TSP_GetPcr(MS_U32 u32EngId,MS_U32 * pu32Pcr_32,MS_U32 * pu32Pcr)2324 MS_BOOL HAL_TSP_GetPcr(MS_U32 u32EngId, MS_U32 *pu32Pcr_32, MS_U32 *pu32Pcr)
2325 {
2326 MS_U32 i = 0;
2327
2328 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2329 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2330 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_PCR_GET);
2331 while (i< 4)
2332 {
2333 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2334 {
2335 *pu32Pcr = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2336 *pu32Pcr_32 = _HAL_REG32_R(&_TspCtrl[0].MCU_Data1);
2337 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2338 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2339 return ((0!= *pu32Pcr) || (0!= *pu32Pcr_32))? TRUE: FALSE;
2340 }
2341 i++;
2342 _delay();
2343 }
2344 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2345 return FALSE;
2346 }
2347
HAL_TSP_CmdQ_IsEmpty(void)2348 MS_BOOL HAL_TSP_CmdQ_IsEmpty(void)
2349 {
2350 if (_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_EMPTY)
2351 {
2352 return TRUE;
2353 }
2354 return FALSE;
2355 }
2356
HAL_TSP_Int_Disable(MS_U32 u32Mask)2357 void HAL_TSP_Int_Disable(MS_U32 u32Mask)
2358 {
2359 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2360 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)(u32Mask>>8)));
2361 }
2362
HAL_TSP_Int_Enable(MS_U32 u32Mask)2363 void HAL_TSP_Int_Enable(MS_U32 u32Mask)
2364 {
2365 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2366 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)(u32Mask>>8)));
2367 }
2368
HAL_TSP_Int_ClearSw(void)2369 void HAL_TSP_Int_ClearSw(void)
2370 {
2371 if (_bIsHK)
2372 {
2373 _HAL_REG32_W(&_TspCtrl[0].SwInt_Stat, 0);
2374 }
2375 else
2376 {
2377 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_M, 0);
2378 _HAL_REG32_W(&_TspCtrl[0].SwInt_Stat1_H,
2379 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].SwInt_Stat1_H), TSP_SWINT1_H_MASK));
2380 }
2381 }
2382
HAL_TSP_Int_ClearHw(MS_U32 u32Mask)2383 void HAL_TSP_Int_ClearHw(MS_U32 u32Mask)
2384 {
2385 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2386 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)u32Mask));
2387 }
2388
HAL_TSP_CmdQ_CmdCount(void)2389 MS_U32 HAL_TSP_CmdQ_CmdCount(void)
2390 {
2391 return (((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_CNT_MASK)>>TSP_CMDQ_CNT_SHFT));
2392 }
2393
HAL_TSP_CmdQ_TsDma_Reset(void)2394 void HAL_TSP_CmdQ_TsDma_Reset(void)
2395 {
2396 _HAL_REG32_W(&_TspCtrl[0].TsDma_Ctrl_CmdQ, 0);
2397 }
2398
HAL_TSP_CmdQ_Reset(void)2399 MS_BOOL HAL_TSP_CmdQ_Reset(void)
2400 {
2401 int ii = 0;
2402 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2403 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_CMDQ_RESET));
2404 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2405 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_CMDQ_RESET));
2406
2407 //reset the last data that hw is excuting --> HW new design
2408 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0,
2409 SET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg0), TSP_TSIFCFG_WB_FSM_RESET));
2410
2411 //check R done
2412 for(ii = 0; ii < 100; ii++)
2413 {
2414 if(_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_TSDMA_RDONE)
2415 {
2416 break;
2417 }
2418 MsOS_DelayTask(1);
2419 }
2420
2421 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0,
2422 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg0), TSP_TSIFCFG_WB_FSM_RESET));
2423
2424 if(ii == 100)
2425 {
2426 printf("%s, wait fine in reset timeout\n", __FUNCTION__);
2427 return FALSE;
2428 }
2429
2430 //rst_ts_fin
2431 _HAL_REG32_W(&_TspCtrl[0].reg160C, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2432 _HAL_REG32_W(&_TspCtrl[0].reg160C, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2433
2434 return TRUE;
2435 }
2436
HAL_TSP_WbDmaEnable(MS_BOOL bEnable)2437 void HAL_TSP_WbDmaEnable(MS_BOOL bEnable)
2438 {
2439 if (bEnable)
2440 {
2441 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2442 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2443 }
2444 else
2445 {
2446 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2447 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2448 }
2449 }
2450
2451 // u32TSSrc: 0 -> TS0, 1 -> File
2452 // u32GroupId: 0 -> filter0~filter31
HAL_TSP_Scmb_Status(MS_U32 u32TSSrc,MS_U32 u32GroupId,MS_U32 u32PidFltId)2453 MS_U32 HAL_TSP_Scmb_Status(MS_U32 u32TSSrc, MS_U32 u32GroupId, MS_U32 u32PidFltId)
2454 {
2455 MS_U32 u32PIDFltMask = u32PidFltId;
2456 MS_U32 u32ScmbSts = 0;
2457
2458 if(u32PidFltId != 0xFFFFFFFF)
2459 {
2460 u32PIDFltMask = (1 << (u32PidFltId & 0x1F));
2461 }
2462
2463 if (u32TSSrc == 0)
2464 {
2465 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2466 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld));
2467
2468 u32ScmbSts = HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsPidScmbStatTsin), u32PIDFltMask);
2469
2470 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2471 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld));
2472 }
2473 else
2474 {
2475 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2476 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_fi_ld));
2477
2478 u32ScmbSts = HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsPidScmbStatFile), u32PIDFltMask);
2479
2480 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2481 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_fi_ld));
2482 }
2483
2484 if(u32PIDFltMask != 0xFFFFFFFF)
2485 {
2486 u32ScmbSts = ((u32ScmbSts > 0) ? 1: 0);
2487 }
2488
2489 return u32ScmbSts;
2490
2491 }
2492 #if 0
2493 void HAL_TSP_CPU_SetBase(MS_U32 u32Addr, MS_U32 u32Size)
2494 {
2495 #if (!LINUX_TEST)
2496 // TSP FW running in QMEM
2497 _HAL_TSP_FW_load(u32Addr, u32Size, TRUE, TRUE, TRUE);
2498 #else
2499 // only for linux
2500 // @FIXME: abstract this later
2501 void* pBuf = NULL;
2502 MS_U32 u32PhysAddr = 0;
2503
2504 #if 0
2505 if (NULL == (pBuf = MsOS_AllocateMemory (u32Size, gs32NonCachedPoolID)))
2506 {
2507 MS_ASSERT(0);
2508 }
2509
2510 memcpy(pBuf, (void*)u32Addr, u32Size);
2511 u32PhysAddr = (MS_U32)VA2PA(pBuf);
2512 printf("firmware 0x%08x 0x%08x\n", (MS_U32)pBuf, u32Addr);
2513 _HAL_TSP_FW_load(u32PhysAddr, u32Size, TRUE, TRUE, TRUE);
2514 MsOS_FreeMemory(pBuf, gs32NonCachedPoolID);
2515 #else
2516 if (NULL == (pBuf = MsOS_AllocateMemory (72*1024*1024, gs32NonCachedPoolID)))
2517 {
2518 MS_ASSERT(0);
2519 }
2520 u32PhysAddr = 60*1024*1024;
2521 memcpy(PA2KSEG1(u32PhysAddr), (void*)u32Addr, u32Size);
2522 printf("firmware 0x%08x 0x%08x\n", (MS_U32)PA2KSEG1(u32PhysAddr), u32PhysAddr);
2523 _HAL_TSP_FW_load(u32PhysAddr, u32Size, TRUE, TRUE, TRUE);
2524 MsOS_FreeMemory(pBuf, gs32NonCachedPoolID);
2525 #endif
2526 #endif
2527 }
2528 #else
HAL_TSP_CPU_SetBase(MS_PHY phyAddr,MS_U32 u32Size)2529 void HAL_TSP_CPU_SetBase(MS_PHY phyAddr, MS_U32 u32Size)
2530 {
2531 printf("[%s][%d] load firmware (address, size) = (0x%08lx, 0x%08lx)\n", __FUNCTION__, __LINE__, (unsigned long)phyAddr, (unsigned long)u32Size);
2532 _HAL_TSP_FW_load(phyAddr, u32Size, TRUE, TRUE, TRUE);
2533 }
2534
2535 #endif // #if 0
2536
HAL_TSP_Alive(void)2537 MS_BOOL HAL_TSP_Alive(void)
2538 {
2539 MS_U32 i = 0;
2540 MS_U32 u32Data;
2541
2542 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2543 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_ALIVE);
2544 while (i< 4)
2545 {
2546 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2547 {
2548 u32Data = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2549 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2550 return (TSP_MCU_DATA_ALIVE == u32Data)? TRUE: FALSE;
2551 }
2552 i++;
2553 _delay();
2554 }
2555 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2556 return FALSE;
2557 }
2558
HAL_TSP_SetOwner(REG_SecFlt * pSecFilter,MS_BOOL bOwner)2559 void HAL_TSP_SetOwner(REG_SecFlt* pSecFilter, MS_BOOL bOwner)
2560 {
2561 MS_U32 u32HkId;
2562
2563 if (_bIsHK)
2564 {
2565 u32HkId = (bOwner)? 0: 1;
2566 }
2567 else
2568 {
2569 u32HkId = (bOwner)? 1: 0;
2570 }
2571 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_OWNER_MASK) |
2572 ((u32HkId << TSP_SECFLT_OWNER_SHFT) & TSP_SECFLT_OWNER_MASK));
2573 }
2574
HAL_TSP_FileIn_Set(MS_BOOL bset)2575 void HAL_TSP_FileIn_Set(MS_BOOL bset)
2576 {
2577 if (bset)
2578 {
2579 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2580 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_FILEIN192_EN));
2581 }
2582 else
2583 {
2584 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2585 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_FILEIN192_EN));
2586 }
2587 }
2588
HAL_TSP_ResetTimeStamp(void)2589 void HAL_TSP_ResetTimeStamp(void)
2590 {
2591 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2592 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2593 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2594 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2595 }
2596
HAL_TSP_GetPVRTimeStamp(void)2597 MS_U32 HAL_TSP_GetPVRTimeStamp(void)
2598 {
2599 MS_U32 u32lpcr;
2600
2601 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2602 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_RLD));
2603 u32lpcr = _HAL_REG32_R(&_TspCtrl[0].LPcr1);
2604 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2605 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_RLD));
2606
2607 return u32lpcr;
2608 }
2609
HAL_TSP_SetPVRTimeStamp(MS_U32 u32Stamp)2610 void HAL_TSP_SetPVRTimeStamp(MS_U32 u32Stamp)
2611 {
2612 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2613 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_WLD));
2614 _HAL_REG32_W(&_TspCtrl[0].LPcr1,u32Stamp);
2615 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2616 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_WLD));
2617 }
2618
HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId,MS_U32 u32ClkSrc)2619 MS_BOOL HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId, MS_U32 u32ClkSrc)
2620 {
2621 if(u32ClkSrc == 0x0) // 90K
2622 {
2623 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2624 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PVR1_CLK_STAMP_27_EN));
2625 }
2626 else // 27M
2627 {
2628 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2629 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PVR1_CLK_STAMP_27_EN));
2630 }
2631 return TRUE;
2632 }
2633
HAL_TSP_GetPlayBackTimeStamp(void)2634 MS_U32 HAL_TSP_GetPlayBackTimeStamp(void)
2635 {
2636 MS_U32 u32lpcr;
2637
2638 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2639 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_RLD));
2640 u32lpcr = _HAL_REG32_R(&_TspCtrl[0].LPcr2);
2641 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2642 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_RLD));
2643
2644 return u32lpcr;
2645 }
2646
HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp)2647 void HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp)
2648 {
2649 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2650 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_WLD));
2651 _HAL_REG32_W(&_TspCtrl[0].LPcr2,u32Stamp);
2652 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2653 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_WLD));
2654 }
2655
HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id,MS_U32 u32ClkSrc)2656 MS_BOOL HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id, MS_U32 u32ClkSrc)
2657 {
2658 if(u32ClkSrc == 0x0) // 90K
2659 {
2660 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2661 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_TSIF0_CLK_STAMP_27_EN));
2662 }
2663 else // 27M
2664 {
2665 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2666 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_TSIF0_CLK_STAMP_27_EN));
2667 }
2668 return TRUE;
2669 }
2670
HAL_TSP_GetFileInTimeStamp(void)2671 MS_U32 HAL_TSP_GetFileInTimeStamp(void)
2672 {
2673 return _HAL_REG32_R(&_TspCtrl[0].TimeStamp_FileIn);
2674 }
2675
HAL_TSP_GetFilinReadAddr(MS_PHY * pphyReadAddr)2676 MS_BOOL HAL_TSP_GetFilinReadAddr(MS_PHY* pphyReadAddr)
2677 {
2678 *pphyReadAddr = ((MS_PHY)_HAL_REG32_R(&_TspCtrl[0].TsFileIn_RPtr) << MIU_BUS) + _phyFIBufMiuOffset;
2679
2680 return TRUE;
2681 }
2682
HAL_TSP_SetDMABurstLen(MS_U32 u32Len)2683 void HAL_TSP_SetDMABurstLen(MS_U32 u32Len)
2684 {
2685 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2686 _HAL_REG32_R(&_TspCtrl[0].Hw_Config4) | ((u32Len<<TSP_HW_DMA_MODE_SHIFT)&TSP_HW_DMA_MODE_MASK));
2687 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2688 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_SEC_DMA_BURST_EN));
2689 }
2690
HAL_TSP_PVR_PacketMode(MS_BOOL bSet)2691 void HAL_TSP_PVR_PacketMode(MS_BOOL bSet)
2692 {
2693 if (bSet)
2694 {
2695 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2696 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RECORD192_EN));
2697 }
2698 else
2699 {
2700 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2701 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RECORD192_EN));
2702 }
2703 }
2704
HAL_ResetAll(void)2705 void HAL_ResetAll(void)
2706 {
2707 printf("Reset ALL registers\n");
2708 //_HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2709 // SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_CPU_EN));
2710 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2711 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2712 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2713 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2714 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2715 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
2716
2717 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2718 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2719 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2720 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2721 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2722 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
2723 }
2724
2725
2726 #define CKG_TS0_TS1 0x16A0UL //0x28
2727 #define CLK_TS0_DISABLE 0x0001UL
2728 #define CLK_TS0_INVERT 0x0002UL
2729 #define CLK_TS0_CLK_MASK 0x001CUL
2730 #define CLK_TS1_DISABLE 0x0100UL
2731 #define CLK_TS1_INVERT 0x0200UL
2732 #define CLK_TS1_CLK_MASK 0x1C00UL
2733 #define CKG_TSP_STC0 0x16A8UL //0x2a
2734 #define CLK_TSP_DISABLE 0x0001UL
2735 #define CLK_TSP_INVERT 0x0002UL
2736 #define CLK_TSP_CLK_MASK 0x000CUL
2737 #define CLK_PAR_DISABLE 0x0010UL
2738 #define CLK_PAR_INVERT 0x0020UL
2739 #define CLK_PAR_CLK_MASK 0x0040UL
2740 #define CLK_PAR_CLK_192 0x0040UL
2741 #define CLK_STC_DISABLE 0x0100UL
2742 #define CLK_STC_INVERT 0x0200UL
2743 #define CLK_STC_CLK_MASK 0x0C00UL
2744 #define CKG_TSP_STAMP 0x16ACUL //0x2b
2745 #define CLK_SYN_STC0_MASK 0x0007UL
2746 #define CLK_SYN_STC0_432M 0x0001UL
2747 #define CLK_STAM_DISABLE 0x0100UL
2748 #define CLK_STAM_INVERT 0x0200UL
2749 #define CLK_STAM_CLK_MASK 0x0C00UL
2750 #define CKG2_TSP_TS_SAMPLE 0x1464UL //0x019
2751 #define CKG2_TSP_TS_SAMPLE_DISABLE 0x0010UL
2752 #define CKG2_TSP_TS_SAMPLE_INVERT 0x0020UL
2753 #define CKG2_TSP_TS_SAMPLE_CLK_MASK 0x00C0UL
2754 #define CHIP_TSP_BOOT_CLK_SEL 0x3D68 //0x5a
2755 #define CHIP_TSP_BOOT_CLK_SEL_MASK 0x0020
2756
HAL_TSP_PowerCtrl(MS_BOOL bOn)2757 void HAL_TSP_PowerCtrl(MS_BOOL bOn)
2758 {
2759 if (bOn)
2760 {
2761 //Set PE Pad
2762 //TSP_TOP_REG(REG_TOP_TS0_PE) |= REG_TOP_TS0_PE_MASK;
2763
2764 // Enable TSP Clock
2765 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2766 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_TSP_DISABLE|CLK_TSP_INVERT|CLK_TSP_CLK_MASK)));
2767
2768 // Enable CLK_PARSER clock
2769 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2770 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_DISABLE|CLK_PAR_INVERT|CLK_PAR_CLK_MASK)));
2771 //Set CLK_PARSER_192
2772 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2773 SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_CLK_192)));
2774
2775 //TSP select SRAM
2776 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL)), CHIP_TSP_BOOT_CLK_SEL_MASK));
2777
2778 //Select SRAM
2779 _HAL_REG32_W(&(_TspCtrl2[0].Qmem_Config), SET_FLAG1(_HAL_REG32_R(&(_TspCtrl2[0].Qmem_Config)), TSP_TSP_SEL_SRAM));
2780
2781 // Enable TS0 clock
2782 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),
2783 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS0_DISABLE|CLK_TS0_INVERT|CLK_TS0_CLK_MASK)));
2784
2785 // Enable TS1 clock
2786 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),
2787 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS1_DISABLE|CLK_TS1_INVERT|CLK_TS1_CLK_MASK)));
2788
2789 // Set SYN_STC to be 432MHz
2790 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),
2791 SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), CLK_SYN_STC0_432M));
2792
2793 // Enable STC clock
2794 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2795 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_STC_DISABLE|CLK_STC_INVERT|CLK_STC_CLK_MASK)));
2796
2797 // Enable TIMESTAMP clock
2798 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),
2799 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INVERT|CLK_STAM_CLK_MASK)));
2800
2801 // Enable Sample clock
2802 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE),
2803 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), (CKG2_TSP_TS_SAMPLE_DISABLE|CKG2_TSP_TS_SAMPLE_INVERT|CKG2_TSP_TS_SAMPLE_CLK_MASK)));
2804
2805 }
2806 else
2807 {
2808 // Disable TSP clock
2809 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_TSP_DISABLE));
2810
2811 // Disable TS0 clock
2812 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), CLK_TS0_DISABLE));
2813
2814 // Disable TS1 clock
2815 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), CLK_TS1_DISABLE));
2816
2817 // Disable STC clock
2818 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_STC_DISABLE));
2819
2820 // Disable CLK_PARSER clock
2821 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_PAR_DISABLE));
2822
2823 // Disable TIMESTAMP clock
2824 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), CLK_STAM_DISABLE));
2825
2826 // Disable Sample clock
2827 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), CKG2_TSP_TS_SAMPLE_DISABLE));
2828
2829 //Reset PE Pad
2830 if(_bTsPadUsed[0] == TRUE)
2831 {
2832 TSP_TOP_REG(REG_TOP_TS0_PE) &= ~REG_TOP_TS0_PE_MASK;
2833 _bTsPadUsed[0] = FALSE;
2834 }
2835 else if(_bTsPadUsed[1] == TRUE)
2836 {
2837 TSP_TOP_REG(REG_TOP_TS1_PE) &= ~REG_TOP_TS1_PE_MASK;
2838 _bTsPadUsed[1] = FALSE;
2839 }
2840
2841 }
2842 }
2843
2844 #undef CKG_TS0_TS1
2845 #undef CLK_TS0_DISABLE
2846 #undef CLK_TS0_INVERT
2847 #undef CLK_TS0_CLK_MASK
2848 #undef CKG_TSP_STC0
2849 #undef CLK_TSP_DISABLE
2850 #undef CLK_TSP_INVERT
2851 #undef CLK_TSP_CLK_MASK
2852 #undef CLK_PAR_DISABLE
2853 #undef CLK_PAR_INVERT
2854 #undef CLK_PAR_CLK_MASK
2855 #undef CLK_PAR_CLK_192
2856 #undef CLK_STC_DISABLE
2857 #undef CLK_STC_INVERT
2858 #undef CLK_STC_CLK_MASK
2859 #undef CKG_TSP_STAMP
2860 #undef CLK_SYN_STC0_MASK
2861 #undef CLK_SYN_STC0_432M
2862 #undef CLK_STAM_DISABLE
2863 #undef CLK_STAM_INVERT
2864 #undef CLK_STAM_CLK_MASK
2865 #undef CKG2_TSP_TS_SAMPLE
2866 #undef CKG2_TSP_TS_SAMPLE_DISABLE
2867 #undef CKG2_TSP_TS_SAMPLE_INVERT
2868 #undef CKG2_TSP_TS_SAMPLE_CLK_MASK
2869 #undef CHIP_TSP_BOOT_CLK_SEL
2870 #undef CHIP_TSP_BOOT_CLK_SEL_MASK
2871
2872
HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel)2873 MS_U32 HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel)
2874 {
2875 _HAL_REG32_W(&_TspCtrl[0].PKT_CNT, TSP_DBG_SEL_MASK&(u32dbgsel<<TSP_DBG_SEL_SHIFT));
2876 return (_HAL_REG32_R(&_TspCtrl[0].TSP_Debug)&TSP_DEBUG_MASK);
2877 }
2878
HAL_TSP_Enable_ValidSync_Dectect(void)2879 void HAL_TSP_Enable_ValidSync_Dectect(void)
2880 {
2881 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2882 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_VALID_FALLING_DETECT));
2883 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2884 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_SYNC_RISING_DETECT));
2885 }
2886
HAL_Reset_WB(void)2887 void HAL_Reset_WB(void)
2888 {
2889 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2890 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2891 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2892 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2893 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2894 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2895 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2896 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2897 }
2898
HAL_TSP_Get_FW_VER(void)2899 MS_U32 HAL_TSP_Get_FW_VER(void)
2900 {
2901 MS_U32 i = 0;
2902 MS_U32 u32Data = 0;
2903
2904 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2905 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_VERSION_GET);
2906 while (i< 4)
2907 {
2908 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2909 {
2910 u32Data = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2911 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2912 return u32Data;
2913 }
2914 i++;
2915 _delay();
2916 }
2917 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2918 return u32Data;
2919 }
2920
HAL_TSP_Check_FW_VER(void)2921 MS_BOOL HAL_TSP_Check_FW_VER(void)
2922 {
2923 MS_U32 u32FWVer;
2924
2925 u32FWVer = HAL_TSP_Get_FW_VER();
2926 if((u32FWVer >> 16) != TSP_FW_DEVICE_ID)
2927 {
2928 printf("\nWarning: TSP FW not match!! FW version: 0x%08x\n\n", (unsigned int)u32FWVer);
2929 return FALSE;
2930 }
2931
2932 return TRUE;
2933 }
2934
HAL_TSP_SetFwDbgMem(MS_PHY phyAddr,MS_U32 u32Size)2935 MS_BOOL HAL_TSP_SetFwDbgMem(MS_PHY phyAddr, MS_U32 u32Size)
2936 {
2937 MS_U32 i = 0;
2938
2939 if(IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_SIZE) ||
2940 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE) ||
2941 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZE) ||
2942 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_QMEM_ADDR, OPENRISC_QMEM_ADDR + OPENRISC_QMEM_SIZE))
2943 {
2944 printf("[%s][%d] invalid physical address 0x%x\n", __FUNCTION__, __LINE__, (unsigned int)phyAddr);
2945 return FALSE;
2946 }
2947 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, phyAddr);
2948 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, u32Size);
2949 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DBG_MEM);
2950 while(i<4)
2951 {
2952 if(0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2953 {
2954 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2955 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2956 return TRUE;
2957 }
2958 i++;
2959 _delay();
2960 }
2961 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2962 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2963 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2964
2965 return FALSE;
2966 }
2967
HAL_TSP_SetFwDbgWord(MS_U32 u32Word)2968 MS_BOOL HAL_TSP_SetFwDbgWord(MS_U32 u32Word)
2969 {
2970 MS_U32 i = 0;
2971
2972 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Word);
2973 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DBG_WORD);
2974 while(i<4)
2975 {
2976 if(0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2977 {
2978 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2979 return TRUE;
2980 }
2981 i++;
2982 _delay();
2983 }
2984 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2985 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2986 return FALSE;
2987 }
2988
2989 //0: VQ0, 1: VQ_file
HAL_TSP_SetVQBuffer(MS_PHY phyBaseAddr,MS_U32 u32BufLen)2990 void HAL_TSP_SetVQBuffer(MS_PHY phyBaseAddr, MS_U32 u32BufLen)
2991 {
2992 MS_PHY phyAddr = phyBaseAddr;
2993 MS_U32 u32Size = 0, u32OneBufSize = 0, u32temp = 0;
2994 MS_PHY phyVqBufOffset = _HAL_TSP_MIU_OFFSET(phyBaseAddr);
2995
2996 u32OneBufSize = ((u32BufLen >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment
2997 u32Size = u32OneBufSize / TSP_VQ_PITCH;
2998
2999 _HAL_REG32_W(&(_TspCtrl[0].VQ0_BASE), (MS_U32)((phyAddr-phyVqBufOffset) >> MIU_BUS));
3000 u32temp = (u32Size << TSP_VQ0_SIZE_192PK_SHIFT) | (_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL) & ~TSP_VQ0_SIZE_192PK_MASK);
3001 _HAL_REG32_W(&(_TspCtrl[0].VQ0_CTRL), u32temp);
3002
3003 phyAddr += u32OneBufSize;
3004 _HAL_REG32_W(&(_TspCtrl[0].VQ1_Base), (MS_U32)((phyAddr-phyVqBufOffset) >> MIU_BUS));
3005 u32temp = (u32Size << TSP_VQ1_SIZE_192BYTE_SHIFT) | (_HAL_REG32_R(&_TspCtrl[0].VQ1_Size) & ~TSP_VQ1_SIZE_192BYTE_MASK);
3006 _HAL_REG32_W(&(_TspCtrl[0].VQ1_Size), u32temp);
3007 }
3008
HAL_TSP_VQueue_Enable(MS_BOOL bEnable)3009 void HAL_TSP_VQueue_Enable(MS_BOOL bEnable)
3010 {
3011 if (bEnable)
3012 {
3013 // Reset VQ before VQ enable.
3014 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3015 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3016
3017 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3018 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3019
3020 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3021 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS), (TSP_VQ0_EN|TSP_VQ_FILE_EN|TSP_VQ_PINGPONG_EN)));
3022 }
3023 else
3024 {
3025 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3026 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS), (TSP_VQ0_EN|TSP_VQ_FILE_EN|TSP_VQ_PINGPONG_EN)));
3027 }
3028
3029 }
3030
HAL_TSP_VQueue_Reset(void)3031 void HAL_TSP_VQueue_Reset(void)
3032 {
3033 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3034 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3035 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3036 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3037
3038 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3039 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3040 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3041 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3042 }
3043
HAL_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable)3044 void HAL_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable)
3045 {
3046 if (bEnable)
3047 {
3048 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3049 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_OVERFLOW_INT_EN));
3050 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3051 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_OVF_INT_EN));
3052
3053 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3054 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L)|0xFF00 , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8));
3055 }
3056 else
3057 {
3058 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3059 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_OVERFLOW_INT_EN));
3060 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3061 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_OVF_INT_EN));
3062
3063 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3064 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8));
3065 }
3066 }
3067
HAL_TSP_VQueue_Clr_OverflowInt(void)3068 void HAL_TSP_VQueue_Clr_OverflowInt(void)
3069 {
3070 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL);
3071
3072 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, u32data | TSP_VQ0_CLR_OVERFLOW_INT);
3073 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, u32data & ~TSP_VQ0_CLR_OVERFLOW_INT);
3074
3075 u32data = _HAL_REG32_R(&_TspCtrl[0].VQ1_Config);
3076 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, u32data | TSP_VQ1_CLR_OVF_INT);
3077 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, u32data & ~TSP_VQ1_CLR_OVF_INT);
3078
3079 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3080 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L), TSP_HWINT2_VQ_OVERFLOW_STATUS));
3081 }
3082
HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len)3083 void HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len)
3084 {
3085 MS_U32 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN1;
3086
3087 switch(u8req_len)
3088 {
3089 case 1:
3090 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN1;
3091 break;
3092 case 2:
3093 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN2;
3094 break;
3095 case 4:
3096 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN4;
3097 break;
3098 case 8:
3099 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN8;
3100 break;
3101 default:
3102 break;
3103 }
3104
3105 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3106 (_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value);
3107
3108
3109 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3110 (_HAL_REG32_R(&_TspCtrl[0].VQ1_Config) & ~TSP_VQ1_WR_THRESHOLD_MASK) | u32Value);
3111 }
3112
HAL_TSP_VQ_INT_STATUS(void)3113 MS_U32 HAL_TSP_VQ_INT_STATUS(void)
3114 {
3115 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_VQ_OVERFLOW_STATUS);
3116 }
3117
HAL_TSP_Get_VQStatus(void)3118 MS_U32 HAL_TSP_Get_VQStatus(void)
3119 {
3120 return (_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS) & TSP_VQ0_STATUS_MASK);
3121 }
3122
HAL_TSP_GetPidFltReg(MS_U32 u32EngId,MS_U32 u32PidFltId)3123 REG_PidFlt* HAL_TSP_GetPidFltReg(MS_U32 u32EngId, MS_U32 u32PidFltId)
3124 {
3125 return (&(_TspPid[u32EngId].Flt[u32PidFltId]));
3126 }
3127
HAL_TSP_Read_DropPktCnt(MS_U16 * pu16ADropCnt,MS_U16 * pu16VDropCnt)3128 MS_BOOL HAL_TSP_Read_DropPktCnt(MS_U16* pu16ADropCnt, MS_U16* pu16VDropCnt)
3129 {
3130 return FALSE;
3131 }
3132
HAL_TSP_TSIF0_Enable(MS_BOOL bEnable)3133 void HAL_TSP_TSIF0_Enable(MS_BOOL bEnable)
3134 {
3135 if (bEnable)
3136 {
3137 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3138 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
3139 }
3140 else
3141 {
3142 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3143 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
3144 }
3145 }
3146
HAL_TSP_TSIF1_Enable(MS_BOOL bEnable)3147 void HAL_TSP_TSIF1_Enable(MS_BOOL bEnable)
3148 {
3149 if (bEnable)
3150 {
3151 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3152 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
3153 }
3154 else
3155 {
3156 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3157 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
3158 }
3159 }
3160
3161 // (Section DMA + PVR) , total 5 set
3162 // Default value of low bound is 0, default value of up bound is 0xFFFFFFFF, means no protection
3163 // If set both low bound and up bound to be 0, means protection all
3164 // MIU bus is 4, Max MIU address is 512MB, should append 1 zero
3165 // The range can be written: u32StartAddr <= x < u32EndAddr
3166 // Protection range: x >= u32EndAddr && x < u32StartAddr
HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable,MS_PHY * pphyStartAddr,MS_PHY * pphyEndAddr)3167 void HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY* pphyStartAddr, MS_PHY* pphyEndAddr)
3168 {
3169 MS_U32 u32value;
3170 MS_U32 u32lbnd, u32ubnd;
3171
3172 if (bEnable)
3173 {
3174 if(pphyStartAddr[0] == pphyEndAddr[0])
3175 pphyEndAddr[0] += (1UL << MIU_BUS);
3176
3177 u32lbnd = (MS_U32)(((pphyStartAddr[0]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[0])) >> MIU_BUS) >> TSP_DMAW_BND_ALI_SHIFT) & TSP_DMAW_LBND_LSB8;
3178 u32ubnd = (MS_U32)((((pphyEndAddr[0]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[0])) >> MIU_BUS) >> TSP_DMAW_BND_ALI_SHIFT) & TSP_DMAW_LBND_LSB8) << TSP_DMAW_UBND_LSB8_SHIFT;
3179 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16C4) & ~(TSP_DMAW_LBND_LSB8|TSP_DMAW_UBND_LSB8));
3180 _HAL_REG32_W(&_TspCtrl[0].reg16C4, u32value);
3181 u32lbnd = (MS_U32)(((pphyStartAddr[0]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[0])) >> MIU_BUS) >> TSP_DMAWP_BND_ALI_SHIFT) & TSP_DMAWP_LBND_MASK;
3182 u32ubnd = (MS_U32)((((pphyEndAddr[0]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[0])) >> MIU_BUS) >> TSP_DMAWP_BND_ALI_SHIFT) & TSP_DMAWP_HBND_MASK) << TSP_DMAWP_HBND_SHFT;
3183 u32value = u32lbnd + u32ubnd;
3184 _HAL_REG32_W(&_TspCtrl[0].TSP_DMAWP_BND, u32value);
3185
3186 if(pphyStartAddr[1] == pphyEndAddr[1])
3187 pphyStartAddr[1] += (1UL << MIU_BUS);
3188
3189 u32lbnd = (MS_U32)(((pphyStartAddr[1]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[1])) >> MIU_BUS) >> TSP_DMAW1_BND_ALI_SHIFT) & TSP_DMAW1_LBND_LSB8;
3190 u32ubnd = (MS_U32)((((pphyEndAddr[1]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[1])) >> MIU_BUS) >> TSP_DMAW1_BND_ALI_SHIFT) & TSP_DMAW1_LBND_LSB8) << TSP_DMAW1_UBND_LSB8_SHIFT;
3191 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16C8) & ~(TSP_DMAW1_LBND_LSB8|TSP_DMAW1_UBND_LSB8));
3192 _HAL_REG32_W(&_TspCtrl[0].reg16C8, u32value);
3193 u32lbnd = (MS_U32)(((pphyStartAddr[1]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[1])) >> MIU_BUS) >> TSP_DMAW1_ALI_SHIFT) & TSP_DMAW1_LBND_MASK1;
3194 u32ubnd = (MS_U32)((((pphyEndAddr[1]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[1])) >> MIU_BUS) >> TSP_DMAW1_ALI_SHIFT) & TSP_DMAW1_UBND_MASK1) << TSP_DMAW1_UBND_SHIFT1;
3195 u32value = u32lbnd + u32ubnd;
3196 _HAL_REG32_W(&_TspCtrl[0].DMAW1_1, u32value);
3197
3198 if(pphyStartAddr[2] == pphyEndAddr[2])
3199 pphyStartAddr[2] += (1UL << MIU_BUS);
3200
3201 u32lbnd = (MS_U32)(((pphyStartAddr[2]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[2])) >> MIU_BUS) >> TSP_DMAW2_BND_ALI_SHIFT) & TSP_DMAW2_LBND_LSB8;
3202 u32ubnd = (MS_U32)((((pphyEndAddr[2]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[2])) >> MIU_BUS) >> TSP_DMAW2_BND_ALI_SHIFT) & TSP_DMAW2_LBND_LSB8) << TSP_DMAW2_UBND_LSB8_SHIFT;
3203 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16CC) & ~(TSP_DMAW2_LBND_LSB8|TSP_DMAW2_UBND_LSB8));
3204 _HAL_REG32_W(&_TspCtrl[0].reg16CC, u32value);
3205 u32lbnd = (MS_U32)(((pphyStartAddr[2]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[2])) >> MIU_BUS) >> TSP_DMAW2_ALI_SHIFT) & TSP_DMAW2_LBND_MASK1;
3206 u32ubnd = (MS_U32)((((pphyEndAddr[2]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[2])) >> MIU_BUS) >> TSP_DMAW2_ALI_SHIFT) & TSP_DMAW2_UBND_MASK1) << TSP_DMAW2_UBND_SHIFT1;
3207 u32value = u32lbnd + u32ubnd;
3208 _HAL_REG32_W(&_TspCtrl[0].DMAW2_1, u32value);
3209
3210 if(pphyStartAddr[3] == pphyEndAddr[3])
3211 pphyStartAddr[3] += (1UL << MIU_BUS);
3212
3213 u32lbnd = (MS_U32)(((pphyStartAddr[3]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[3])) >> MIU_BUS) >> TSP_DMAW3_BND_ALI_SHIFT) & TSP_DMAW3_LBND_MASK;
3214 u32ubnd = (MS_U32)(((pphyEndAddr[3]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[3])) >> MIU_BUS) >> TSP_DMAW3_BND_ALI_SHIFT) & TSP_DMAW3_UBND_MASK;
3215 _HAL_REG32_W(&_TspCtrl[0].DMAW3_LBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW3_LBND) & ~TSP_DMAW3_LBND_MASK) | u32lbnd);
3216 _HAL_REG32_W(&_TspCtrl[0].DMAW3_UBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW3_UBND) & ~TSP_DMAW3_UBND_MASK) | u32ubnd);
3217
3218 if(pphyStartAddr[4] == pphyEndAddr[4])
3219 pphyStartAddr[4] += (1UL << MIU_BUS);
3220
3221 u32lbnd = (MS_U32)(((pphyStartAddr[4]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[4])) >> MIU_BUS) >> TSP_DMAW4_BND_ALI_SHIFT) & TSP_DMAW4_LBND_MASK;
3222 u32ubnd = (MS_U32)(((pphyEndAddr[4]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[4])) >> MIU_BUS) >> TSP_DMAW4_BND_ALI_SHIFT) & TSP_DMAW4_UBND_MASK;
3223 _HAL_REG32_W(&_TspCtrl[0].DMAW4_LBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW4_LBND) & ~TSP_DMAW4_LBND_MASK) | u32lbnd);
3224 _HAL_REG32_W(&_TspCtrl[0].DMAW4_UBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW4_UBND) & ~TSP_DMAW4_UBND_MASK) | u32ubnd);
3225
3226 _HAL_REG32_W(&_TspCtrl[0].reg15b4, _HAL_REG32_R(&_TspCtrl[0].reg15b4) | TSP_DMAW_PROTECT_EN);
3227 }
3228 else
3229 {
3230 _HAL_REG32_W(&_TspCtrl[0].reg15b4, _HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_DMAW_PROTECT_EN);
3231 }
3232 }
3233
HAL_TSP_MOBF_Set_PVRKey(MS_U32 u32Key0,MS_U32 u32Key1)3234 MS_BOOL HAL_TSP_MOBF_Set_PVRKey(MS_U32 u32Key0, MS_U32 u32Key1)
3235 {
3236 _HAL_REG32_W(&_TspCtrl[0].MOBF_PVR_KEY, (_HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_MOBF_PVR_KEY0_MASK) | ((u32Key0 << TSP_MOBF_PVR_KEY0_SHIFT) & TSP_MOBF_PVR_KEY0_MASK));
3237 _HAL_REG32_W(&_TspCtrl[0].MOBF_PVR_KEY, (_HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_MOBF_PVR_KEY1_MASK) | ((u32Key0 << TSP_MOBF_PVR_KEY1_SHIFT) & TSP_MOBF_PVR_KEY1_MASK));
3238 return TRUE;
3239 }
3240
HAL_TSP_MOBF_Set_FileinKey(MS_U32 u32Key)3241 MS_BOOL HAL_TSP_MOBF_Set_FileinKey(MS_U32 u32Key)
3242 {
3243 MS_U32 u32Data = 0;
3244
3245 u32Data = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_MOBF_FILE_KEY0_L_MASK) |
3246 ((u32Key << TSP_MOBF_FILE_KEY0_L_SHIFT) & TSP_MOBF_FILE_KEY0_L_MASK);
3247 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32Data);
3248 return TRUE;
3249 }
3250
HAL_TSP_MOBF_Filein_Enable(MS_BOOL bEnable)3251 MS_BOOL HAL_TSP_MOBF_Filein_Enable(MS_BOOL bEnable)
3252 {
3253 return FALSE;
3254 }
3255
HAL_TSP_MOBF_PVR_Enable(MS_BOOL bEnable)3256 MS_BOOL HAL_TSP_MOBF_PVR_Enable(MS_BOOL bEnable)
3257 {
3258 return FALSE;
3259 }
3260
HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable)3261 MS_BOOL HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable)
3262 {
3263 if (bEnable)
3264 {
3265 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3266 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_BD_AUDIO_EN));
3267 }
3268 else
3269 {
3270 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3271 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_BD_AUDIO_EN));
3272 }
3273
3274 return TRUE;
3275 }
3276
HAL_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,MS_U32 * pData)3277 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData)
3278 {
3279 switch (u32Cmd)
3280 {
3281 default:
3282 return FALSE;
3283 }
3284
3285 return TRUE;
3286 }
3287
HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId)3288 MS_U8 HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId)
3289 {
3290 MS_U32 u32Value = TSP_MCU_CMD_SCMSTS_GET | (MS_U32)(u8FltId & 0xFF);
3291
3292 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32Value);
3293 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3294 return (MS_U8)(_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3295 }
3296
HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId)3297 MS_U8 HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId)
3298 {
3299 MS_U32 u32Value = TSP_MCU_CMD_SCMSTS_GET | (MS_U32)(u8FltId & 0xFF);
3300
3301 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32Value);
3302 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3303 return (MS_U8)(_HAL_REG32_R(&_TspCtrl[0].MCU_Data0) >> 8);
3304 }
3305
3306 //-------------------------------------------------------------------------------
3307 // @u16Mode : TSP_DEBUG_MODE_DIS_CONT => discontinuous packet count
3308 // TSP_DEBUG_MODE_DROP_COUNT => drop packet count
3309 // @u16Src : TBD
3310 // @u16Fifo : TBD
3311 //-------------------------------------------------------------------------------
_HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE u16Mode,TSP_DEBUG_SRC TspSrc,TSP_DEBUG_FIFO TspFifo)3312 static MS_U32 _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE u16Mode, TSP_DEBUG_SRC TspSrc, TSP_DEBUG_FIFO TspFifo)
3313 {
3314 REG16* pReg = NULL;
3315 MS_U16 u16Mask = 0;
3316 MS_U16 u16Shft = 0;
3317 MS_U16 u16Cfg = 0;
3318
3319 switch (TspSrc)
3320 {
3321 case TSP_DEBUG_SRC_TS0: // TS0
3322 pReg = &(_TspCtrl2[0].PktCnt_TS0);
3323 break;
3324 case TSP_DEBUG_SRC_TS1: // TS1
3325 pReg = &(_TspCtrl2[0].PktCnt_TS1);
3326 break;
3327 case TSP_DEBUG_SRC_FILE: // FILE
3328 pReg = &(_TspCtrl2[0].PktCnt_File);
3329 break;
3330 default:
3331 return 0;
3332 }
3333
3334 switch (TspFifo)
3335 {
3336 case TSP_DEBUG_FIFO_VIDEO: // VIDEO
3337 u16Mask = DISCONTI_CNT_VIDEO_MASK;
3338 u16Shft = DISCONTI_CNT_VIDEO_SHFT;
3339 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2; // discontinuous packet count : drop packet count
3340 break;
3341 case TSP_DEBUG_FIFO_AUDIO: // AUDIO
3342 u16Mask = DISCONTI_CNT_AUDIO_MASK;
3343 u16Shft = DISCONTI_CNT_AUDIO_SHFT;
3344 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2;
3345 break;
3346 case TSP_DEBUG_FIFO_VIDEO3D: // VIDEO3D
3347 u16Mask = DISCONTI_CNT_V3D_MASK;
3348 u16Shft = DISCONTI_CNT_V3D_SHFT;
3349 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2;
3350 break;
3351 default:
3352 return 0;
3353 }
3354
3355 _HAL_REG16_W(&(_TspCtrl2[0].HwCfg1),
3356 (_HAL_REG16_R(&(_TspCtrl2[0].HwCfg1)) & ~HW_INFO_SRC_MODE_MASK) | u16Cfg);
3357
3358 return (MS_U32)(_HAL_REG16_R(pReg) & u16Mask) >> u16Shft;
3359 }
3360
3361 //-------------------------------------------------------------------------------
3362 // @ u16Src : TBD
3363 // @ u16Fifo : TBD
3364 // @ return value : 0 ~ 15
3365 //-------------------------------------------------------------------------------
HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info * TspDisconPktCntInfo)3366 MS_U32 HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info* TspDisconPktCntInfo)
3367 {
3368 if(TspDisconPktCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3369 {
3370 // Set the clear source
3371 if(TspDisconPktCntInfo->TspSrc == TSP_DEBUG_SRC_TS0)
3372 {
3373 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3374 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_0<<TSP_CLR_SRC_SHIFT));
3375 }
3376 else if(TspDisconPktCntInfo->TspSrc == TSP_DEBUG_SRC_FILE)
3377 {
3378 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3379 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_FILE<<TSP_CLR_SRC_SHIFT));
3380 }
3381
3382 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3383 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) | (TSP_DISCONTI_VD_CLR | TSP_DISCONTI_V3D_CLR | TSP_DISCONTI_AUD_CLR));
3384 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3385 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~(TSP_DISCONTI_VD_CLR | TSP_DISCONTI_V3D_CLR | TSP_DISCONTI_AUD_CLR));
3386 }
3387 return _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE_DIS_CONT, TspDisconPktCntInfo->TspSrc, TspDisconPktCntInfo->TspFifo);
3388 }
3389
3390 //-------------------------------------------------------------------------------
3391 // @ u16Src : TBD
3392 // @ u16Fifo : TBD
3393 // @ return value : 0 ~ 15
3394 //-------------------------------------------------------------------------------
HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info * TspDropCntInfo)3395 MS_U32 HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info* TspDropCntInfo)
3396 {
3397 if(TspDropCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3398 {
3399 // Set the clear source
3400 if(TspDropCntInfo->TspSrc == TSP_DEBUG_SRC_TS0)
3401 {
3402 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3403 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_0<<TSP_CLR_SRC_SHIFT));
3404 }
3405 else if(TspDropCntInfo->TspSrc == TSP_DEBUG_SRC_FILE)
3406 {
3407 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3408 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_FILE<<TSP_CLR_SRC_SHIFT));
3409 }
3410
3411 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3412 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) | (TSP_DUP_PKT_CNT_CLR));
3413 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3414 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~(TSP_DUP_PKT_CNT_CLR));
3415 }
3416 return _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE_DROP_CONT, TspDropCntInfo->TspSrc, TspDropCntInfo->TspFifo);
3417 }
3418
3419 //-------------------------------------------------------------------------------
3420 // @u16Tsif : TBD
3421 // @ return value : 0 ~ 15
3422 //-------------------------------------------------------------------------------
HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info * TspLockCntInfo)3423 MS_U32 HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info* TspLockCntInfo)
3424 {
3425 if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3426 {
3427 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3428 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_CLR_LOCKED_PKT_CNT));
3429 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3430 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_CLR_LOCKED_PKT_CNT));
3431 }
3432 else if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_ENABLE)
3433 {
3434 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3435 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_DIS_LOCKED_PKT_CNT));
3436 }
3437 else if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_DISABLE)
3438 {
3439 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3440 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_DIS_LOCKED_PKT_CNT));
3441 }
3442
3443 switch (TspLockCntInfo->TspTsif)
3444 {
3445 case TSP_DEBUG_TSIF0: // TS0
3446 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].LockPktCnt)) & TS0_LOCK_CNT_MASK) >> TS0_LOCK_CNT_SHFT;
3447 case TSP_DEBUG_TSIF1: // TS1
3448 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].LockPktCnt)) & TS1_LOCK_CNT_MASK) >> TS1_LOCK_CNT_SHFT;
3449 default:
3450 return 0;
3451 }
3452 }
3453
3454 //-------------------------------------------------------------------------------
3455 // @ u16Fifo : TBD
3456 // @ return value : 0 ~ 15
3457 //-------------------------------------------------------------------------------
HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info * TspAVCntInfo)3458 MS_U32 HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info* TspAVCntInfo)
3459 {
3460 if(TspAVCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3461 {
3462 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3463 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_CLR_AV_PKT_CNT));
3464 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3465 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_CLR_AV_PKT_CNT));
3466 }
3467
3468 switch (TspAVCntInfo->TspFifo)
3469 {
3470 case TSP_DEBUG_FIFO_VIDEO: // VIDEO
3471 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].AVPktCnt)) & VIDEO_PKT_CNT_MASK) >> VIDEO_PKT_CNT_SHFT;
3472 case TSP_DEBUG_FIFO_AUDIO: // AUDIO
3473 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].AVPktCnt)) & AUDIO_PKT_CNT_MASK) >> AUDIO_PKT_CNT_SHFT;
3474 default:
3475 return 0;
3476 }
3477 }
3478
3479
HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc)3480 MS_U32 HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc)
3481 {
3482 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_TEI_COUNT_GET | u32PktSrc);
3483 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3484 return (_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3485 }
3486
HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc)3487 MS_BOOL HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc)
3488 {
3489 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_TEI_COUNT_GET | TSP_MCU_CMD_TEI_COUNT_OPTION_RESET | u32PktSrc);
3490 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3491 return TRUE;
3492 }
3493
HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId)3494 MS_U32 HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId)
3495 {
3496 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DISCONT_COUNT_GET | u32FltId);
3497 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3498 return (_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3499 }
3500
HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId)3501 MS_BOOL HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId)
3502 {
3503 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DISCONT_COUNT_GET | TSP_MCU_CMD_DISCONT_COUNT_OPTION_RESET | u32FltId);
3504 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3505 return TRUE;
3506 }
3507
HAL_TSP_SetPacketMode(MS_U32 u32TSIf,MS_U32 u32PktMode)3508 MS_BOOL HAL_TSP_SetPacketMode(MS_U32 u32TSIf, MS_U32 u32PktMode)
3509 {
3510 return FALSE;
3511 }
3512
HAL_TSP_SetMergeStrSyncByte(MS_U32 u32SrcID,MS_U8 u8SyncByte)3513 MS_BOOL HAL_TSP_SetMergeStrSyncByte(MS_U32 u32SrcID, MS_U8 u8SyncByte)
3514 {
3515 return FALSE;
3516 }
3517
HAL_TSP_MOBF_Set_PVRKey_EX(MS_U32 u32PvrEng,MS_U32 u32Key0,MS_U32 u32Key1)3518 void HAL_TSP_MOBF_Set_PVRKey_EX(MS_U32 u32PvrEng, MS_U32 u32Key0, MS_U32 u32Key1)
3519 {
3520 return;
3521 }
3522
3523