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Searched refs:REG_CTRL_BASE_TSO1 (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tso/
H A DregTSO.h196 #define REG_CTRL_BASE_TSO1 (0x47A00) // 0x123D macro
H A DhalTSO.c296 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1); in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tso/
H A DregTSO.h205 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D macro
H A DhalTSO.c352 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1); in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tso/
H A DregTSO.h205 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D macro
H A DhalTSO.c145 #define TSO1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO1 + ((…
360 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1); in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tso/
H A DregTSO.h195 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D macro
H A DhalTSO.c151 #define TSO1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO1 + ((…
312 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1); in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tso/
H A DregTSO.h205 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D macro
H A DhalTSO.c153 #define TSO1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO1 + ((…
368 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1); in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tso/
H A DregTSO.h205 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D macro
H A DhalTSO.c153 #define TSO1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO1 + ((…
368 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1); in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tso/
H A DregTSO.h202 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D macro
H A DhalTSO.c153 #define TSO1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO1 + ((…
359 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1); in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tso/
H A DregTSO.h202 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D macro
H A DhalTSO.c153 #define TSO1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO1 + ((…
359 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1); in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DregTSO.h173 #define REG_CTRL_BASE_TSO1 (0xC2400UL) // 0x1612 macro
H A DhalTSO.c227 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612 in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DregTSO.h173 #define REG_CTRL_BASE_TSO1 (0xC2400UL) // 0x1612 macro
H A DhalTSO.c227 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612 in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DregTSO.h173 #define REG_CTRL_BASE_TSO1 (0xC2400UL) // 0x1612 macro
H A DhalTSO.c227 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612 in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DregTSO.h173 #define REG_CTRL_BASE_TSO1 (0xC2400UL) // 0x1612 macro
H A DhalTSO.c227 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612 in HAL_TSO_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DregTSO.h173 #define REG_CTRL_BASE_TSO1 (0xC2400UL) // 0x1612 macro

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