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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSO.h 98 // Description: TS I/O Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSO_REG_H_ 103 #define _TSO_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TSO_ENGINE_NUM (1UL) 137 #define TSO_PIDFLT_NUM (128UL) 138 #define TSO_REP_PIDFLT_NUM (16UL) 139 #define TSO_TSIF_NUM (2UL) 140 #define TSO_FILE_IF_NUM (1UL) 141 #define TSO_SVQ_UNIT_SIZE (208UL) 142 143 #define TSO_PIDFLT_NUM_ALL TSO_PIDFLT_NUM 144 145 #define TSO_PID_NULL 0x1FFFUL 146 147 #define TSO_MIU_BUS 4UL 148 //------------------------------------------------------------------------------------------------- 149 // Harware Capability 150 //------------------------------------------------------------------------------------------------- 151 152 #define TSO_IN_MUX_TS0 0x0UL 153 #define TSO_IN_MUX_TS1 0x1UL 154 #define TSO_IN_MUX_TS2 0x2UL 155 #define TSO_IN_MUX_TSDEMOD 0x7UL 156 #define TSO_IN_MUX_MEM 0x8UL 157 158 #define TSO_CLKIN_TS0 0x00UL 159 #define TSO_CLKIN_TS1 0x04UL 160 #define TSO_CLKIN_TS2 0x08UL 161 #define TSO_CLKIN_DMD 0x1CUL 162 163 //--------------- u16ClkOutDivSrcSel ------------- 164 #define TSO_OUT_DIV_DMPLLDIV5 0x0000UL // dmplldiv5 = 844/5 = 172.8MHz 165 #define TSO_OUT_DIV_DMPLLDIV3 0x0001UL // dmplldiv3 = 844/3 = 288MHz 166 167 // Note: 168 // DVB-T dmplldiv5 / 2 (11+1) = 7.2 MHz 169 // DVB-C dmplldiv5 / 2 (11+1) = 7.2 MHz 170 // ATSC dmplldiv5 / 2 (11+1) = 7.2 MHz 171 // ISDB-T dmplldiv_3 / 2 (17+1) = 8 MHz 172 173 //---------------- u16ClkOutSel --------------- 174 #define TSO_OUT_DIV2 0x0000UL // Must also select div src and set div num 175 #define TSO_OUT_62MHz 0x0400UL 176 #define TSO_OUT_54MHz 0x0800UL 177 #define TSO_OUT_PTSO_OUT 0x0C00UL //live-in 178 #define TSO_OUT_PTSO_OUT_DIV8 0x1000UL //live-in 179 #define TSO_OUT_27MHz 0x1400UL 180 #define TSO_OUT_DEMOD_P 0x1C00UL //live-in 181 182 //--------------- u16PreTsoOutSel ------------- 183 #define TSO_PRE_OUT_TS0IN 0x0000UL 184 #define TSO_PRE_OUT_TS1IN 0x0001UL 185 #define TSO_PRE_OUT_TS2IN 0x0002UL 186 #define TSO_PRE_OUT_DEMDOIN 0x0003UL 187 188 //------------------------------------------------------------------------------------------------- 189 // Type and Structure 190 //------------------------------------------------------------------------------------------------- 191 192 #define REG_PIDFLT_BASE (0x00210000UL << 1UL) // Fit the size of REG32 193 194 #define REG_CTRL_BASE_TSO (0x27400UL) // 0x113A 195 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D 196 #define REG_CTRL_BASE_TSO2 (0xA7200UL) // 0x1539 197 198 199 typedef struct _REG32 200 { 201 volatile MS_U16 L; 202 volatile MS_U16 empty_L; 203 volatile MS_U16 H; 204 volatile MS_U16 empty_H; 205 } REG32; 206 207 typedef struct _REG16 208 { 209 volatile MS_U16 data; 210 volatile MS_U16 _resv; 211 } REG16; 212 213 typedef REG32 REG_PidFlt; 214 215 // PID 216 #define TSO_PIDFLT_PID_MASK 0x00001FFFUL 217 #define TSO_PIDFLT_PID_SHFT 0UL 218 219 // Channel source 220 #define TSO_PIDFLT_IN_SHIFT 13UL 221 #define TSO_PIDFLT_IN_MASK 0x0000E000UL 222 #define TSO_PIDFLT_IN_CH0 0x00002000UL 223 #define TSO_PIDFLT_IN_CH5 0x0000A000UL 224 #define TSO_PIDFLT_IN_CH6 0x0000C000UL 225 226 typedef struct _REG_Pid 227 { // Index(word) CPU(byte) Default 228 REG_PidFlt Flt[TSO_PIDFLT_NUM]; 229 } REG_Pid; 230 231 232 typedef struct _REG_Ctrl_TSO 233 { 234 //---------------------------------------------- 235 // 0xBF802A00 MIPS direct access 236 //---------------------------------------------- 237 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 238 239 REG16 SW_RSTZ; // 0xbf827400 0x00 240 #define TSO_SW_RSTZ_DISABLE 0x0001UL 241 #define TSO_SW_RSTZ_CLK_STAMP 0x0002UL 242 #define TSO_SW_RSTZ_CMDQ1 0x0100UL 243 #define TSO_SW_RSTZ_WB1 0x0200UL 244 #define TSO_SW_RSTZ_WB_DMA1 0x0400UL 245 #define TSO_SW_RSTZ_TS_FIN1 0x0800UL 246 #define TSO_SW_RSTZ_CMDQ 0x1000UL 247 #define TSO_SW_RSTZ_WB 0x2000UL 248 #define TSO_SW_RSTZ_WB_DMA 0x4000UL 249 #define TSO_SW_RSTZ_TS_FIN 0x8000UL 250 #define TSO_SW_RSTZ_ALL 0x00FEUL 251 252 REG16 SW_RSTZ1; // 0xbf827404 0x01 253 #define TSO_SW_RSTZ1_CH_IF1 0x0001UL 254 #define TSO_SW_RSTZ1_CH_IF5 0x0010UL 255 #define TSO_SW_RSTZ1_CH_IF6 0x0020UL 256 #define TSO_SW_RSTZ1_ALL 0x0031UL 257 258 REG32 _xbf827408_740c; // 0xbf827408~0xbf82740c 0x02~03 259 260 REG16 TSO_CH0_IF1_CFG0; // 0xbf827410 0x04 261 #define TSO_PKT_SIZE_CHK_LIVE_MASK 0x00FFUL 262 #define TSO_PIDFLT_PKT_SIZE_MASK 0xFF00UL 263 #define TSO_PIDFLT_PKT_SIZE_SHIFT 8UL 264 265 REG16 TSO_CH0_IF1_CFG1; // 0xbf827414 0x05 //sunc byte 266 REG16 TSO_CH0_IF1_CFG2; // 0xbf827418 0x06 267 #define TSO_CHCFG_P_SEL 0x0001UL 268 #define TSO_CHCFG_EXT_SYNC_SEL 0x0002UL 269 #define TSO_CHCFG_TS_SIN_C0 0x0004UL 270 #define TSO_CHCFG_TS_SIN_C1 0x0008UL 271 #define TSO_CHCFG_PIDFLT_REC_ALL 0x0010UL // bypass all packets 272 #define TSO_CHCFG_PIDFLT_REC_NULL 0x0020UL // bypass NULL packets 273 #define TSO_CHCFG_PIDFLT_OVF_INT_EN 0x0040UL 274 #define TSO_CHCFG_PIDFLT_OVF_CLR 0x0080UL 275 #define TSO_CHCFG_FORCE_SYNC_BYTE 0x0100UL 276 #define TSO_CHCFG_SKIP_TEI_PKT 0x0200UL 277 #define TSO_CHCFG_DIS_LOCKED_PKT_CNT 0x0400UL 278 #define TSO_CHCFG_CLR_LOCKED_PKT_CNT 0x0800UL 279 #define TSO_CHCFG_TRC_CLK_LD_DIS 0x1000UL 280 #define TSO_CHCFG_TRC_CLK_CLR 0x2000UL 281 REG16 TSO_CH0_IF1_CFG3; // 0xbf82741c 0x07 282 283 REG16 _xbf827470_747c[12]; // 0xbf827420~0xbf82744c 0x08~13 284 285 REG16 TSO_CH0_IF5_CFG0; // 0xbf827450 0x14 286 REG16 TSO_CH0_IF5_CFG1; // 0xbf827454 0x15 287 REG16 TSO_CH0_IF5_CFG2; // 0xbf827458 0x16 288 REG16 TSO_CH0_IF5_CFG3; // 0xbf82745c 0x17 289 290 REG16 TSO_CH0_IF6_CFG0; // 0xbf827460 0x18 291 REG16 TSO_CH0_IF6_CFG1; // 0xbf827464 0x19 292 REG16 TSO_CH0_IF6_CFG2; // 0xbf827468 0x1a 293 REG16 TSO_CH0_IF6_CFG3; // 0xbf82746c 0x1b 294 295 REG16 TSO_CFG0; // 0xbf827470 0x1c 296 #define TSO_CFG0_S2P0_SHIFT 0UL 297 #define TSO_CFG0_S2P1_SHIFT 1UL 298 #define TSO_CFG0_S2P_CFG_MASK 0x001FUL 299 #define TSO_CFG0_S2P_EN 0x0001UL 300 #define TSO_CFG0_S2P_TS_SIN_C0 0x0002UL 301 #define TSO_CFG0_S2P_TS_SIN_C1 0x0004UL 302 #define TSO_CFG0_S2P_TS_3WIRE_MOD 0x0008UL 303 #define TSO_CFG0_S2P_BYPASS 0x0010UL 304 305 REG16 TSO_CFG1; // 0xbf827474 0x1d 306 #define TSO_CFG1_TSO_OUT_EN 0x0001UL 307 #define TSO_CFG1_TSO_TSIF1_EN 0x0002UL 308 #define TSO_CFG1_TSO_TSIF5_EN 0x0020UL 309 #define TSO_CFG1_TSO_TSIF6_EN 0x0040UL 310 #define TSO_CFG1_CLK_TRC_SEL_MASK 0x0E00UL 311 #define TSO_CFG1_PKT_LOCK_CLR 0x2000UL 312 #define TSO_CFG1_NULL_EN 0x4000UL 313 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL 314 315 REG16 TSO_CFG2; // 0xbf827478 0x1e 316 #define TSO_CFG2_VALID_BYTECNT_MASK 0x00FFUL 317 #define TSO_CFG2_INVALID_BYTECNT_MASK 0xFF00UL 318 #define TSO_CFG2_VALID_BYTECNT_SHIFT 0UL 319 #define TSO_CFG2_INVALID_BYTECNT_SHIFT 8UL 320 321 REG16 TSO_CFG3; // 0xbf82747c 0x1f //opif_pkt_size 322 323 REG32 REP_PidFlt[16]; // 0xbf827480~0xbf8274F8 0x20~0x3e 324 #define REP_PIDFLT_ORG_PID_MASK 0x00001FFFUL 325 #define REP_PIDFLT_SRC_MASK 0x0000E000UL 326 #define REP_PIDFLT_SRC_SHIFT 13UL 327 #define REP_PIDFLT_SRC_CH1 0x00002000UL 328 #define REP_PIDFLT_SRC_CH5 0x0000A000UL 329 #define REP_PIDFLT_SRC_CH6 0x0000C000UL 330 #define REP_PIDFLT_NEW_PID_MASK 0x01FFF000UL 331 #define REP_PIDFLT_NEW_PID_SHIFT 16UL 332 #define REP_PIDFLT_REPLACE_EN 0x80000000UL 333 334 REG16 TSO_CLR_BYTE_CNT; // 0xbf827500 0x40 335 #define TSO_CLR_BYTE_CNT_1 0x0000UL 336 #define TSO_CLR_BYTE_CNT_5 0x0004UL 337 #define TSO_CLR_BYTE_CNT_6 0x0005UL 338 339 REG32 TSO_SYSTIMESTAMP; // 0xbf827504~0xbf827508 0x41~42 340 341 REG16 TSO_CFG4; // 0xbf82750c 0x43 342 #define TSO_CFG4_LOCK_RET_SYS_TIMESTAMP 0x0001UL 343 #define TSO_CFG4_ENABLE_SYS_TIMESTAMP 0x0002UL 344 #define TSO_CFG4_SET_SYS_TIMESTAMP 0x0004UL 345 #define TSO_CFG4_SET_TIMESTAMP_BASE_MASK 0x0008UL 346 #define TSO_CFG4_SET_TIMESTAMP_90K 0x0000UL 347 #define TSO_CFG4_SET_TIMESTAMP_27M 0x0008UL 348 #define TSO_CFG4_PIDTABLE_SRAM_SD_EN 0x0010UL 349 #define TSO_TIMESTAMP_RING_BACK 0x0020UL 350 #define TSO_LPCR_RING_BACK 0x0040UL 351 #define TSO_INIT_STAMP_RSTART 0x0100UL 352 #define TSO_CFG4_NULL_PKT_ID_MASK 0xF000UL 353 354 REG16 TSO_CFG5; // 0xbf82750c 0x44 355 #define TSO_CFG5_WIRE_MODE_EN_1 0x0001UL 356 #define TSO_CFG5_WIRE_MODE_EN_5 0x0010UL 357 #define TSO_CFG5_WIRE_MODE_EN_6 0x0020UL 358 #define TSO_CFG5_DIS_MIU_RQ 0x0400UL 359 360 REG32 TSO_INDR_ADDR; // 0xbf82750c~0xbf827510 0x45~0x46 361 REG32 TSO_INDR_WDATA; // 0xbf827514~0xbf827518 0x47~0x48 362 REG16 TSO_INDR_RDATA; // 0xbf82751c 0x49 363 REG16 TSO_INDR_CTRL ; // 0xbf827520 0x4a 364 #define TSO_INDIR_W_ENABLE 0x0001UL 365 #define TSO_INDIR_R_ENABLE 0x0002UL 366 367 REG16 TSO_STATUS; // 0xbf827524 0x4b 368 369 REG16 TSO_FI_TIMER[2]; // 0xbf827528~0xbf82752c 0x4c~0x4d 370 371 REG16 TSO_STATUS1; // 0xbf827530 0x4e 372 #define TSO_PIDFLT_OVF_EVER_TSIF0 0x0001UL 373 #define TSO_PIDFLT_OVF_EVER_TSIF5 0x0010UL 374 #define TSO_PIDFLT_OVF_EVER_TSIF6 0x0020UL 375 376 REG16 _xbf827534_7568[12]; // 0xbf827534~0xbf827568 0x4f~0x5a 377 378 REG16 TSO_TRACE_HIGH; // 0xbf82756c 0x5b 379 REG16 TSO_TRACE_LOW; // 0xbf827570 0x5c 380 REG16 TSO_TRACE_1t; // 0xbf827574 0x5d 381 382 REG16 TSO_BLOCK_SIZE_DB; // 0xbf827578 0x5e 383 REG16 TSO_BLOCK_OPT_DB; // 0xbf82757c 0x5f 384 385 REG32 TSO_Filein_raddr; // 0xbf827580~0xbf827584 0x60-0x61 386 REG32 TSO_Filein_rNum; // 0xbf827588~0xbf82758c 0x62-0x63 387 REG16 TSO_Filein_Ctrl; // 0xbf827590 0x64 388 #define TSO_FILEIN_CTRL_MASK 0x0003UL 389 #define TSO_FILEIN_RSTART 0x0001UL 390 #define TSO_FILEIN_ABORT 0x0002UL 391 #define TSO_FILEIN_MOBF_IDX_MASK 0x1F00UL 392 #define TSO_FILEIN_MOBF_IDX_SHIFT 8UL 393 #define TSO_FILEIN_RIU_TSO_NS 0x2000UL 394 395 REG32 TSO_Filein_raddr1; // 0xbf827594~0xbf827598 0x65-0x66 396 REG32 TSO_Filein_rNum1; // 0xbf82759c~0xbf8275a0 0x67-0x68 397 REG16 TSO_Filein_Ctrl1; // 0xbf8275a4 0x69 398 399 REG16 TSO_PKT_CNT_SEL; // 0xbf8275a8 0x6a 400 #define TSO_PKT_CNT_SEL_MASK 0x000FUL 401 #define TSO_PKT_CNT_LOCKED_CNT_MASK 0x00F0UL 402 #define TSO_PKT_CNT_DBG_MASK 0xFF00UL 403 404 REG16 TSO_PKT_CHKSIZE_FI; // 0xbf8275ac 0x6b 405 #define TSO_PKT_CHKSIZE_FI_MASK 0x00FFUL 406 #define TSO_PKT_CHKSIZE_FI1_MASK 0xFF00UL 407 408 REG32 TSO_LPCR2[2]; // 0xbf8275b0~ 0xbf8275bc 0x6c~0x6f 409 REG32 TSO_TIMESTAMP[2]; // 0xbf8275c0~ 0xbf8275cc 0x70~0x73 410 REG32 TSO_TSO2MI_RADDR[2]; // 0xbf8275d0~ 0xbf8275dc 0x74~0x77 411 412 REG16 TSO_CMDQ_STATUS; // 0xbf8275e0 0x78 413 #define TSO_CMDQ_SIZE 8UL 414 #define TSO_CMDQ_STS_WCNT_MASK 0x000FUL 415 #define TSO_CMDQ_STS_WLEVEL_MASK 0x0030UL 416 #define TSO_CMDQ_STS_FIFO_FULL 0x0040UL 417 #define TSO_CMDQ_STS_FIFO_EMPTY 0x0080UL 418 #define TSO_CMDQ_STS1_SHIFT 8UL 419 420 REG16 TSO_FILE_CFG[1]; // 0xbf8275e4~0xbf8275e8 0x79 421 #define TSO_FICFG_TSO2MI_RPRI 0x0001UL 422 #define TSO_FICFG_MEM_TSDATA_ENDIAN 0x0002UL 423 #define TSO_FICFG_MEM_TS_W_ORDER 0x0004UL 424 #define TSO_FICFG_LPCR2_WLD 0x0008UL 425 #define TSO_FICFG_LPCR2_LD 0x0010UL 426 #define TSO_FICFG_DIS_MIU_RQ 0x0020UL 427 #define TSO_FICFG_RADDR_READ 0x0040UL 428 #define TSO_FICFG_TS_DATAPORT_SEL 0x0080UL 429 #define TSO_FICFG_TSO_FILEIN 0x0100UL 430 #define TSO_FICFG_TIMER_ENABLE 0x0200UL 431 #define TSO_FICFG_PKT192_BLK_DISABLE 0x0400UL 432 #define TSO_FICFG_PKT192_ENABLE 0x0800UL 433 #define TSO_FICFG_FILE_SEGMENT 0x1000UL 434 #define TSO_FICFG_CLK_TIMESTAMP_SEL_MASK 0x2000UL 435 #define TSO_FICFG_CLK_TIMESTAMP_27M 0x2000UL 436 #define TSO_FICFG_CLK_TIMESTAMP_90K 0x0000UL 437 #define TSO_FICFG_INIT_TIMESTAMP 0x4000UL 438 REG16 _xbf8275e8; // 0xbf8275e8 x7a 439 440 REG16 TSO_Interrupt; // 0xbf8275ec 0x7b 441 #define TSO_INT_ENABLE_MASK 0x00FFUL 442 #define TSO_INT_STATUS_MASK 0xFF00UL 443 #define TSO_INT_DMA_DONE 0x0001UL 444 #define TSO_INT_DMA_DONE1 0x0002UL 445 #define TSO_INT_TRCCLK_UPDATE 0x0004UL 446 447 REG16 TSO_Interrupt1; // 0xbf8275f0 0x7c 448 #define TSO_INT1_ENABLE_MASK 0x00FFUL 449 #define TSO_INT1_STATUS_MASK 0xFF00UL 450 #define TSO_INT1_PIDFLT1_OVF 0x0001UL 451 #define TSO_INT1_PIDFLT5_OVF 0x0010UL 452 #define TSO_INT1_PIDFLT6_OVF 0x0020UL 453 454 REG32 TSO_DBG; // 0xbf8275f4~0xbf8275f8 0x7d~0x7e 455 REG16 TSO_DBG_SEL; // 0xbf8275fc 0x7f 456 457 } REG_Ctrl_TSO; 458 459 typedef struct _REG_Ctrl_TSO1 460 { 461 //---------------------------------------------- 462 // 0xBF802A00 MIPS direct access 463 //---------------------------------------------- 464 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 465 466 REG16 TSO_PRE_HEADER1_CFG0; // 0xbf847A00 0x00 467 #define TSO_PRE_HD1_CFG0_LOCAL_STRID_MASK 0x00FFUL 468 469 REG16 TSO_PRE_HEADER1_CFG1; // 0xbf847A04 0x01 470 REG16 TSO_PRE_HEADER1_CFG2; // 0xbf847A08 0x02 471 REG16 TSO_PRE_HEADER1_CFG3; // 0xbf847A0c 0x03 472 473 REG16 _xbf827a10_7a3c[12]; // 0xbf847A10~0xbf847A3c 0x04~0x0f 474 475 REG16 TSO_PRE_HEADER5_CFG0; // 0xbf847A40 0x10 476 REG16 TSO_PRE_HEADER5_CFG1; // 0xbf847A44 0x11 477 REG16 TSO_PRE_HEADER5_CFG2; // 0xbf847A48 0x12 478 REG16 TSO_PRE_HEADER5_CFG3; // 0xbf847A4c 0x13 479 480 REG16 TSO_PRE_HEADER6_CFG0; // 0xbf847A40 0x14 481 REG16 TSO_PRE_HEADER6_CFG1; // 0xbf847A44 0x15 482 REG16 TSO_PRE_HEADER6_CFG2; // 0xbf847A48 0x16 483 REG16 TSO_PRE_HEADER6_CFG3; // 0xbf847A4c 0x17 484 485 REG32 TSO_SVQ1_BASE; // 0xbf847A50~0xbf847A54 0x18~0x19 486 REG16 TSO_SVQ1_SIZE; // 0xbf847A58 0x1a //unit:200byte/pkt 487 REG16 TSO_SVQ1_TX_CFG; // 0xbf847A5c 0x1b 488 #define TSO_SVQ_TX_CFG_WR_THRESHOLD_MASK 0x000FUL 489 #define TSO_SVQ_TX_CFG_PRI_THRESHOLD_MASK 0x00F0UL 490 #define TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK 0x0F00UL 491 #define TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT 8UL 492 #define TSO_SVQ_TX_CFG_TX_RESET 0x1000UL 493 #define TSO_SVQ_TX_CFG_OVF_INT_EN 0x2000UL 494 #define TSO_SVQ_TX_CFG_OVF_CLR 0x4000UL 495 #define TSO_SVQ_TX_CFG_SVQ_EN 0x8000UL 496 497 REG16 _xbf827a60_7a9c[12]; // 0xbf847A60~0xbf847A9c 0x1c~0x27 498 499 REG32 TSO_SVQ5_BASE; // 0xbf847Aa0~0xbf847Aa4 0x28~0x29 500 REG16 TSO_SVQ5_SIZE; // 0xbf847Aa8 0x2a //unit:200byte/pkt 501 REG16 TSO_SVQ5_TX_CFG; // 0xbf847Aac 0x2b 502 503 REG32 TSO_SVQ6_BASE; // 0xbf847Ab0~0xbf847Ab4 0x2c~0x2d 504 REG16 TSO_SVQ6_SIZE; // 0xbf847Ab8 0x2e //unit:200byte/pkt 505 REG16 TSO_SVQ6_TX_CFG; // 0xbf847Abc 0x2f 506 507 REG16 TSO_SVQ_RX_CFG; // 0xbf847Ac0 0x30 508 #define TSO_SVQ_RX_CFG_MODE_MASK 0x0003UL 509 #define TSO_SVQ_RX_CFG_MODE_OPENCBL 0x0000UL 510 #define TSO_SVQ_RX_CFG_MODE_CIPL 0x0001UL 511 #define TSO_SVQ_RX_CFG_MODE_192PKT 0x0002UL 512 #define TSO_SVQ_RX_CFG_MODE_DONGLE 0x0003UL //dongle mode 513 #define TSO_SVQ_RX_CFG_RD_THRESHOLD_MASK 0x001CUL 514 #define TSO_SVQ_RX_CFG_ARBMODE_MASK 0x0060UL 515 #define TSO_SVQ_RX_CFG_ARBMODE_RUNROBIN 0x0000UL 516 #define TSO_SVQ_RX_CFG_ARBMODE_FIXPRI 0x0020UL 517 #define TSO_SVQ_RX_CFG_ARBMODE_DYMPRI 0x0040UL 518 #define TSO_SVQ_RX_CFG_DRAM_SD_ENABLE 0x0080UL 519 #define TSO_SVQ_RX_CFG_SVQ_FORCE_RESET 0x0100UL 520 #define TSO_SVQ_RX_CFG_SVQ_MIU_NS 0x0200UL 521 #define TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK 0x7C00UL 522 #define TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_SHIFT 10UL 523 #define TSO_SVQ_RX_CFG_SVQ_DYN_PRI 0x8000UL 524 525 REG16 TSO_SVQ_RX_PRI[3]; // 0xbf847Ac4~0xbf847Acc 0x31~0x33 526 #define TSO_SVQ_RX_NUM 6UL 527 #define TSO_SVQ_RX_PRI_MASK 0xFFUL 528 #define TSO_SVQ_RX_PRI_SHIFT 8UL 529 530 REG32 TSO_SVQ_STATUS; // 0xbf847Ad0~0xbf847Ad4 0x34~0x35 531 #define TSO_SVQ_STS_MASK 0x000FUL 532 #define TSO_SVQ1_STS_SHIFT 0UL 533 #define TSO_SVQ5_STS_SHIFT 16UL 534 #define TSO_SVQ6_STS_SHIFT 20UL 535 #define TSO_SVQ_STS_EVER_FULL 0x0001UL 536 #define TSO_SVQ_STS_EVER_OVF 0x0002UL 537 #define TSO_SVQ_STS_EMPTY 0x0004UL 538 #define TSO_SVQ_STS_BUSY 0x0008UL 539 540 REG32 TSO_SVQ_STATUS2; // 0xbf847Ad8~0xbf847Adc 0x36~0x37 541 #define TSO_SVQ_STS2_MASK 0x000FUL 542 #define TSO_SVQ1_STS2_SHIFT 0UL 543 #define TSO_SVQ5_STS2_SHIFT 16UL 544 #define TSO_SVQ6_STS2_SHIFT 20UL 545 #define TSO_SVQ_STS2_TXFIFO_WLEVEL_MASK 0x000CUL 546 #define TSO_SVQ_STS2_TXFIFO_FULL 0x0002UL 547 #define TSO_SVQ_STS2_TXFIFO_EMPTY 0x0001UL 548 549 REG32 TSO_DELTA; // 0xbf847Ae0~0xbf847Ae4 0x38~0x39 550 551 REG16 TSO_DELTA_CFG; // 0xbf847Ae8 0x3a 552 #define TSO_DELTA_CFG_SEL_CH_MASK 0x0007UL 553 #define TSO_DELTA_CFG_DELTA_CLR 0x0008UL 554 #define TSO_DELTA_CFG_MAX_ID_MASK 0x0700UL 555 #define TSO_DELTA_CFG_MAX_ID_SHIFT 8UL 556 557 REG32 TSO_DONGLE_TSIF1; 558 REG32 TSO_DONGLE_TSIF2; 559 REG32 TSO_DONGLE_TSIF3; 560 REG32 TSO_DONGLE_TSIF4; 561 REG32 TSO_DONGLE_TSIF5; 562 REG32 TSO_DONGLE_TSIF6; 563 #define TSO_DONGLE_PROTOCAL_ID_MASK 0x000000FF 564 #define TSO_DONGLE_PROTOCAL_ID_SHIFT 0 565 #define TSO_DONGLE_RFU0_MASK 0x0000FF00 566 #define TSO_DONGLE_RFU1_MASK 0x00FF0000 567 #define TSO_DONGLE_STREAM_ID_MASK 0xFF000000 568 #define TSO_DONGLE_STREAM_ID_SHIFT 24 569 570 571 REG16 TSO_MIU_SEL; 572 #define TSO_SVQ_TX1 0x00000001 573 #define TSO_SVQ_TX2 0x00000002 574 #define TSO_PVR 0x00000004 575 #define TSO_SVQ_TX4 0x00000008 576 #define TSO_SVQ_TX5 0x00000010 577 #define TSO_SVQ_TX6 0x00000020 578 #define TSO_SVQ_RX 0x00000040 579 #define TSO_FI_CH5 0x00000080 580 #define TSO_FI_CH6 0x00000100 581 } REG_Ctrl_TSO1; 582 583 584 #endif // _TSO_REG_H_ 585 586