1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSO.h 98 // Description: TS I/O Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSO_REG_H_ 103 #define _TSO_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 //@TODO check ENG PIDFLT TSIF number 138 139 #define TSO_ENGINE_NUM (1) 140 #define TSO_PIDFLT_NUM (256) 141 #define TSO_REP_PIDFLT_NUM (16) 142 #define TSO_FILE_IF_NUM (2) 143 #define TSO_TSIF_NUM (6) 144 145 #define TSO_PIDFLT_NUM_ALL TSO_PIDFLT_NUM 146 147 #define TSO_PID_NULL (0x1FFF) 148 #define TSO_MIU_BUS (4) 149 #define TSO_SVQ_UNIT_SIZE (208) 150 151 //------------------------------------------------------------------------------------------------- 152 // Harware Capability 153 //------------------------------------------------------------------------------------------------- 154 #define TSO_CLKIN_TS0 0x00 155 #define TSO_CLKIN_TS1 0x01 156 #define TSO_CLKIN_TS2 0x02 157 #define TSO_CLKIN_TS3 0x03 158 #define TSO_CLKIN_TS4 0x04 159 #define TSO_CLKIN_TS5 0x05 160 #define TSO_CLKIN_TS6 0x06 161 #define TSO_CLKIN_TSO0_OUT_P 0x07 162 #define TSO_CLKIN_DMD 0x0E 163 164 //------------------------------------------------------------------------------------------------- 165 // Type and Structure 166 //------------------------------------------------------------------------------------------------- 167 #define REG_PIDFLT_BASE (0x210000UL) 168 #define TSO_PIDFLT_PID_MASK (0x1FFF) 169 #define TSO_PIDFLT_IN_MASK (0x7) 170 #define TSO_PIDFLT_IN_SHIFT (13) 171 172 #define REG_CTRL_BASE_TSO (0xE0C00UL) // 0x1706 173 #define REG_CTRL_BASE_TSO1 (0xC2400UL) // 0x1612 174 #define REG_CTRL_BASE_TSO2 (0xA7200UL) // 0x1539 175 176 177 typedef struct _REG32_TSO 178 { 179 volatile MS_U16 L; 180 volatile MS_U16 empty_L; 181 volatile MS_U16 H; 182 volatile MS_U16 empty_H; 183 } REG32_TSO; 184 185 typedef struct _REG16_TSO 186 { 187 volatile MS_U16 data; 188 volatile MS_U16 _resv; 189 } REG16_TSO; 190 191 //TSO0 192 typedef struct _REG_Ctrl_TSO 193 { 194 //---------------------------------------------- 195 // 0xBF802A00 MIPS direct access 196 //---------------------------------------------- 197 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 198 REG16_TSO SW_RSTZ; //00 199 #define TSO_SW_RSTZ 0x0001 200 #define TSO_SW_RST_CLK_STAMP 0x0002 201 #define TSO_SW_RST_CMDQ1 0x0100 202 #define TSO_SW_RST_WB1 0x0200 203 #define TSO_SW_RST_WB_DMA1 0x0400 204 #define TSO_SW_RST_TS_FIN1 0x0800 205 #define TSO_SW_RST_CMDQ 0x1000 206 #define TSO_SW_RST_WB 0x2000 207 #define TSO_SW_RST_WB_DMA 0x4000 208 #define TSO_SW_RST_FIN 0x8000 209 #define TSO_SW_RST_ALL 0xF002 210 #define TSO_SW_RST_ALL1 0x0F02 211 212 213 REG16_TSO SW_RSTZ1; //01 214 #define TSO_SW_RST_CHANNEL_IF1 0x0001 215 #define TSO_SW_RST_CHANNEL_IF2 0x0002 216 #define TSO_SW_RST_CHANNEL_IF3 0x0004 217 #define TSO_SW_RST_CHANNEL_IF4 0x0008 218 #define TSO_SW_RST_CHANNEL_IF5 0x0010 219 #define TSO_SW_RST_CHANNEL_IF6 0x0020 220 221 REG16_TSO CFG_TSO_02_03[2]; 222 223 REG16_TSO CHANNEL0_IF1_CONFIG0; //04 224 #define TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF //for internal sync 225 #define TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 226 #define TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 227 #define TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 228 229 REG16_TSO CHANNEL0_IF1_CONFIG1; //05 230 #define TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK 0x00FF 231 #define TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_SHIFT 0 232 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 233 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_SHIFT 8 234 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 235 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_SHIFT 11 236 237 REG16_TSO CHANNEL0_IF1_CONFIG2; //06 238 //----- for TV comaptibility -----// 239 #define TSO_CHCFG_P_SEL 0x0001 240 #define TSO_CHCFG_EXT_SYNC_SEL 0x0002 241 #define TSO_CHCFG_TS_SIN_C0 0x0004 242 #define TSO_CHCFG_TS_SIN_C1 0x0008 243 #define TSO_CHCFG_PIDFLT_REC_ALL 0x0010 244 #define TSO_CHCFG_PIDFLT_REC_NULL 0x0020 245 #define TSO_CHCFG_PIDFLT_OVF_INT_EN 0x0040 246 #define TSO_CHCFG_PIDFLT_OVF_CLR 0x0080 247 #define TSO_CHCFG_FORCE_SYNC_BYTE 0x0100 248 #define TSO_CHCFG_SKIP_TEI_PKT 0x0200 249 #define TSO_CHCFG_DIS_LOCKED_PKT_CNT 0x0400 250 #define TSO_CHCFG_CLR_LOCKED_PKT_CNT 0x0800 251 #define TSO_CHCFG_TRC_CLK_LD_DIS 0x1000 252 #define TSO_CHCFG_TRC_CLK_CLR 0x2000 253 #define TSO_CHCFG_SRC_ID_FLT_EN 0x4000 254 #define TSO_CHCFG_PKT_CVT_OVERFLOW1_CLR 0x8000 255 256 //--------------------------------// 257 258 REG16_TSO CHANNEL0_IF1_CONFIG3; //07 reserved 259 260 REG16_TSO CHANNEL0_IF2_CONFIG0; //08 261 #define TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 262 #define TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 263 #define TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 264 #define TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 265 266 REG16_TSO CHANNEL0_IF2_CONFIG1; //09 267 #define TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK 0x00FF 268 #define TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_SHIFT 0 269 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 270 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_SHIFT 8 271 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 272 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_SHIFT 11 273 274 REG16_TSO CHANNEL0_IF2_CONFIG2; //0a 275 #define TSO_CHANNEL0_IF2_CONFIG2_P_SEL 0x0001 276 #define TSO_CHANNEL0_IF2_CONFIG2_EXT_SYNC_SEL 0x0002 277 #define TSO_CHANNEL0_IF2_CONFIG2_TS_SIN_C0 0x0004 278 #define TSO_CHANNEL0_IF2_CONFIG2_TS_SIN_C1 0x0008 279 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL 0x0010 280 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_NULL 0x0020 281 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 282 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 283 #define TSO_CHANNEL0_IF2_CONFIG2_FORCE_SYNC_BYTE 0x0100 284 #define TSO_CHANNEL0_IF2_CONFIG2_SKIP_TEI_PKT 0x0200 285 #define TSO_CHANNEL0_IF2_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 286 #define TSO_CHANNEL0_IF2_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 287 #define TSO_CHANNEL0_IF2_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 288 #define TSO_CHANNEL0_IF2_CONFIG2_TRACING_CLOCK_CLR 0x2000 289 #define TSO_CHANNEL0_IF2_CONFIG2_SRC_ID_FLT_EN 0x4000 290 #define TSO_CHANNEL0_IF2_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 291 292 REG16_TSO CHANNEL0_IF2_CONFIG3; //0b reserved 293 294 REG16_TSO CHANNEL0_IF3_CONFIG0; //0c 295 #define TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 296 #define TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 297 #define TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 298 #define TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 299 300 REG16_TSO CHANNEL0_IF3_CONFIG1; //0d 301 #define TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK 0x00FF 302 #define TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_SHIFT 0 303 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 304 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_SHIFT 8 305 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 306 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_SHIFT 11 307 308 REG16_TSO CHANNEL0_IF3_CONFIG2; //0e 309 #define TSO_CHANNEL0_IF3_CONFIG2_P_SEL 0x0001 310 #define TSO_CHANNEL0_IF3_CONFIG2_EXT_SYNC_SEL 0x0002 311 #define TSO_CHANNEL0_IF3_CONFIG2_TS_SIN_C0 0x0004 312 #define TSO_CHANNEL0_IF3_CONFIG2_TS_SIN_C1 0x0008 313 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL 0x0010 314 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_NULL 0x0020 315 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 316 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 317 #define TSO_CHANNEL0_IF3_CONFIG2_FORCE_SYNC_BYTE 0x0100 318 #define TSO_CHANNEL0_IF3_CONFIG2_SKIP_TEI_PKT 0x0200 319 #define TSO_CHANNEL0_IF3_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 320 #define TSO_CHANNEL0_IF3_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 321 #define TSO_CHANNEL0_IF3_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 322 #define TSO_CHANNEL0_IF3_CONFIG2_TRACING_CLOCK_CLR 0x2000 323 #define TSO_CHANNEL0_IF3_CONFIG2_SRC_ID_FLT_EN 0x4000 324 #define TSO_CHANNEL0_IF3_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 325 326 REG16_TSO CHANNEL0_IF3_CONFIG3; //0f reserved 327 328 REG16_TSO CHANNEL0_IF4_CONFIG0; //10 329 #define TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 330 #define TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 331 #define TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 332 #define TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 333 334 REG16_TSO CHANNEL0_IF4_CONFIG1; //11 335 #define TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK 0x00FF 336 #define TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_SHIFT 0 337 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 338 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_SHIFT 8 339 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 340 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_SHIFT 11 341 342 REG16_TSO CHANNEL0_IF4_CONFIG2; //12 343 #define TSO_CHANNEL0_IF4_CONFIG2_P_SEL 0x0001 344 #define TSO_CHANNEL0_IF4_CONFIG2_EXT_SYNC_SEL 0x0002 345 #define TSO_CHANNEL0_IF4_CONFIG2_TS_SIN_C0 0x0004 346 #define TSO_CHANNEL0_IF4_CONFIG2_TS_SIN_C1 0x0008 347 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL 0x0010 348 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_NULL 0x0020 349 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 350 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 351 #define TSO_CHANNEL0_IF4_CONFIG2_FORCE_SYNC_BYTE 0x0100 352 #define TSO_CHANNEL0_IF4_CONFIG2_SKIP_TEI_PKT 0x0200 353 #define TSO_CHANNEL0_IF4_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 354 #define TSO_CHANNEL0_IF4_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 355 #define TSO_CHANNEL0_IF4_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 356 #define TSO_CHANNEL0_IF4_CONFIG2_TRACING_CLOCK_CLR 0x2000 357 #define TSO_CHANNEL0_IF4_CONFIG2_SRC_ID_FLT_EN 0x4000 358 #define TSO_CHANNEL0_IF4_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 359 360 REG16_TSO CHANNEL0_IF4_CONFIG3; //13 reserved 361 362 REG16_TSO CHANNEL0_IF5_CONFIG0; //14 363 #define TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 364 #define TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 365 #define TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 366 #define TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 367 368 REG16_TSO CHANNEL0_IF5_CONFIG1; //15 369 #define TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK 0x00FF 370 #define TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_SHIFT 0 371 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 372 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT 8 373 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 374 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_SHIFT 11 375 376 REG16_TSO CHANNEL0_IF5_CONFIG2; //16 377 #define TSO_CHANNEL0_IF5_CONFIG2_P_SEL 0x0001 378 #define TSO_CHANNEL0_IF5_CONFIG2_EXT_SYNC_SEL 0x0002 379 #define TSO_CHANNEL0_IF5_CONFIG2_TS_SIN_C0 0x0004 380 #define TSO_CHANNEL0_IF5_CONFIG2_TS_SIN_C1 0x0008 381 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL 0x0010 382 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_NULL 0x0020 383 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 384 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 385 #define TSO_CHANNEL0_IF5_CONFIG2_FORCE_SYNC_BYTE 0x0100 386 #define TSO_CHANNEL0_IF5_CONFIG2_SKIP_TEI_PKT 0x0200 387 #define TSO_CHANNEL0_IF5_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 388 #define TSO_CHANNEL0_IF5_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 389 #define TSO_CHANNEL0_IF5_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 390 #define TSO_CHANNEL0_IF5_CONFIG2_TRACING_CLOCK_CLR 0x2000 391 #define TSO_CHANNEL0_IF5_CONFIG2_SRC_ID_FLT_EN 0x4000 392 #define TSO_CHANNEL0_IF5_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 393 394 REG16_TSO CHANNEL0_IF5_CONFIG3; //17 reserved 395 396 REG16_TSO CHANNEL0_IF6_CONFIG0; //18 397 #define TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 398 #define TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 399 #define TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 400 #define TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 401 402 REG16_TSO CHANNEL0_IF6_CONFIG1; //19 403 #define TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK 0x00FF 404 #define TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_SHIFT 0 405 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 406 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_SHIFT 8 407 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 408 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_SHIFT 11 409 410 REG16_TSO CHANNEL0_IF6_CONFIG2; //1a 411 #define TSO_CHANNEL0_IF6_CONFIG2_P_SEL 0x0001 412 #define TSO_CHANNEL0_IF6_CONFIG2_EXT_SYNC_SEL 0x0002 413 #define TSO_CHANNEL0_IF6_CONFIG2_TS_SIN_C0 0x0004 414 #define TSO_CHANNEL0_IF6_CONFIG2_TS_SIN_C1 0x0008 415 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL 0x0010 416 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_NULL 0x0020 417 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 418 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 419 #define TSO_CHANNEL0_IF6_CONFIG2_FORCE_SYNC_BYTE 0x0100 420 #define TSO_CHANNEL0_IF6_CONFIG2_SKIP_TEI_PKT 0x0200 421 #define TSO_CHANNEL0_IF6_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 422 #define TSO_CHANNEL0_IF6_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 423 #define TSO_CHANNEL0_IF6_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 424 #define TSO_CHANNEL0_IF6_CONFIG2_TRACING_CLOCK_CLR 0x2000 425 #define TSO_CHANNEL0_IF6_CONFIG2_SRC_ID_FLT_EN 0x4000 426 #define TSO_CHANNEL0_IF6_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 427 428 REG16_TSO CHANNEL0_IF6_CONFIG3; //1b reserved 429 430 REG16_TSO TSO_CONFIG0; //1c 431 #define TSO_CONFIG0_S2P_EN 0x0001 432 #define TSO_CONFIG0_S2P_TS_SIN_C0 0x0002 433 #define TSO_CONFIG0_S2P_TS_SIN_C1 0x0004 434 #define TSO_CONFIG0_S2P_3WIRE_MODE 0x0008 435 #define TSO_CONFIG0_BYPASS_S2P 0x0010 436 #define TSO_CONFIG0_S2P1_EN 0x0100 437 #define TSO_CONFIG0_S2P1_TS_SIN_C0 0x0200 438 #define TSO_CONFIG0_S2P1_TS_SIN_C1 0x0400 439 #define TSO_CONFIG0_S2P1_3WIRE_MODE 0x0800 440 #define TSO_CONFIG0_BYPASS_S2P1 0x1000 441 442 REG16_TSO TSO_CONFIG1; //1d 443 //----- for TV comaptibility -----// 444 #define TSO_CFG1_TSO_OUT_EN 0x0001 445 #define TSO_CFG1_TSO_TSIF1_EN 0x0002 446 #define TSO_CFG1_TSO_TSIF2_EN 0x0004 447 #define TSO_CFG1_TSO_TSIF3_EN 0x0008 448 #define TSO_CFG1_TSO_TSIF4_EN 0x0010 449 #define TSO_CFG1_TSO_TSIF5_EN 0x0020 450 #define TSO_CFG1_TSO_TSIF6_EN 0x0040 451 //--------------------------------// 452 #define TSO_CONFIG1_PAUSE_OPIF 0x0080 453 #define TSO_CONFIG1_TURN_OFF_MCM 0x0100 454 #define TSO_CONFIG1_CLOCK_TRACING_SEL_MASK 0x0E00 455 #define TSO_CONFIG1_CLOCK_TRACING_SEL_SHIFT 9 456 #define TSO_CONFIG1_SERIAL_OUT_EN 0x1000 457 #define TSO_CONFIG1_PKT_LOCK_CLR 0x2000 458 #define TSO_CONFIG1_PKT_NULL_EN 0x4000 459 //----- for TV comaptibility -----// 460 #define TSO_CFG1_PKT_PARAM_LD 0x8000 461 //--------------------------------// 462 463 REG16_TSO TSO_CONFIG2; //1e 464 #define TSO_CONFIG2_VALID_BYTE_CNT_MASK 0x00FF 465 #define TSO_CONFIG2_VALID_BYTE_CNT_SHIFT 0 466 #define TSO_CONFIG2_INVALID_BYTE_CNT_MASK 0xFF00 467 #define TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT 8 468 469 REG16_TSO TSO_CONFIG3; //1f 470 #define TSO_CONFIG3_OPIF_PKT_SIZE_MASK 0xFFFF 471 472 REG32_TSO PIDFLTS[16]; //20~3e PID00~0F 473 //FOR ALL PID 474 #define TSO_PID_ORIGINAL_PID_MASK 0x00001FFF 475 #define TSO_PID_ORIGINAL_PID_SHIFT 0 476 #define TSO_PID_SOURCE_SEL_MASK 0x0000E000 477 #define TSO_PID_SOURCE_SEL_SHIFT 13 478 #define TSO_PID_NEW_PID_MASK 0x1FFF0000 479 #define TSO_PID_NEW_PID_SHIFT 16 480 #define TSO_PID_REPLACE_EN 0x80000000 481 482 REG16_TSO CLR_BYTE_CNT; //40 483 #define TSO_CLR_BYTE_CNT_1 0x0001 484 #define TSO_CLR_BYTE_CNT_2 0x0002 485 #define TSO_CLR_BYTE_CNT_3 0x0004 486 #define TSO_CLR_BYTE_CNT_4 0x0008 487 #define TSO_CLR_BYTE_CNT_5 0x0010 488 #define TSO_CLR_BYTE_CNT_6 0x0020 489 490 REG16_TSO CFG_TSO_41_42[2]; //41~42 491 492 REG16_TSO TSO_CONFIG4; //43 493 #define TSO_CFG4_LOCK_RETURN_SYSTEM_TIMESTAMP 0x0001 494 #define TSO_CFG4_ENABLE_SYS_TIMESTAMP 0x0002 495 #define TSO_CFG4_SET_SYS_TIMESTAMP_TO_HW 0x0004 496 #define TSO_CFG4_TIMESTAMP_BASE 0x0008 //0:90k 1:27m 497 #define TSO_CFG4_PDTABLE_SRAM_SD_EN 0x0010 498 //------------------------------------------------------------------------ 499 #define TSO_CFG4_FIX_TIMESTAMP_RING_BACK_EN 0x0020 500 #define TSO_CFG4_FIX_LPCR_RING_BACK_EN 0x0040 501 #define TSO_CFG4_INIT_TIMESTAMP_RESTART_EN 0x0080 502 //------------------------------------------------------------------------ 503 #define TSO_CFG4_NULL_PKT_ID_MASK 0xFF00 504 #define TSO_CFG4_NULL_PKT_ID_SHIFT 8 505 506 REG16_TSO TSO_CONFIG5; //44 507 #define TSO_CONFIG5_3_WIRE_EN_1 0x0001 508 #define TSO_CONFIG5_3_WIRE_EN_2 0x0002 509 #define TSO_CONFIG5_3_WIRE_EN_3 0x0004 510 #define TSO_CONFIG5_3_WIRE_EN_4 0x0008 511 #define TSO_CONFIG5_3_WIRE_EN_5 0x0010 512 #define TSO_CONFIG5_3_WIRE_EN_6 0x0020 513 #define TSO_CONFIG5_DIS_MIU_RQ 0x0040 514 #define TSO_CONFIG5_FIXED_MIU_REG_FLUSH 0x0080 // fix svq_tx error 515 #define TSO_CONFIG5_EXTEND_ENABLE 0x0100 // fix svq_tx error 516 #define TSO_CONFIG5_REG_VQ_IDLE_CNT_DIS 0x0200 // fix svq_tx error 517 #define TSO_CONFIG5_REG_TSIO_MODE 0x0400 518 #define TSO_CONFIG5_REG_TSIO2OPIF 0x0800 519 #define TSO_CONFIG5_BYPASS_SVQ_FOR_CH1 0x1000 520 #define TSO_CONFIG5_REG_CHECK_VQ_BURST_LEN 0x2000 521 522 REG16_TSO PDTABLE_ADDR_L; //45 ind R/W of L addr to pdtable 523 REG16_TSO PDTABLE_ADDR_H; //46 ind R/W of H addr to pdtable 524 525 REG16_TSO PDTABLE_WDATA_L; //47 ind R/W of L addr to pdtable 526 REG16_TSO PDTABLE_WDATA_H; //48 ind R/W of L addr to pdtable 527 528 REG16_TSO PDTABLE_RDATA; //49 ind of Rdata from pdtable 529 530 REG16_TSO PDTABLE_EN; //4a 531 #define TSO_PDTABLE_W_EN 0x0001//Ind W flag to pdtable 532 #define TSO_PDTABLE_R_EN 0x0002//Ind R flag to pdtable 533 534 #define TSO_PDTABLE_RDATA_H_MASK 0x3F00 // ind of Rdata[21:16] from pdtable 535 536 REG16_TSO TSO_STATUS; //4b 537 #define TSO_STATUS_SVQ_MASK 0x7F00 538 #define TSO_STATUS_SVQ_SHIFT 8 539 #define TSO_STATUS_PDFLT 0x8000 540 541 REG16_TSO FILE_TIMER[2]; //4c ~ 4d 542 543 REG16_TSO TSO_STATUS1; //4e 544 #define TSO_STATUS1_EVEROVERFLOW_TSIF_1 0x0001 545 #define TSO_STATUS1_EVEROVERFLOW_TSIF_2 0x0002 546 #define TSO_STATUS1_EVEROVERFLOW_TSIF_3 0x0004 547 #define TSO_STATUS1_EVEROVERFLOW_TSIF_4 0x0008 548 #define TSO_STATUS1_EVEROVERFLOW_TSIF_5 0x0010 549 #define TSO_STATUS1_EVEROVERFLOW_TSIF_6 0x0020 550 551 REG16_TSO CFG_TSO_4F_5A[12]; //4f~5a 552 553 REG16_TSO TSO_TRACING_HIGH; //5b 554 REG16_TSO TSO_TRACING_LOW; //5c 555 REG16_TSO TSO_TRACING_1T; //5d 556 REG16_TSO TSO_BLOCK_SIZE_DB; //5e 557 REG16_TSO TSO_OPT_SZIE_DB; //5f 558 559 REG32_TSO CFG_TSO_60_63[2]; //60~63 560 REG16_TSO TSO_Filein_Ctrl; //64 561 REG32_TSO CFG_TSO_65_68[2]; //65~68 562 REG16_TSO TSO_Filein_Ctrl1; //69 563 #define TSO_FILEIN_CTRL_MASK 0x0007 564 #define TSO_FILEIN_RSTART 0x0001 565 #define TSO_FILEIN_ABORT 0x0002 566 #define TSO_FILEIN_TRUST 0x0004 567 568 REG16_TSO PKT_CNT_SEL; //6a 569 #define TSO_PKT_CNT_RETURN_SEL_MASK 0x000F 570 #define TSO_PKT_CNT_RETURN_SEL_SHIFT 0 571 #define TSO_PKT_CNT_DBG_LOCKED_PKT_CNT_MASK 0x00F0 572 #define TSO_PKT_CNT_DBG_LOCKED_PKT_CNT_SHIFT 4 573 #define TSO_PKT_CNT_DBG_PKT_CNTT_DBG_MASK 0xFF00 574 #define TSO_PKT_CNT_DBG_PKT_CNTT_DBG_SHIFT 8 575 576 REG16_TSO PKT_CHK_SIZE_FIN; //6b 577 #define TSO_PKT_CHK_SIZE_FIN_MASK 0x00FF 578 #define TSO_PKT_CHK_SIZE_FIN_SHIFT 0 579 #define TSO_PKT_CHK_SIZE_FIN1_MASK 0xFF00 580 #define TSO_PKT_CHK_SIZE_FIN1_SHIFT 8 581 582 REG32_TSO LPCR2_BUF; //6c~6d 583 REG32_TSO LPCR2_BUF1; //6e~6f 584 585 REG32_TSO TIMESTAMP; //70~71 586 REG32_TSO TIMESTAMP1; //72~73 587 588 REG32_TSO TSO2MI_RADDR; //74~75 589 REG32_TSO TSO2MI_RADDR1; //76~77 590 591 REG16_TSO CMD_QUEUE_STATUS; //78 592 #define TSO_CMDQ_SIZE 16 593 #define TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_MASK 0x000F 594 #define TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_SHIFT 0 595 #define TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_MASK 0x0030 596 #define TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_SHIFT 4 597 #define TSO_CMD_QUEUE_STATUS_CMD_FIFO_FULL 0x0040 598 #define TSO_CMD_QUEUE_STATUS_CMD_FIFO_EMPTY 0x0080 599 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_MASK 0x0F00 600 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_SHIFT 8 601 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_MASK 0x3000 602 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_SHIFT 12 603 #define TSO_CMD_QUEUE_STATUS1_CMD_FIFO_FULL 0x4000 604 #define TSO_CMD_QUEUE_STATUS1_CMD_FIFO_EMPTY 0x8000 605 606 REG16_TSO TSO_FILE_CONFIG; //79 607 #define TSO_FILE_CONFIG_TSO2MI_RPRIORITY 0x0001 608 #define TSO_FILE_CONFIG_MEM_TS_DATA_ENDIAN 0x0002 609 #define TSO_FILE_CONFIG_MEM_TS_W_ORDER 0x0004 610 #define TSO_FILE_CONFIG_LPCR2_WLD 0x0008 611 #define TSO_FILE_CONFIG_LPCR2_LOAD 0x0010 612 #define TSO_FILE_CONFIG_DIS_MIU_RQ 0x0020 613 #define TSO_FILE_CONFIG_TSO_RADDR_READ 0x0040 614 #define TSO_FILE_CONFIG_TS_DATA_PORT_SEL 0x0080 615 #define TSO_FILE_CONFIG_TSO_FILE_IN 0x0100 616 #define TSO_FILE_CONFIG_TIMER_EN 0x0200 617 #define TSO_FILE_CONFIG_PKT_192_BLK_DISABLE 0x0400 618 #define TSO_FILE_CONFIG_PKT_192_EN 0x0800 619 #define TSO_FILE_CONFIG_TSP_FILE_SEGMENT 0x1000 620 #define TSO_FILE_CONFIG_CLK_STAMP_27_EN 0x2000 621 #define TSO_FILE_CONFIG_INIT_TIMESTAMP 0x4000 622 623 REG16_TSO TSO_FILE_CONFIG1; //7a 624 #define TSO_FILE_CONFIG1_TSO2MI_RPRIORITY 0x0001 625 #define TSO_FILE_CONFIG1_MEM_TS_DATA_ENDIAN 0x0002 626 #define TSO_FILE_CONFIG1_MEM_TS_W_ORDER 0x0004 627 #define TSO_FILE_CONFIG1_LPCR2_WLD 0x0008 628 #define TSO_FILE_CONFIG1_LPCR2_LOAD 0x0010 629 #define TSO_FILE_CONFIG1_DIS_MIU_RQ 0x0020 630 #define TSO_FILE_CONFIG1_TSO_RADDR_READ 0x0040 631 #define TSO_FILE_CONFIG1_TS_DATA_PORT_SEL 0x0080 632 #define TSO_FILE_CONFIG1_TSO_FILE_IN 0x0100 633 #define TSO_FILE_CONFIG1_TIMER_EN 0x0200 634 #define TSO_FILE_CONFIG1_PKT_192_BLK_DISABLE 0x0400 635 #define TSO_FILE_CONFIG1_PKT_192_EN 0x0800 636 #define TSO_FILE_CONFIG1_TSP_FILE_SEGMENT 0x1000 637 #define TSO_FILE_CONFIG1_CLK_STAMP_27_EN 0x2000 638 #define TSO_FILE_CONFIG1_INIT_TIMESTAMP 0x4000 639 640 REG16_TSO INTERRUPT; //7b 641 #define TSO_INT_SRC_MASK 0x00FF 642 #define TSO_INT_STS_MASK 0xFF00 643 //----- for TV comaptibility -----// 644 #define TSO_INT_DMA_DONE 0x0001 645 #define TSO_INT_DMA_DONE1 0x0002 646 //--------------------------------// 647 #define TSO_INT_SRC_TRAC_CLK_UPDATE 0x0004 648 #define TSO_INT_STS_DMA_DONE 0x0100 649 #define TSO_INT_STS_DMA_DONE1 0x0200 650 #define TSO_INT_STS_TRAC_CLK_UPDATE 0x0400 651 652 REG16_TSO INTERRUPT1; //7c 653 #define TSO_INT_SRC_PIDFLT1_OVERFLOW 0x0001 654 #define TSO_INT_SRC_PIDFLT2_OVERFLOW 0x0002 655 #define TSO_INT_SRC_PIDFLT3_OVERFLOW 0x0004 656 #define TSO_INT_SRC_PIDFLT4_OVERFLOW 0x0008 657 #define TSO_INT_SRC_PIDFLT5_OVERFLOW 0x0010 658 #define TSO_INT_SRC_PIDFLT6_OVERFLOW 0x0020 659 660 #define TSO_INT_STS_PIDFLT1_OVERFLOW 0x0100 661 #define TSO_INT_STS_PIDFLT2_OVERFLOW 0x0200 662 #define TSO_INT_STS_PIDFLT3_OVERFLOW 0x0400 663 #define TSO_INT_STS_PIDFLT4_OVERFLOW 0x0800 664 #define TSO_INT_STS_PIDFLT5_OVERFLOW 0x1000 665 #define TSO_INT_STS_PIDFLT6_OVERFLOW 0x2000 666 667 REG32_TSO TSO_DEBUG; //7d~7e 668 669 REG16_TSO DBG_SEL; //7f 670 671 } REG_Ctrl_TSO; 672 673 674 //TSO1 675 typedef struct _REG_Ctrl_TSO1 676 { 677 //---------------------------------------------- 678 // 0xBF802C00 MIPS direct access 679 //---------------------------------------------- 680 681 REG16_TSO REG_PRE_HEADER_1_CONFIG_0; //00 682 #define TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 683 #define TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_SHIFT 0 684 685 REG16_TSO REG_PRE_HEADER_1_CONFIG_1; //01 686 REG16_TSO REG_PRE_HEADER_1_CONFIG_2; //02 687 REG16_TSO REG_PRE_HEADER_1_CONFIG_3; //03 688 689 REG16_TSO REG_PRE_HEADER_2_CONFIG_0; //04 690 #define TSO1_REG_PRE_HEADER_2_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 691 #define TSO1_REG_PRE_HEADER_2_CONFIG_0_LOCAL_STREAMID_SHIFT 0 692 693 REG16_TSO REG_PRE_HEADER_2_CONFIG_1; //05 694 REG16_TSO REG_PRE_HEADER_2_CONFIG_2; //06 695 REG16_TSO REG_PRE_HEADER_2_CONFIG_3; //07 696 697 REG16_TSO REG_PRE_HEADER_3_CONFIG_0; //08 698 #define TSO1_REG_PRE_HEADER_3_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 699 #define TSO1_REG_PRE_HEADER_3_CONFIG_0_LOCAL_STREAMID_SHIFT 0 700 701 REG16_TSO REG_PRE_HEADER_3_CONFIG_1; //09 702 REG16_TSO REG_PRE_HEADER_3_CONFIG_2; //0a 703 REG16_TSO REG_PRE_HEADER_3_CONFIG_3; //0b 704 705 REG16_TSO REG_PRE_HEADER_4_CONFIG_0; //0c 706 #define TSO1_REG_PRE_HEADER_4_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 707 #define TSO1_REG_PRE_HEADER_4_CONFIG_0_LOCAL_STREAMID_SHIFT 0 708 709 REG16_TSO REG_PRE_HEADER_4_CONFIG_1; //0d 710 REG16_TSO REG_PRE_HEADER_4_CONFIG_2; //0e 711 REG16_TSO REG_PRE_HEADER_4_CONFIG_3; //0f 712 713 REG16_TSO REG_PRE_HEADER_5_CONFIG_0; //10 714 #define TSO1_REG_PRE_HEADER_5_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 715 #define TSO1_REG_PRE_HEADER_5_CONFIG_0_LOCAL_STREAMID_SHIFT 0 716 717 REG16_TSO REG_PRE_HEADER_5_CONFIG_1; //11 718 REG16_TSO REG_PRE_HEADER_5_CONFIG_2; //12 719 REG16_TSO REG_PRE_HEADER_5_CONFIG_3; //13 720 721 REG16_TSO REG_PRE_HEADER_6_CONFIG_0; //14 722 #define TSO1_REG_PRE_HEADER_6_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 723 #define TSO1_REG_PRE_HEADER_6_CONFIG_0_LOCAL_STREAMID_SHIFT 0 724 725 REG16_TSO REG_PRE_HEADER_6_CONFIG_1; //15 726 REG16_TSO REG_PRE_HEADER_6_CONFIG_2; //16 727 REG16_TSO REG_PRE_HEADER_6_CONFIG_3; //17 728 729 REG32_TSO SVQ1_BASE; //18~19 730 #define TSO1_SVQ1_BASE_MASK 0x0FFFFFFF 731 #define TSO1_SVQ1_BASE_SHIFT 0 732 733 REG16_TSO SVQ1_SIZE_200BYTE; //1a 734 #define TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_MASK 0xFFFF 735 #define TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_SHIFT 0 736 737 REG16_TSO SVQ1_TX_CONFIG; //1b 738 #define TSO1_SVQ1_TX_CONFIG_WR_THRESHOLD_MASK 0x000F 739 #define TSO1_SVQ1_TX_CONFIG_WR_THRESHOLD_SHIFT 0 740 #define TSO1_SVQ1_TX_CONFIG_PRIORITY_THRESHOLD_MASK 0x00F0 741 #define TSO1_SVQ1_TX_CONFIG_PRIORITY_THRESHOLD_SHIFT 4 742 #define TSO1_SVQ1_TX_CONFIG_FORCEFIRE_CNT_MASK 0x0F00 743 #define TSO1_SVQ1_TX_CONFIG_FORCEFIRE_CNT_SHIFT 8 744 #define TSO1_SVQ1_TX_CONFIG_TX_RESET 0x1000 745 #define TSO1_SVQ1_TX_CONFIG_OVERFLOW_INT_EN 0x2000 746 #define TSO1_SVQ1_TX_CONFIG_OVERFLOW_CLR 0x4000 747 #define TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE 0x8000 748 REG32_TSO SVQ2_BASE; //1C~1D 749 REG16_TSO SVQ2_SIZE_200BYTE; //1E 750 REG16_TSO SVQ2_TX_CONFIG; //1F 751 REG32_TSO SVQ3_BASE; //20~21 752 REG16_TSO SVQ3_SIZE_200BYTE; //22 753 REG16_TSO SVQ3_TX_CONFIG; //23 754 REG32_TSO SVQ4_BASE; //24~25 755 REG16_TSO SVQ4_SIZE_200BYTE; //26 756 REG16_TSO SVQ4_TX_CONFIG; //27 757 REG32_TSO SVQ5_BASE; //28~29 758 REG16_TSO SVQ5_SIZE_200BYTE; //2a 759 REG16_TSO SVQ5_TX_CONFIG; //2b 760 REG32_TSO SVQ6_BASE; //2C~2D 761 REG16_TSO SVQ6_SIZE_200BYTE; //2E 762 REG16_TSO SVQ6_TX_CONFIG; //2F 763 764 REG16_TSO SVQ_RX_CONFIG; //30 765 #define TSO1_SVQ_RX_CONFIG_MODE_MASK 0x0003 //00=open cable 01=CI+ 10=192 mode 766 #define TSO1_SVQ_RX_CONFIG_MODE_SHIT 0 767 //----- for TV comaptibility -----// 768 #define TSO_SVQ_RX_CFG_MODE_OPENCBL 0x0000 769 #define TSO_SVQ_RX_CFG_MODE_CIPL 0x0001 770 #define TSO_SVQ_RX_CFG_MODE_192PKT 0x0002 771 //--------------------------------// 772 #define TSO1_SVQ_RX_CONFIG_RD_THRESHOLD_MASK 0x001C //000=1/6 empty 001=1/8 empty 010=1/4 empty 011=1/2 empty else empty 773 #define TSO1_SVQ_RX_CONFIG_RD_THRESHOLD_SHIT 2 774 #define TSO1_SVQ_RX_CONFIG_ARBITOR_MODE_MASK 0x0060 //00=Run-Robin. 01=fix priority by REG 0x31~33 mode 10=dynamic priority 775 #define TSO1_SVQ_RX_CONFIG_ARBITOR_MODE_SHIT 5 776 //----- for TV comaptibility -----// 777 #define TSO_SVQ_RX_CFG_ARBMODE_RUNROBIN 0x0000 778 #define TSO_SVQ_RX_CFG_ARBMODE_FIXPRI 0x0001 779 #define TSO_SVQ_RX_CFG_ARBMODE_DYMPRI 0x0002 780 //--------------------------------// 781 #define TSO1_SVQ_RX_CONFIG_SRAM_SD_EN 0x0080 782 #define TSO1_SVQ_RX_CONFIG_SVQ_FORCE_RESET 0x0100 783 #define TSO1_SVQ_RX_CONFIG_SVQ_MIU_NS 0x0200 784 #define TSO1_SVQ_RX_CONFIG_SVQ_MOBF_INDEX_MASK 0x7C00 785 #define TSO1_SVQ_RX_CONFIG_SVQ_MOBF_INDEX_SHIFT 10 786 #define TSO1_SVQ_RX_CONFIG_SVQ_DYNAMIC_PRI 0x8000 787 788 REG16_TSO SVQ_RX_1_2_PRIORITY; //31 789 #define TSO1_SVQ_RX1_PRIORITY_MASK 0x003F 790 #define TSO1_SVQ_RX1_PRIORITY_SHIFT 0 791 #define TSO1_SVQ_RX2_PRIORITY_MASK 0x3F00 792 #define TSO1_SVQ_RX2_PRIORITY_SHIFT 8 793 794 REG16_TSO SVQ_RX_3_4_PRIORITY; //32 795 #define TSO1_SVQ_RX3_PRIORITY_MASK 0x003F 796 #define TSO1_SVQ_RX3_PRIORITY_SHIFT 0 797 #define TSO1_SVQ_RX4_PRIORITY_MASK 0x3F00 798 #define TSO1_SVQ_RX4_PRIORITY_SHIFT 8 799 800 REG16_TSO SVQ_RX_5_6_PRIORITY; //33 801 #define TSO1_SVQ_RX5_PRIORITY_MASK 0x003F 802 #define TSO1_SVQ_RX5_PRIORITY_SHIFT 0 803 #define TSO1_SVQ_RX6_PRIORITY_MASK 0x3F00 804 #define TSO1_SVQ_RX6_PRIORITY_SHIFT 8 805 806 REG32_TSO SVQ_STATUS; //34~35 807 //----- for TV comaptibility -----// 808 #define TSO_SVQ_STS_MASK 0x000F 809 #define TSO_SVQ1_STS_SHIFT 0 810 #define TSO_SVQ2_STS_SHIFT 4 811 #define TSO_SVQ3_STS_SHIFT 8 812 #define TSO_SVQ4_STS_SHIFT 12 813 #define TSO_SVQ5_STS_SHIFT 16 814 #define TSO_SVQ6_STS_SHIFT 20 815 #define TSO_SVQ_STS_EVER_FULL 0x0001 816 #define TSO_SVQ_STS_EVER_OVF 0x0002 817 #define TSO_SVQ_STS_EMPTY 0x0004 818 #define TSO_SVQ_STS_BUSY 0x0008 819 //--------------------------------// 820 #define TSO1_SVQ1_OVERFLOW_INT 0x01000000 821 #define TSO1_SVQ2_OVERFLOW_INT 0x02000000 822 #define TSO1_SVQ3_OVERFLOW_INT 0x04000000 823 #define TSO1_SVQ4_OVERFLOW_INT 0x08000000 824 #define TSO1_SVQ5_OVERFLOW_INT 0x10000000 825 #define TSO1_SVQ6_OVERFLOW_INT 0x20000000 826 827 REG32_TSO SVQ_STATUS2; //36~37 828 #define TSO1_SVQ1_TX_WATER_LEVEL_MASK 0x00000003 829 #define TSO1_SVQ1_TX_WATER_LEVEL_SHIFT 0 830 #define TSO1_SVQ1_TX_FULL_MASK 0x00000004 831 #define TSO1_SVQ1_TX_FULL_SHIFT 2 832 #define TSO1_SVQ1_TX_EMPTY_MASK 0x00000008 833 #define TSO1_SVQ1_TX_EMPTY_SHIFT 3 834 #define TSO1_SVQ2_TX_WATER_LEVEL_MASK 0x00000030 835 #define TSO1_SVQ2_TX_WATER_LEVEL_SHIFT 4 836 #define TSO1_SVQ2_TX_FULL_MASK 0x00000040 837 #define TSO1_SVQ2_TX_FULL_SHIFT 6 838 #define TSO1_SVQ2_TX_EMPTY_MASK 0x00000080 839 #define TSO1_SVQ2_TX_EMPTY_SHIFT 7 840 #define TSO1_SVQ3_TX_WATER_LEVEL_MASK 0x00000300 841 #define TSO1_SVQ3_TX_WATER_LEVEL_SHIFT 8 842 #define TSO1_SVQ3_TX_FULL_MASK 0x00000400 843 #define TSO1_SVQ3_TX_FULL_SHIFT 10 844 #define TSO1_SVQ3_TX_EMPTY_MASK 0x00000800 845 #define TSO1_SVQ3_TX_EMPTY_SHIFT 11 846 #define TSO1_SVQ4_TX_WATER_LEVEL_MASK 0x00003000 847 #define TSO1_SVQ4_TX_WATER_LEVEL_SHIFT 12 848 #define TSO1_SVQ4_TX_FULL_MASK 0x00004000 849 #define TSO1_SVQ4_TX_FULL_SHIFT 14 850 #define TSO1_SVQ4_TX_EMPTY_MASK 0x00008000 851 #define TSO1_SVQ4_TX_EMPTY_SHIFT 15 852 #define TSO1_SVQ5_TX_WATER_LEVEL_MASK 0x00030000 853 #define TSO1_SVQ5_TX_WATER_LEVEL_SHIFT 16 854 #define TSO1_SVQ5_TX_FULL_MASK 0x00040000 855 #define TSO1_SVQ5_TX_FULL_SHIFT 18 856 #define TSO1_SVQ5_TX_EMPTY_MASK 0x00080000 857 #define TSO1_SVQ5_TX_EMPTY_SHIFT 19 858 #define TSO1_SVQ6_TX_WATER_LEVEL_MASK 0x00300000 859 #define TSO1_SVQ6_TX_WATER_LEVEL_SHIFT 20 860 #define TSO1_SVQ6_TX_FULL_MASK 0x00400000 861 #define TSO1_SVQ6_TX_FULL_SHIFT 22 862 #define TSO1_SVQ6_TX_EMPTY_MASK 0x00800000 863 #define TSO1_SVQ6_TX_EMPTY_SHIFT 23 864 865 REG32_TSO DELTA; //38~39 866 867 REG16_TSO DELTA_CONFIG; //3a 868 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_MASK 0x0007 869 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_SHIFT 0 870 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_1 1 871 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_2 2 872 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_3 3 873 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_4 4 874 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_5 5 875 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_6 6 876 #define TSO1_DELTA_CONFIG_DELTA_CLR 0x0008 877 #define TSO1_DELTA_CONFIG_MAX_ID_MASK 0x0070 878 #define TSO1_DELTA_CONFIG_MAX_ID_SHIFT 8 879 880 REG16_TSO REG_TSO1_CFG3B_52[24]; //3b~52 881 REG16_TSO REG_TSO_MIU_SEL_1; //53 882 #define REG_MIU_SEL_SVQTX1_MASK 0x0003 883 #define REG_MIU_SEL_SVQTX1_SHIFT 0 884 #define REG_MIU_SEL_SVQTX2_MASK 0x000C 885 #define REG_MIU_SEL_SVQTX2_SHIFT 2 886 #define REG_MIU_SEL_SVQTX3_MASK 0x0030 887 #define REG_MIU_SEL_SVQTX3_SHIFT 4 888 #define REG_MIU_SEL_SVQTX4_MASK 0x00C0 889 #define REG_MIU_SEL_SVQTX4_SHIFT 6 890 #define REG_MIU_SEL_SVQTX5_MASK 0x0300 891 #define REG_MIU_SEL_SVQTX5_SHIFT 8 892 #define REG_MIU_SEL_SVQTX6_MASK 0x0C00 893 #define REG_MIU_SEL_SVQTX6_SHIFT 10 894 #define REG_MIU_SEL_SVQRX_MASK 0x300 895 #define REG_MIU_SEL_SVQRX_SHIFT 12 896 #define REG_MIU_SEL_CH5FILEIN_MASK 0xC000 897 #define REG_MIU_SEL_CH5FILEIN_SHIFT 14 898 REG16_TSO REG_TSO_MIU_SEL_2; //54 899 #define REG_MIU_SEL_CH6FILEIN_MASK 0x0003 900 #define REG_MIU_SEL_CH6FILEIN_SHIFT 0 901 } REG_Ctrl_TSO1; 902 903 904 //TSO2 905 typedef struct _REG_Ctrl_TSO2 906 { 907 //---------------------------------------------- 908 // 0xBF802A00 MIPS direct access 909 //---------------------------------------------- 910 911 REG16_TSO REG_TSO2_PVR1_CONFIR1; //00 912 #define TSO2_REG_PVR1_REG_PINGPONG_EN 0x0001 913 #define TSO2_REG_PVR1_STR2MI_EN 0x0002 914 #define TSO2_REG_PVR1_STR2MI_RST_WADR 0x0004 915 #define TSO2_REG_PVR1_STR2MI_PARSE 0x0008 916 #define TSO2_REG_PVR1_PKT192_EN 0x0010 917 #define TSO2_REG_PVR1_BURST_LEN_MASK 0x0060 918 #define TSO2_REG_PVR1_BURST_LEN_SHIFT 5 919 #define TSO2_REG_PVR1_LPCR1_WLD 0x0080 920 #define TSO2_REG_PVR1_PVR_ALIGN_EN 0x0100 921 #define TSO2_REG_PVR1_STR2MI_DSWAP 0x0200 922 #define TSO2_REG_PVR1_STR2MI_BT_ORDER 0x0400 923 #define TSO2_REG_REC_DATA_INV_EN 0x0800 924 #define TSO2_REG_PVR1_BLOCK_DIS 0x1000 925 #define TSO2_REG_PID_BYPASS_REC 0x2000 926 #define TSO2_REG_REC_ALL 0x4000 927 #define TSO2_REG_PVR1_LPCR1_RLD 0x8000 928 929 REG32_TSO REG_TSO2_PVR1_STR2MI_HEAD; //01~02 930 REG32_TSO REG_TSO2_PVR1_STR2MI_MID; //03~04 931 REG32_TSO REG_TSO2_PVR1_STR2MI_TAIL; //05~06 932 REG32_TSO REG_TSO2_PVR1_STR2MI_HEAD2; //07~08 933 REG32_TSO REG_TSO2_PVR1_STR2MI_MID2; //09~0A 934 REG32_TSO REG_TSO2_PVR1_STR2MI_TAIL2; //0B~0C 935 936 REG16_TSO REG_TSO2_PVR1_CONFIR2; //0D 937 #define TSO2_REG_PVR1_SRAM_SD_EN 0x0001 938 #define TSO2_REG_PVR1_FLUSH_DATA 0x0002 939 #define TSO2_REG_PVR1_STR2MI_WP_LD 0x0004 940 #define TSO2_REG_PVR1_CLR 0x0008 941 #define TSO2_REG_PVR1_DMA_FLUSH_EN 0x0010 942 #define TSO2_REG_PVR1_FORCE_SYNC_EN 0x0020 943 #define TSO2_REG_PVR1_RECORD_DIS_SYNC_EN 0x0040 944 #define TSO2_REG_PVR1_MIU_HIGHPRI 0x0080 945 #define TSO2_REG_PVR1_RECORD_ALL_OLD 0x0100 946 #define TSO2_REG_PVR1_WRITE_POINTER_TO_NEXT_ADDR_EN 0x0200 947 #define TSO2_REG_PVR1_DMAW_PROTECT_EN 0x0400 948 #define TSO2_REG_PVR1_CLR_NO_HIT_INT 0x0800 949 950 REG32_TSO REG_TSO2_PVR1_DMAW_LBUD; //0E~0F 951 REG32_TSO REG_TSO2_PVR1_DMAW_UBUD; //10~11 952 REG32_TSO REG_TSO2_PVR1_LPCR1; //12~13 953 954 REG16_TSO REG_TSO2_CFG14; //14 955 #define TSO2_REG_PVR1_SRC_MASK 0x0003 //01 : from svq merge stream, 10: MMT function 956 #define TSO2_REG_CLK_27M_90K 0x0004 // 0 : 90k, 1: 27M 957 958 REG16_TSO REG_TSO2_CFG15_1F[11]; //15~1F 959 960 REG16_TSO REG_TSO2_CFG20; //20 961 #define TSO2_REG_SYNC_RISING_DETECT 0x0001 962 #define TSO2_REG_VALID_FALLING_DETECT_INV 0x0002 963 #define TSO2_REG_FROCE_SYNCBYTE 0x0004 964 #define TSO2_REG_P_SEL 0x0008 965 #define TSO2_REG_EXT_SYNC_SEL 0x0010 966 #define TSO2_REG_DATA_CHK_2T 0x0020 967 #define TSO2_REG_SERIAL_EXT_SYNC_1T 0x0040 968 #define TSO2_REG_TSIF_EVER_OVERFLOW_CLR 0x0080 969 #define TSO2_REG_PKT_CHK_SIZE_MASK 0xFF00 970 #define TSO2_REG_PKT_CHK_SIZE_SHIFT 8 971 REG16_TSO REG_TSO2_MMT_CFG21; //21 972 #define TSO2_REG_TSO_MMT_EN 0x0001 973 #define TSO2_REG_3_WIRE_EN_MMT 0x0002 974 #define TSO2_REG_SW_RST_TS_MMT 0x0004 975 #define TSO2_REG_LOCKED_PKT_CNT_MMT_LOAD 0x0008 976 #define TSO2_REG_LOCKED_PKT_CNT_MMT_CLR 0x0010 977 REG32_TSO REG_TSO2_PVR1_DMAW_WADDR_ERR; //22~23 978 REG16_TSO REG_TSO2_MOBF_CFG24; //24 979 REG32_TSO REG_TSO2_STR2MI_WADR_R; //25~26 980 REG16_TSO REG_TSO2_CFG27; //27 981 #define TSO2_REG_TSIF_EVER_OVERFLOW_FLAG 0x0001 982 #define TSO2_REG_FLUSH_DATA_PVR1_STATUS 0x0002 983 #define TSO2_REG_PVR1_FIFO_STATUS_MASK 0x003C 984 #define TSO2_REG_PVR1_FIFO_STATUS_SHIFT 2 985 986 REG16_TSO REG_TSO2_CFG28_2F[8]; //28~2F 987 988 REG16_TSO REG_TSO2_PCR_CFG30; //30 989 #define TSO2_REG_TEI_SKIP_PKT_PCR1 0x0001 990 #define TSO2_REG_PCR1_RESET 0x0002 991 #define TSO2_REG_PCR1_READ 0x0004 992 #define TSO2_REG_TEI_SKIP_PKT_PCR2 0x0010 993 #define TSO2_REG_PCR2_RESET 0x0020 994 #define TSO2_REG_PCR2_READ 0x0040 995 #define TSO2_REG_TEI_SKIP_PKT_PCR3 0x0100 996 #define TSO2_REG_PCR3_RESET 0x0200 997 #define TSO2_REG_PCR3_READ 0x0400 998 #define TSO2_REG_TEI_SKIP_PKT_PCR4 0x1000 999 #define TSO2_REG_PCR4_RESET 0x2000 1000 #define TSO2_REG_PCR4_READ 0x4000 1001 REG16_TSO REG_TSO2_PCR2_CFG31; //31 1002 #define TSO2_REG_TEI_SKIP_PKT_PCR5 0x0001 1003 #define TSO2_REG_PCR5_RESET 0x0002 1004 #define TSO2_REG_PCR5_READ 0x0004 1005 #define TSO2_REG_TEI_SKIP_PKT_PCR6 0x0010 1006 #define TSO2_REG_PCR6_RESET 0x0020 1007 #define TSO2_REG_PCR6_READ 0x0040 1008 1009 REG16_TSO REG_TSO2_PIDFLT_PCR_CFG32_37[6]; //32~37 1010 #define TSO2_REG_PIDFLT_PCR_PID_MASK 0x1FFF 1011 #define TSO2_REG_PIDFLT_PCR_ENPCR 0x8000 1012 1013 REG32_TSO REG_TSO2_PCR1_LOW32_CFG38_39; //38~39 1014 REG16_TSO REG_TSO2_PCR1_VAILD_CFG3A; //3A 1015 #define TSO2_REG_PCR1_VALID_33_HIGH 0x0001 1016 #define TSO2_REG_PCR1_VALID_EXT_MASK 0x03FE 1017 #define TSO2_REG_PCR1_VALID_EXT_SHIFT 1 1018 1019 REG32_TSO REG_TSO2_PCR2_LOW32_CFG3B_3C; //3B~3C 1020 REG16_TSO REG_TSO2_PCR2_VAILD_CFG3D; //3D 1021 #define TSO2_REG_PCR2_VALID_33_HIGH 0x0001 1022 #define TSO2_REG_PCR2_VALID_EXT_MASK 0x03FE 1023 #define TSO2_REG_PCR2_VALID_EXT_SHIFT 1 1024 1025 REG32_TSO REG_TSO2_PCR3_LOW32_CFG3E_3F; //3E~3F 1026 REG16_TSO REG_TSO2_PCR3_VAILD_CFG40; //40 1027 #define TSO2_REG_PCR3_VALID_33_HIGH 0x0001 1028 #define TSO2_REG_PCR3_VALID_EXT_MASK 0x03FE 1029 #define TSO2_REG_PCR3_VALID_EXT_SHIFT 1 1030 1031 REG32_TSO REG_TSO2_PCR4_LOW32_CFG41_42; //41~42 1032 REG16_TSO REG_TSO2_PCR4_VAILD_CFG43; //43 1033 #define TSO2_REG_PCR4_VALID_33_HIGH 0x0001 1034 #define TSO2_REG_PCR4_VALID_EXT_MASK 0x03FE 1035 #define TSO2_REG_PCR4_VALID_EXT_SHIFT 1 1036 1037 REG32_TSO REG_TSO2_PCR5_LOW32_CFG44_45; //44~45 1038 REG16_TSO REG_TSO2_PCR5_VAILD_CFG46; //46 1039 #define TSO2_REG_PCR5_VALID_33_HIGH 0x0001 1040 #define TSO2_REG_PCR5_VALID_EXT_MASK 0x03FE 1041 #define TSO2_REG_PCR5_VALID_EXT_SHIFT 1 1042 1043 REG32_TSO REG_TSO2_PCR6_LOW32_CFG47_48; //47~48 1044 REG16_TSO REG_TSO2_PCR6_VAILD_CFG49; //49 1045 #define TSO2_REG_PCR6_VALID_33_HIGH 0x0001 1046 #define TSO2_REG_PCR6_VALID_EXT_MASK 0x03FE 1047 #define TSO2_REG_PCR6_VALID_EXT_SHIFT 1 1048 1049 REG16_TSO REG_TSO2_CFG4A_4F[6]; //4A~4F 1050 REG16_TSO REG_TSO2_SG_PDFLT_CONFIG0_CFG50; //50 1051 #define TSO2_REG_SG_PD_FLT_DISABLE 0x0001 1052 #define TSO2_REG_PDFLT_REC_ALL 0x0010 1053 #define TSO2_REG_PDFLT_REC_NULL 0x0020 1054 #define TSO2_REG_PDFLT_OVERFLOW_INT_EN 0x0040 1055 #define TSO2_REG_PDFLT_OVERFLOW_CLR 0x0080 1056 #define TSO2_REG_SKIP_TEI_PKT 0x0200 1057 1058 REG32_TSO REG_TSO2_SG_PDFLT_SVID_EN[2]; //51~54 1059 REG16_TSO REG_TSO2_SG_PDTABLE_RDATA_CFG55; //55 1060 REG16_TSO REG_TSO2_SG_PD_CFG56; //56 1061 #define TSO2_REG_SG_PDTABLE_RDATA_H_MASK 0x003F 1062 #define TSO2_REG_READ_SG_PDFLT_EVER_OVERFLOW 0x0100 1063 REG16_TSO REG_TSO2_CFG57_5F[9]; //57~5F 1064 REG16_TSO REG_TSO2_PKT_TIME_THRESHOLD_CFG60; //60 1065 REG16_TSO REG_TSO2_DATA_TRACING_CONFIG_CFG61; //61 1066 #define TSO2_REG_DATA_TRACING_ST_CLR 0x0001 // 1: data rate trace status clear 1067 #define TSO2_REG_DATA_TRACING_ST_LD 0x0002 // 1: load latest info 0: keep old info 1068 #define TSO2_REG_MAX_MIN_EVER_CURRENT 0x0004 // 1: max/min ever, 0: max/min in current sample period 1069 #define TSO2_REG_DATA_RATE_SRC_SEL_MASK 0x00F0 1070 #define TSO2_REG_DATA_RATE_SRC_SEL_SHIFT 4 1071 #define TSO2_REG_DATA_TRACING_SHIFT_VAL_MASK 0x0F00 1072 #define TSO2_REG_DATA_TRACING_SHIFT_VAL_SHIFT 8 1073 REG16_TSO REG_TSO2_REG_AVG_PKT_TIME_CFG62; //62 1074 REG16_TSO REG_TSO2_MIN_PKT_TIME_CFG63; //63 1075 REG16_TSO REG_TSO2_MAX_PKT_TIME_CFG64; //64 1076 1077 } REG_Ctrl_TSO2; 1078 1079 1080 #endif // _TSO_REG_H_ 1081