1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSO.h 98 // Description: TS I/O Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSO_REG_H_ 103 #define _TSO_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 //@TODO check ENG PIDFLT TSIF number 138 139 #define TSO_ENGINE_NUM (2) 140 #define TSO_PIDFLT_NUM (512) 141 #define TSO_REP_PIDFLT_NUM (16) 142 #define TSO_FILE_IF_NUM (2) 143 #define TSO_TSIF_NUM (6) 144 145 #define TSO_PIDFLT_NUM_ALL TSO_PIDFLT_NUM 146 147 #define TSO_PID_NULL (0x1FFF) 148 #define TSO_MIU_BUS (4) 149 #define TSO_SVQ_UNIT_SIZE (208) 150 151 //------------------------------------------------------------------------------------------------- 152 // Harware Capability 153 //------------------------------------------------------------------------------------------------- 154 #define TSO_CLKIN_TS0 0x00 155 #define TSO_CLKIN_TS1 0x01 156 #define TSO_CLKIN_TS2 0x02 157 #define TSO_CLKIN_TS3 0x03 158 #define TSO_CLKIN_TS4 0x04 159 #define TSO_CLKIN_TS5 0x05 160 #define TSO_CLKIN_TS6 0x06 161 #define TSO_CLKIN_TSO0_OUT_P 0x07 162 #define TSO_CLKIN_DMD 0xFFFF //not supported 163 164 //------------------------------------------------------------------------------------------------- 165 // Type and Structure 166 //------------------------------------------------------------------------------------------------- 167 #define REG_PIDFLT_BASE (0x210000UL) 168 #define TSO_PIDFLT_PID_MASK (0x1FFF) 169 #define TSO_PIDFLT_IN_MASK (0x7) 170 #define TSO_PIDFLT_IN_SHIFT (13) 171 172 #define REG_CTRL_BASE_TSO (0xE0C00UL) // 0x1706 173 #define REG_CTRL_BASE_TSO1 (0xC2400UL) // 0x1612 174 #define REG_CTRL_BASE_TSO2 (0xA7200UL) // 0x1539 175 #define REG_CTRL_BASE_TSO3 (0xE3A00UL) // 0x171D 176 #define REG_CTRL_BASE_TSO4 (0x42A00UL) // 0x1215 177 178 typedef struct _REG32_TSO 179 { 180 volatile MS_U16 L; 181 volatile MS_U16 empty_L; 182 volatile MS_U16 H; 183 volatile MS_U16 empty_H; 184 } REG32_TSO; 185 186 typedef struct _REG16_TSO 187 { 188 volatile MS_U16 data; 189 volatile MS_U16 _resv; 190 } REG16_TSO; 191 192 //TSO0 193 typedef struct _REG_Ctrl_TSO 194 { 195 //---------------------------------------------- 196 // 0xBF802A00 MIPS direct access 197 //---------------------------------------------- 198 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 199 REG16_TSO SW_RSTZ; //00 200 #define TSO_SW_RSTZ 0x0001 201 #define TSO_SW_RST_CLK_STAMP 0x0002 202 #define TSO_SW_RST_CMDQ1 0x0100 203 #define TSO_SW_RST_WB1 0x0200 204 #define TSO_SW_RST_WB_DMA1 0x0400 205 #define TSO_SW_RST_TS_FIN1 0x0800 206 #define TSO_SW_RST_CMDQ 0x1000 207 #define TSO_SW_RST_WB 0x2000 208 #define TSO_SW_RST_WB_DMA 0x4000 209 #define TSO_SW_RST_FIN 0x8000 210 #define TSO_SW_RST_ALL 0xF002 211 #define TSO_SW_RST_ALL1 0x0F02 212 213 214 REG16_TSO SW_RSTZ1; //01 215 #define TSO_SW_RST_CHANNEL_IF1 0x0001 216 #define TSO_SW_RST_CHANNEL_IF2 0x0002 217 #define TSO_SW_RST_CHANNEL_IF3 0x0004 218 #define TSO_SW_RST_CHANNEL_IF4 0x0008 219 #define TSO_SW_RST_CHANNEL_IF5 0x0010 220 #define TSO_SW_RST_CHANNEL_IF6 0x0020 221 222 REG16_TSO CFG_TSO_02; 223 REG16_TSO PDTABLE_RDATA_SYNCID; //03 224 #define TSO_PDTABLE_RDATA_SYNCID_MASK 0xFF00 225 #define TSO_PDTABLE_RDATA_SYNCID_SHIFT 8 226 227 REG16_TSO CHANNEL0_IF1_CONFIG0; //04 228 #define TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF //for internal sync 229 #define TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 230 #define TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 231 #define TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 232 233 REG16_TSO CHANNEL0_IF1_CONFIG1; //05 234 #define TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK 0x00FF 235 #define TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_SHIFT 0 236 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 237 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_SHIFT 8 238 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 239 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_SHIFT 11 240 241 REG16_TSO CHANNEL0_IF1_CONFIG2; //06 242 //----- for TV comaptibility -----// 243 #define TSO_CHCFG_P_SEL 0x0001 244 #define TSO_CHCFG_EXT_SYNC_SEL 0x0002 245 #define TSO_CHCFG_TS_SIN_C0 0x0004 246 #define TSO_CHCFG_TS_SIN_C1 0x0008 247 #define TSO_CHCFG_PIDFLT_REC_ALL 0x0010 248 #define TSO_CHCFG_PIDFLT_REC_NULL 0x0020 249 #define TSO_CHCFG_PIDFLT_OVF_INT_EN 0x0040 250 #define TSO_CHCFG_PIDFLT_OVF_CLR 0x0080 251 #define TSO_CHCFG_FORCE_SYNC_BYTE 0x0100 252 #define TSO_CHCFG_SKIP_TEI_PKT 0x0200 253 #define TSO_CHCFG_DIS_LOCKED_PKT_CNT 0x0400 254 #define TSO_CHCFG_CLR_LOCKED_PKT_CNT 0x0800 255 #define TSO_CHCFG_TRC_CLK_LD_DIS 0x1000 256 #define TSO_CHCFG_TRC_CLK_CLR 0x2000 257 #define TSO_CHCFG_SRC_ID_FLT_EN 0x4000 258 #define TSO_CHCFG_PKT_CVT_OVERFLOW1_CLR 0x8000 259 260 //--------------------------------// 261 262 REG16_TSO CHANNEL0_IF1_CONFIG3; //07 reserved 263 264 REG16_TSO CHANNEL0_IF2_CONFIG0; //08 265 #define TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 266 #define TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 267 #define TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 268 #define TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 269 270 REG16_TSO CHANNEL0_IF2_CONFIG1; //09 271 #define TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK 0x00FF 272 #define TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_SHIFT 0 273 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 274 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_SHIFT 8 275 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 276 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_SHIFT 11 277 278 REG16_TSO CHANNEL0_IF2_CONFIG2; //0a 279 #define TSO_CHANNEL0_IF2_CONFIG2_P_SEL 0x0001 280 #define TSO_CHANNEL0_IF2_CONFIG2_EXT_SYNC_SEL 0x0002 281 #define TSO_CHANNEL0_IF2_CONFIG2_TS_SIN_C0 0x0004 282 #define TSO_CHANNEL0_IF2_CONFIG2_TS_SIN_C1 0x0008 283 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL 0x0010 284 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_NULL 0x0020 285 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 286 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 287 #define TSO_CHANNEL0_IF2_CONFIG2_FORCE_SYNC_BYTE 0x0100 288 #define TSO_CHANNEL0_IF2_CONFIG2_SKIP_TEI_PKT 0x0200 289 #define TSO_CHANNEL0_IF2_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 290 #define TSO_CHANNEL0_IF2_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 291 #define TSO_CHANNEL0_IF2_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 292 #define TSO_CHANNEL0_IF2_CONFIG2_TRACING_CLOCK_CLR 0x2000 293 #define TSO_CHANNEL0_IF2_CONFIG2_SRC_ID_FLT_EN 0x4000 294 #define TSO_CHANNEL0_IF2_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 295 296 REG16_TSO CHANNEL0_IF2_CONFIG3; //0b reserved 297 298 REG16_TSO CHANNEL0_IF3_CONFIG0; //0c 299 #define TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 300 #define TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 301 #define TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 302 #define TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 303 304 REG16_TSO CHANNEL0_IF3_CONFIG1; //0d 305 #define TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK 0x00FF 306 #define TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_SHIFT 0 307 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 308 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_SHIFT 8 309 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 310 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_SHIFT 11 311 312 REG16_TSO CHANNEL0_IF3_CONFIG2; //0e 313 #define TSO_CHANNEL0_IF3_CONFIG2_P_SEL 0x0001 314 #define TSO_CHANNEL0_IF3_CONFIG2_EXT_SYNC_SEL 0x0002 315 #define TSO_CHANNEL0_IF3_CONFIG2_TS_SIN_C0 0x0004 316 #define TSO_CHANNEL0_IF3_CONFIG2_TS_SIN_C1 0x0008 317 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL 0x0010 318 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_NULL 0x0020 319 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 320 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 321 #define TSO_CHANNEL0_IF3_CONFIG2_FORCE_SYNC_BYTE 0x0100 322 #define TSO_CHANNEL0_IF3_CONFIG2_SKIP_TEI_PKT 0x0200 323 #define TSO_CHANNEL0_IF3_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 324 #define TSO_CHANNEL0_IF3_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 325 #define TSO_CHANNEL0_IF3_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 326 #define TSO_CHANNEL0_IF3_CONFIG2_TRACING_CLOCK_CLR 0x2000 327 #define TSO_CHANNEL0_IF3_CONFIG2_SRC_ID_FLT_EN 0x4000 328 #define TSO_CHANNEL0_IF3_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 329 330 REG16_TSO CHANNEL0_IF3_CONFIG3; //0f reserved 331 332 REG16_TSO CHANNEL0_IF4_CONFIG0; //10 333 #define TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 334 #define TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 335 #define TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 336 #define TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 337 338 REG16_TSO CHANNEL0_IF4_CONFIG1; //11 339 #define TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK 0x00FF 340 #define TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_SHIFT 0 341 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 342 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_SHIFT 8 343 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 344 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_SHIFT 11 345 346 REG16_TSO CHANNEL0_IF4_CONFIG2; //12 347 #define TSO_CHANNEL0_IF4_CONFIG2_P_SEL 0x0001 348 #define TSO_CHANNEL0_IF4_CONFIG2_EXT_SYNC_SEL 0x0002 349 #define TSO_CHANNEL0_IF4_CONFIG2_TS_SIN_C0 0x0004 350 #define TSO_CHANNEL0_IF4_CONFIG2_TS_SIN_C1 0x0008 351 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL 0x0010 352 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_NULL 0x0020 353 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 354 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 355 #define TSO_CHANNEL0_IF4_CONFIG2_FORCE_SYNC_BYTE 0x0100 356 #define TSO_CHANNEL0_IF4_CONFIG2_SKIP_TEI_PKT 0x0200 357 #define TSO_CHANNEL0_IF4_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 358 #define TSO_CHANNEL0_IF4_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 359 #define TSO_CHANNEL0_IF4_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 360 #define TSO_CHANNEL0_IF4_CONFIG2_TRACING_CLOCK_CLR 0x2000 361 #define TSO_CHANNEL0_IF4_CONFIG2_SRC_ID_FLT_EN 0x4000 362 #define TSO_CHANNEL0_IF4_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 363 364 REG16_TSO CHANNEL0_IF4_CONFIG3; //13 reserved 365 366 REG16_TSO CHANNEL0_IF5_CONFIG0; //14 367 #define TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 368 #define TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 369 #define TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 370 #define TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 371 372 REG16_TSO CHANNEL0_IF5_CONFIG1; //15 373 #define TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK 0x00FF 374 #define TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_SHIFT 0 375 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 376 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT 8 377 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 378 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_SHIFT 11 379 380 REG16_TSO CHANNEL0_IF5_CONFIG2; //16 381 #define TSO_CHANNEL0_IF5_CONFIG2_P_SEL 0x0001 382 #define TSO_CHANNEL0_IF5_CONFIG2_EXT_SYNC_SEL 0x0002 383 #define TSO_CHANNEL0_IF5_CONFIG2_TS_SIN_C0 0x0004 384 #define TSO_CHANNEL0_IF5_CONFIG2_TS_SIN_C1 0x0008 385 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL 0x0010 386 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_NULL 0x0020 387 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 388 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 389 #define TSO_CHANNEL0_IF5_CONFIG2_FORCE_SYNC_BYTE 0x0100 390 #define TSO_CHANNEL0_IF5_CONFIG2_SKIP_TEI_PKT 0x0200 391 #define TSO_CHANNEL0_IF5_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 392 #define TSO_CHANNEL0_IF5_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 393 #define TSO_CHANNEL0_IF5_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 394 #define TSO_CHANNEL0_IF5_CONFIG2_TRACING_CLOCK_CLR 0x2000 395 #define TSO_CHANNEL0_IF5_CONFIG2_SRC_ID_FLT_EN 0x4000 396 #define TSO_CHANNEL0_IF5_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 397 398 REG16_TSO CHANNEL0_IF5_CONFIG3; //17 reserved 399 400 REG16_TSO CHANNEL0_IF6_CONFIG0; //18 401 #define TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 402 #define TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 403 #define TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 404 #define TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 405 406 REG16_TSO CHANNEL0_IF6_CONFIG1; //19 407 #define TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK 0x00FF 408 #define TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_SHIFT 0 409 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 410 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_SHIFT 8 411 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 412 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_SHIFT 11 413 414 REG16_TSO CHANNEL0_IF6_CONFIG2; //1a 415 #define TSO_CHANNEL0_IF6_CONFIG2_P_SEL 0x0001 416 #define TSO_CHANNEL0_IF6_CONFIG2_EXT_SYNC_SEL 0x0002 417 #define TSO_CHANNEL0_IF6_CONFIG2_TS_SIN_C0 0x0004 418 #define TSO_CHANNEL0_IF6_CONFIG2_TS_SIN_C1 0x0008 419 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL 0x0010 420 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_NULL 0x0020 421 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 422 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 423 #define TSO_CHANNEL0_IF6_CONFIG2_FORCE_SYNC_BYTE 0x0100 424 #define TSO_CHANNEL0_IF6_CONFIG2_SKIP_TEI_PKT 0x0200 425 #define TSO_CHANNEL0_IF6_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 426 #define TSO_CHANNEL0_IF6_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 427 #define TSO_CHANNEL0_IF6_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 428 #define TSO_CHANNEL0_IF6_CONFIG2_TRACING_CLOCK_CLR 0x2000 429 #define TSO_CHANNEL0_IF6_CONFIG2_SRC_ID_FLT_EN 0x4000 430 #define TSO_CHANNEL0_IF6_CONFIG2_PKT_CVT_OVERFLOW1_CLR 0x8000 431 432 REG16_TSO CHANNEL0_IF6_CONFIG3; //1b reserved 433 434 REG16_TSO TSO_CONFIG0; //1c 435 #define TSO_CONFIG0_S2P_EN 0x0001 436 #define TSO_CONFIG0_S2P_TS_SIN_C0 0x0002 437 #define TSO_CONFIG0_S2P_TS_SIN_C1 0x0004 438 #define TSO_CONFIG0_S2P_3WIRE_MODE 0x0008 439 #define TSO_CONFIG0_BYPASS_S2P 0x0010 440 #define TSO_CONFIG0_S2P1_EN 0x0100 441 #define TSO_CONFIG0_S2P1_TS_SIN_C0 0x0200 442 #define TSO_CONFIG0_S2P1_TS_SIN_C1 0x0400 443 #define TSO_CONFIG0_S2P1_3WIRE_MODE 0x0800 444 #define TSO_CONFIG0_BYPASS_S2P1 0x1000 445 446 REG16_TSO TSO_CONFIG1; //1d 447 //----- for TV comaptibility -----// 448 #define TSO_CFG1_TSO_OUT_EN 0x0001 449 #define TSO_CFG1_TSO_TSIF1_EN 0x0002 450 #define TSO_CFG1_TSO_TSIF2_EN 0x0004 451 #define TSO_CFG1_TSO_TSIF3_EN 0x0008 452 #define TSO_CFG1_TSO_TSIF4_EN 0x0010 453 #define TSO_CFG1_TSO_TSIF5_EN 0x0020 454 #define TSO_CFG1_TSO_TSIF6_EN 0x0040 455 //--------------------------------// 456 #define TSO_CONFIG1_PAUSE_OPIF 0x0080 457 #define TSO_CONFIG1_TURN_OFF_MCM 0x0100 458 #define TSO_CONFIG1_CLOCK_TRACING_SEL_MASK 0x0E00 459 #define TSO_CONFIG1_CLOCK_TRACING_SEL_SHIFT 9 460 #define TSO_CONFIG1_SERIAL_OUT_EN 0x1000 461 #define TSO_CONFIG1_PKT_LOCK_CLR 0x2000 462 #define TSO_CONFIG1_PKT_NULL_EN 0x4000 463 //----- for TV comaptibility -----// 464 #define TSO_CFG1_PKT_PARAM_LD 0x8000 465 //--------------------------------// 466 467 REG16_TSO TSO_CONFIG2; //1e 468 #define TSO_CONFIG2_VALID_BYTE_CNT_MASK 0x00FF 469 #define TSO_CONFIG2_VALID_BYTE_CNT_SHIFT 0 470 #define TSO_CONFIG2_INVALID_BYTE_CNT_MASK 0xFF00 471 #define TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT 8 472 473 REG16_TSO TSO_CONFIG3; //1f 474 #define TSO_CONFIG3_OPIF_PKT_SIZE_MASK 0xFFFF 475 476 REG32_TSO PIDFLTS[16]; //20~3e PID00~0F 477 //FOR ALL PID 478 #define TSO_PID_ORIGINAL_PID_MASK 0x00001FFF 479 #define TSO_PID_ORIGINAL_PID_SHIFT 0 480 #define TSO_PID_SOURCE_SEL_MASK 0x0000E000 481 #define TSO_PID_SOURCE_SEL_SHIFT 13 482 #define TSO_PID_NEW_PID_MASK 0x1FFF0000 483 #define TSO_PID_NEW_PID_SHIFT 16 484 #define TSO_PID_REPLACE_EN 0x80000000 485 486 REG16_TSO CLR_BYTE_CNT; //40 487 #define TSO_CLR_BYTE_CNT_1 0x0001 488 #define TSO_CLR_BYTE_CNT_2 0x0002 489 #define TSO_CLR_BYTE_CNT_3 0x0004 490 #define TSO_CLR_BYTE_CNT_4 0x0008 491 #define TSO_CLR_BYTE_CNT_5 0x0010 492 #define TSO_CLR_BYTE_CNT_6 0x0020 493 494 REG16_TSO CFG_TSO_41_42[2]; //41~42 495 496 REG16_TSO TSO_CONFIG4; //43 497 #define TSO_CFG4_LOCK_RETURN_SYSTEM_TIMESTAMP 0x0001 498 #define TSO_CFG4_ENABLE_SYS_TIMESTAMP 0x0002 499 #define TSO_CFG4_SET_SYS_TIMESTAMP_TO_HW 0x0004 500 #define TSO_CFG4_TIMESTAMP_BASE 0x0008 //0:90k 1:27m 501 #define TSO_CFG4_PDTABLE_SRAM_SD_EN 0x0010 502 //------------------------------------------------------------------------ 503 #define TSO_CFG4_FIX_TIMESTAMP_RING_BACK_EN 0x0020 504 #define TSO_CFG4_FIX_LPCR_RING_BACK_EN 0x0040 505 #define TSO_CFG4_INIT_TIMESTAMP_RESTART_EN 0x0080 506 //------------------------------------------------------------------------ 507 #define TSO_CFG4_NULL_PKT_ID_MASK 0xFF00 508 #define TSO_CFG4_NULL_PKT_ID_SHIFT 8 509 510 REG16_TSO TSO_CONFIG5; //44 511 #define TSO_CONFIG5_3_WIRE_EN_1 0x0001 512 #define TSO_CONFIG5_3_WIRE_EN_2 0x0002 513 #define TSO_CONFIG5_3_WIRE_EN_3 0x0004 514 #define TSO_CONFIG5_3_WIRE_EN_4 0x0008 515 #define TSO_CONFIG5_3_WIRE_EN_5 0x0010 516 #define TSO_CONFIG5_3_WIRE_EN_6 0x0020 517 #define TSO_CONFIG5_DIS_MIU_RQ 0x0040 518 #define TSO_CONFIG5_FIXED_MIU_REG_FLUSH 0x0080 // fix svq_tx error 519 #define TSO_CONFIG5_EXTEND_ENABLE 0x0100 // fix svq_tx error 520 #define TSO_CONFIG5_REG_VQ_IDLE_CNT_DIS 0x0200 // fix svq_tx error 521 #define TSO_CONFIG5_REG_TSIO_MODE 0x0400 522 #define TSO_CONFIG5_REG_TSIO2OPIF 0x0800 523 #define TSO_CONFIG5_BYPASS_SVQ_FOR_CH1 0x1000 524 #define TSO_CONFIG5_REG_CHECK_VQ_BURST_LEN 0x2000 525 526 REG16_TSO PDTABLE_ADDR_L; //45 ind R/W of L addr to pdtable 527 REG16_TSO PDTABLE_ADDR_H; //46 ind R/W of H addr to pdtable 528 529 REG16_TSO PDTABLE_WDATA_L; //47 ind R/W of L addr to pdtable 530 REG16_TSO PDTABLE_WDATA_H; //48 ind R/W of L addr to pdtable 531 532 REG16_TSO PDTABLE_RDATA; //49 ind of Rdata from pdtable 533 534 REG16_TSO PDTABLE_EN; //4a 535 #define TSO_PDTABLE_W_EN 0x0001//Ind W flag to pdtable 536 #define TSO_PDTABLE_R_EN 0x0002//Ind R flag to pdtable 537 538 #define TSO_PDTABLE_RDATA_H_MASK 0x3F00 // ind of Rdata[21:16] from pdtable 539 540 REG16_TSO TSO_STATUS; //4b 541 #define TSO_STATUS_SVQ_MASK 0x7F00 542 #define TSO_STATUS_SVQ_SHIFT 8 543 #define TSO_STATUS_PDFLT 0x8000 544 545 REG16_TSO FILE_TIMER[2]; //4c ~ 4d 546 547 REG16_TSO TSO_STATUS1; //4e 548 #define TSO_STATUS1_EVEROVERFLOW_TSIF_1 0x0001 549 #define TSO_STATUS1_EVEROVERFLOW_TSIF_2 0x0002 550 #define TSO_STATUS1_EVEROVERFLOW_TSIF_3 0x0004 551 #define TSO_STATUS1_EVEROVERFLOW_TSIF_4 0x0008 552 #define TSO_STATUS1_EVEROVERFLOW_TSIF_5 0x0010 553 #define TSO_STATUS1_EVEROVERFLOW_TSIF_6 0x0020 554 555 REG16_TSO CFG_TSO_4F_5A[12]; //4f~5a 556 557 REG16_TSO TSO_TRACING_HIGH; //5b 558 REG16_TSO TSO_TRACING_LOW; //5c 559 REG16_TSO TSO_TRACING_1T; //5d 560 REG16_TSO TSO_BLOCK_SIZE_DB; //5e 561 REG16_TSO TSO_OPT_SZIE_DB; //5f 562 563 REG32_TSO CFG_TSO_60_63[2]; //60~63 564 REG16_TSO TSO_Filein_Ctrl; //64 565 REG32_TSO CFG_TSO_65_68[2]; //65~68 566 REG16_TSO TSO_Filein_Ctrl1; //69 567 #define TSO_FILEIN_CTRL_MASK 0x0007 568 #define TSO_FILEIN_RSTART 0x0001 569 #define TSO_FILEIN_ABORT 0x0002 570 #define TSO_FILEIN_TRUST 0x0004 571 572 REG16_TSO PKT_CNT_SEL; //6a 573 #define TSO_PKT_CNT_RETURN_SEL_MASK 0x000F 574 #define TSO_PKT_CNT_RETURN_SEL_SHIFT 0 575 #define TSO_PKT_CNT_DBG_LOCKED_PKT_CNT_MASK 0x00F0 576 #define TSO_PKT_CNT_DBG_LOCKED_PKT_CNT_SHIFT 4 577 #define TSO_PKT_CNT_DBG_PKT_CNTT_DBG_MASK 0xFF00 578 #define TSO_PKT_CNT_DBG_PKT_CNTT_DBG_SHIFT 8 579 580 REG16_TSO PKT_CHK_SIZE_FIN; //6b 581 #define TSO_PKT_CHK_SIZE_FIN_MASK 0x00FF 582 #define TSO_PKT_CHK_SIZE_FIN_SHIFT 0 583 #define TSO_PKT_CHK_SIZE_FIN1_MASK 0xFF00 584 #define TSO_PKT_CHK_SIZE_FIN1_SHIFT 8 585 586 REG32_TSO LPCR2_BUF; //6c~6d 587 REG32_TSO LPCR2_BUF1; //6e~6f 588 589 REG32_TSO TIMESTAMP; //70~71 590 REG32_TSO TIMESTAMP1; //72~73 591 592 REG32_TSO TSO2MI_RADDR; //74~75 593 REG32_TSO TSO2MI_RADDR1; //76~77 594 595 REG16_TSO CMD_QUEUE_STATUS; //78 596 #define TSO_CMDQ_SIZE 16 597 #define TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_MASK 0x000F 598 #define TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_SHIFT 0 599 #define TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_MASK 0x0030 600 #define TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_SHIFT 4 601 #define TSO_CMD_QUEUE_STATUS_CMD_FIFO_FULL 0x0040 602 #define TSO_CMD_QUEUE_STATUS_CMD_FIFO_EMPTY 0x0080 603 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_MASK 0x0F00 604 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_SHIFT 8 605 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_MASK 0x3000 606 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_SHIFT 12 607 #define TSO_CMD_QUEUE_STATUS1_CMD_FIFO_FULL 0x4000 608 #define TSO_CMD_QUEUE_STATUS1_CMD_FIFO_EMPTY 0x8000 609 610 REG16_TSO TSO_FILE_CONFIG; //79 611 #define TSO_FILE_CONFIG_TSO2MI_RPRIORITY 0x0001 612 #define TSO_FILE_CONFIG_MEM_TS_DATA_ENDIAN 0x0002 613 #define TSO_FILE_CONFIG_MEM_TS_W_ORDER 0x0004 614 #define TSO_FILE_CONFIG_LPCR2_WLD 0x0008 615 #define TSO_FILE_CONFIG_LPCR2_LOAD 0x0010 616 #define TSO_FILE_CONFIG_DIS_MIU_RQ 0x0020 617 #define TSO_FILE_CONFIG_TSO_RADDR_READ 0x0040 618 #define TSO_FILE_CONFIG_TS_DATA_PORT_SEL 0x0080 619 #define TSO_FILE_CONFIG_TSO_FILE_IN 0x0100 620 #define TSO_FILE_CONFIG_TIMER_EN 0x0200 621 #define TSO_FILE_CONFIG_PKT_192_BLK_DISABLE 0x0400 622 #define TSO_FILE_CONFIG_PKT_192_EN 0x0800 623 #define TSO_FILE_CONFIG_TSP_FILE_SEGMENT 0x1000 624 #define TSO_FILE_CONFIG_CLK_STAMP_27_EN 0x2000 625 #define TSO_FILE_CONFIG_INIT_TIMESTAMP 0x4000 626 627 REG16_TSO TSO_FILE_CONFIG1; //7a 628 #define TSO_FILE_CONFIG1_TSO2MI_RPRIORITY 0x0001 629 #define TSO_FILE_CONFIG1_MEM_TS_DATA_ENDIAN 0x0002 630 #define TSO_FILE_CONFIG1_MEM_TS_W_ORDER 0x0004 631 #define TSO_FILE_CONFIG1_LPCR2_WLD 0x0008 632 #define TSO_FILE_CONFIG1_LPCR2_LOAD 0x0010 633 #define TSO_FILE_CONFIG1_DIS_MIU_RQ 0x0020 634 #define TSO_FILE_CONFIG1_TSO_RADDR_READ 0x0040 635 #define TSO_FILE_CONFIG1_TS_DATA_PORT_SEL 0x0080 636 #define TSO_FILE_CONFIG1_TSO_FILE_IN 0x0100 637 #define TSO_FILE_CONFIG1_TIMER_EN 0x0200 638 #define TSO_FILE_CONFIG1_PKT_192_BLK_DISABLE 0x0400 639 #define TSO_FILE_CONFIG1_PKT_192_EN 0x0800 640 #define TSO_FILE_CONFIG1_TSP_FILE_SEGMENT 0x1000 641 #define TSO_FILE_CONFIG1_CLK_STAMP_27_EN 0x2000 642 #define TSO_FILE_CONFIG1_INIT_TIMESTAMP 0x4000 643 644 REG16_TSO INTERRUPT; //7b 645 #define TSO_INT_SRC_MASK 0x00FF 646 #define TSO_INT_STS_MASK 0xFF00 647 //----- for TV comaptibility -----// 648 #define TSO_INT_DMA_DONE 0x0001 649 #define TSO_INT_DMA_DONE1 0x0002 650 //--------------------------------// 651 #define TSO_INT_SRC_TRAC_CLK_UPDATE 0x0004 652 #define TSO_INT_STS_DMA_DONE 0x0100 653 #define TSO_INT_STS_DMA_DONE1 0x0200 654 #define TSO_INT_STS_TRAC_CLK_UPDATE 0x0400 655 656 REG16_TSO INTERRUPT1; //7c 657 #define TSO_INT_SRC_PIDFLT1_OVERFLOW 0x0001 658 #define TSO_INT_SRC_PIDFLT2_OVERFLOW 0x0002 659 #define TSO_INT_SRC_PIDFLT3_OVERFLOW 0x0004 660 #define TSO_INT_SRC_PIDFLT4_OVERFLOW 0x0008 661 #define TSO_INT_SRC_PIDFLT5_OVERFLOW 0x0010 662 #define TSO_INT_SRC_PIDFLT6_OVERFLOW 0x0020 663 664 #define TSO_INT_STS_PIDFLT1_OVERFLOW 0x0100 665 #define TSO_INT_STS_PIDFLT2_OVERFLOW 0x0200 666 #define TSO_INT_STS_PIDFLT3_OVERFLOW 0x0400 667 #define TSO_INT_STS_PIDFLT4_OVERFLOW 0x0800 668 #define TSO_INT_STS_PIDFLT5_OVERFLOW 0x1000 669 #define TSO_INT_STS_PIDFLT6_OVERFLOW 0x2000 670 671 REG32_TSO TSO_DEBUG; //7d~7e 672 673 REG16_TSO DBG_SEL; //7f 674 675 } REG_Ctrl_TSO; 676 677 678 //TSO1 679 typedef struct _REG_Ctrl_TSO1 680 { 681 //---------------------------------------------- 682 // 0xBF802C00 MIPS direct access 683 //---------------------------------------------- 684 685 REG16_TSO REG_PRE_HEADER_1_CONFIG_0; //00 686 #define TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 687 #define TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_SHIFT 0 688 689 REG16_TSO REG_PRE_HEADER_1_CONFIG_1; //01 690 REG16_TSO REG_PRE_HEADER_1_CONFIG_2; //02 691 REG16_TSO REG_PRE_HEADER_1_CONFIG_3; //03 692 693 REG16_TSO REG_PRE_HEADER_2_CONFIG_0; //04 694 #define TSO1_REG_PRE_HEADER_2_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 695 #define TSO1_REG_PRE_HEADER_2_CONFIG_0_LOCAL_STREAMID_SHIFT 0 696 697 REG16_TSO REG_PRE_HEADER_2_CONFIG_1; //05 698 REG16_TSO REG_PRE_HEADER_2_CONFIG_2; //06 699 REG16_TSO REG_PRE_HEADER_2_CONFIG_3; //07 700 701 REG16_TSO REG_PRE_HEADER_3_CONFIG_0; //08 702 #define TSO1_REG_PRE_HEADER_3_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 703 #define TSO1_REG_PRE_HEADER_3_CONFIG_0_LOCAL_STREAMID_SHIFT 0 704 705 REG16_TSO REG_PRE_HEADER_3_CONFIG_1; //09 706 REG16_TSO REG_PRE_HEADER_3_CONFIG_2; //0a 707 REG16_TSO REG_PRE_HEADER_3_CONFIG_3; //0b 708 709 REG16_TSO REG_PRE_HEADER_4_CONFIG_0; //0c 710 #define TSO1_REG_PRE_HEADER_4_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 711 #define TSO1_REG_PRE_HEADER_4_CONFIG_0_LOCAL_STREAMID_SHIFT 0 712 713 REG16_TSO REG_PRE_HEADER_4_CONFIG_1; //0d 714 REG16_TSO REG_PRE_HEADER_4_CONFIG_2; //0e 715 REG16_TSO REG_PRE_HEADER_4_CONFIG_3; //0f 716 717 REG16_TSO REG_PRE_HEADER_5_CONFIG_0; //10 718 #define TSO1_REG_PRE_HEADER_5_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 719 #define TSO1_REG_PRE_HEADER_5_CONFIG_0_LOCAL_STREAMID_SHIFT 0 720 721 REG16_TSO REG_PRE_HEADER_5_CONFIG_1; //11 722 REG16_TSO REG_PRE_HEADER_5_CONFIG_2; //12 723 REG16_TSO REG_PRE_HEADER_5_CONFIG_3; //13 724 725 REG16_TSO REG_PRE_HEADER_6_CONFIG_0; //14 726 #define TSO1_REG_PRE_HEADER_6_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 727 #define TSO1_REG_PRE_HEADER_6_CONFIG_0_LOCAL_STREAMID_SHIFT 0 728 729 REG16_TSO REG_PRE_HEADER_6_CONFIG_1; //15 730 REG16_TSO REG_PRE_HEADER_6_CONFIG_2; //16 731 REG16_TSO REG_PRE_HEADER_6_CONFIG_3; //17 732 733 REG32_TSO SVQ1_BASE; //18~19 734 #define TSO1_SVQ1_BASE_MASK 0x0FFFFFFF 735 #define TSO1_SVQ1_BASE_SHIFT 0 736 737 REG16_TSO SVQ1_SIZE_200BYTE; //1a 738 #define TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_MASK 0xFFFF 739 #define TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_SHIFT 0 740 741 REG16_TSO SVQ1_TX_CONFIG; //1b 742 #define TSO1_SVQ1_TX_CONFIG_WR_THRESHOLD_MASK 0x000F 743 #define TSO1_SVQ1_TX_CONFIG_WR_THRESHOLD_SHIFT 0 744 #define TSO1_SVQ1_TX_CONFIG_PRIORITY_THRESHOLD_MASK 0x00F0 745 #define TSO1_SVQ1_TX_CONFIG_PRIORITY_THRESHOLD_SHIFT 4 746 #define TSO1_SVQ1_TX_CONFIG_FORCEFIRE_CNT_MASK 0x0F00 747 #define TSO1_SVQ1_TX_CONFIG_FORCEFIRE_CNT_SHIFT 8 748 #define TSO1_SVQ1_TX_CONFIG_TX_RESET 0x1000 749 #define TSO1_SVQ1_TX_CONFIG_OVERFLOW_INT_EN 0x2000 750 #define TSO1_SVQ1_TX_CONFIG_OVERFLOW_CLR 0x4000 751 #define TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE 0x8000 752 REG32_TSO SVQ2_BASE; //1C~1D 753 REG16_TSO SVQ2_SIZE_200BYTE; //1E 754 REG16_TSO SVQ2_TX_CONFIG; //1F 755 REG32_TSO SVQ3_BASE; //20~21 756 REG16_TSO SVQ3_SIZE_200BYTE; //22 757 REG16_TSO SVQ3_TX_CONFIG; //23 758 REG32_TSO SVQ4_BASE; //24~25 759 REG16_TSO SVQ4_SIZE_200BYTE; //26 760 REG16_TSO SVQ4_TX_CONFIG; //27 761 REG32_TSO SVQ5_BASE; //28~29 762 REG16_TSO SVQ5_SIZE_200BYTE; //2a 763 REG16_TSO SVQ5_TX_CONFIG; //2b 764 REG32_TSO SVQ6_BASE; //2C~2D 765 REG16_TSO SVQ6_SIZE_200BYTE; //2E 766 REG16_TSO SVQ6_TX_CONFIG; //2F 767 768 REG16_TSO SVQ_RX_CONFIG; //30 769 #define TSO1_SVQ_RX_CONFIG_MODE_MASK 0x0003 //00=open cable 01=CI+ 10=192 mode 770 #define TSO1_SVQ_RX_CONFIG_MODE_SHIT 0 771 //----- for TV comaptibility -----// 772 #define TSO_SVQ_RX_CFG_MODE_OPENCBL 0x0000 773 #define TSO_SVQ_RX_CFG_MODE_CIPL 0x0001 774 #define TSO_SVQ_RX_CFG_MODE_192PKT 0x0002 775 //--------------------------------// 776 #define TSO1_SVQ_RX_CONFIG_RD_THRESHOLD_MASK 0x001C //000=1/6 empty 001=1/8 empty 010=1/4 empty 011=1/2 empty else empty 777 #define TSO1_SVQ_RX_CONFIG_RD_THRESHOLD_SHIT 2 778 #define TSO1_SVQ_RX_CONFIG_ARBITOR_MODE_MASK 0x0060 //00=Run-Robin. 01=fix priority by REG 0x31~33 mode 10=dynamic priority 779 #define TSO1_SVQ_RX_CONFIG_ARBITOR_MODE_SHIT 5 780 //----- for TV comaptibility -----// 781 #define TSO_SVQ_RX_CFG_ARBMODE_RUNROBIN 0x0000 782 #define TSO_SVQ_RX_CFG_ARBMODE_FIXPRI 0x0001 783 #define TSO_SVQ_RX_CFG_ARBMODE_DYMPRI 0x0002 784 //--------------------------------// 785 #define TSO1_SVQ_RX_CONFIG_SRAM_SD_EN 0x0080 786 #define TSO1_SVQ_RX_CONFIG_SVQ_FORCE_RESET 0x0100 787 #define TSO1_SVQ_RX_CONFIG_SVQ_MIU_NS 0x0200 788 #define TSO1_SVQ_RX_CONFIG_SVQ_MOBF_INDEX_MASK 0x7C00 789 #define TSO1_SVQ_RX_CONFIG_SVQ_MOBF_INDEX_SHIFT 10 790 #define TSO1_SVQ_RX_CONFIG_SVQ_DYNAMIC_PRI 0x8000 791 792 REG16_TSO SVQ_RX_1_2_PRIORITY; //31 793 #define TSO1_SVQ_RX1_PRIORITY_MASK 0x003F 794 #define TSO1_SVQ_RX1_PRIORITY_SHIFT 0 795 #define TSO1_SVQ_RX2_PRIORITY_MASK 0x3F00 796 #define TSO1_SVQ_RX2_PRIORITY_SHIFT 8 797 798 REG16_TSO SVQ_RX_3_4_PRIORITY; //32 799 #define TSO1_SVQ_RX3_PRIORITY_MASK 0x003F 800 #define TSO1_SVQ_RX3_PRIORITY_SHIFT 0 801 #define TSO1_SVQ_RX4_PRIORITY_MASK 0x3F00 802 #define TSO1_SVQ_RX4_PRIORITY_SHIFT 8 803 804 REG16_TSO SVQ_RX_5_6_PRIORITY; //33 805 #define TSO1_SVQ_RX5_PRIORITY_MASK 0x003F 806 #define TSO1_SVQ_RX5_PRIORITY_SHIFT 0 807 #define TSO1_SVQ_RX6_PRIORITY_MASK 0x3F00 808 #define TSO1_SVQ_RX6_PRIORITY_SHIFT 8 809 810 REG32_TSO SVQ_STATUS; //34~35 811 //----- for TV comaptibility -----// 812 #define TSO_SVQ_STS_MASK 0x000F 813 #define TSO_SVQ1_STS_SHIFT 0 814 #define TSO_SVQ2_STS_SHIFT 4 815 #define TSO_SVQ3_STS_SHIFT 8 816 #define TSO_SVQ4_STS_SHIFT 12 817 #define TSO_SVQ5_STS_SHIFT 16 818 #define TSO_SVQ6_STS_SHIFT 20 819 #define TSO_SVQ_STS_EVER_FULL 0x0001 820 #define TSO_SVQ_STS_EVER_OVF 0x0002 821 #define TSO_SVQ_STS_EMPTY 0x0004 822 #define TSO_SVQ_STS_BUSY 0x0008 823 //--------------------------------// 824 #define TSO1_SVQ1_OVERFLOW_INT 0x01000000 825 #define TSO1_SVQ2_OVERFLOW_INT 0x02000000 826 #define TSO1_SVQ3_OVERFLOW_INT 0x04000000 827 #define TSO1_SVQ4_OVERFLOW_INT 0x08000000 828 #define TSO1_SVQ5_OVERFLOW_INT 0x10000000 829 #define TSO1_SVQ6_OVERFLOW_INT 0x20000000 830 831 REG32_TSO SVQ_STATUS2; //36~37 832 #define TSO1_SVQ1_TX_WATER_LEVEL_MASK 0x00000003 833 #define TSO1_SVQ1_TX_WATER_LEVEL_SHIFT 0 834 #define TSO1_SVQ1_TX_FULL_MASK 0x00000004 835 #define TSO1_SVQ1_TX_FULL_SHIFT 2 836 #define TSO1_SVQ1_TX_EMPTY_MASK 0x00000008 837 #define TSO1_SVQ1_TX_EMPTY_SHIFT 3 838 #define TSO1_SVQ2_TX_WATER_LEVEL_MASK 0x00000030 839 #define TSO1_SVQ2_TX_WATER_LEVEL_SHIFT 4 840 #define TSO1_SVQ2_TX_FULL_MASK 0x00000040 841 #define TSO1_SVQ2_TX_FULL_SHIFT 6 842 #define TSO1_SVQ2_TX_EMPTY_MASK 0x00000080 843 #define TSO1_SVQ2_TX_EMPTY_SHIFT 7 844 #define TSO1_SVQ3_TX_WATER_LEVEL_MASK 0x00000300 845 #define TSO1_SVQ3_TX_WATER_LEVEL_SHIFT 8 846 #define TSO1_SVQ3_TX_FULL_MASK 0x00000400 847 #define TSO1_SVQ3_TX_FULL_SHIFT 10 848 #define TSO1_SVQ3_TX_EMPTY_MASK 0x00000800 849 #define TSO1_SVQ3_TX_EMPTY_SHIFT 11 850 #define TSO1_SVQ4_TX_WATER_LEVEL_MASK 0x00003000 851 #define TSO1_SVQ4_TX_WATER_LEVEL_SHIFT 12 852 #define TSO1_SVQ4_TX_FULL_MASK 0x00004000 853 #define TSO1_SVQ4_TX_FULL_SHIFT 14 854 #define TSO1_SVQ4_TX_EMPTY_MASK 0x00008000 855 #define TSO1_SVQ4_TX_EMPTY_SHIFT 15 856 #define TSO1_SVQ5_TX_WATER_LEVEL_MASK 0x00030000 857 #define TSO1_SVQ5_TX_WATER_LEVEL_SHIFT 16 858 #define TSO1_SVQ5_TX_FULL_MASK 0x00040000 859 #define TSO1_SVQ5_TX_FULL_SHIFT 18 860 #define TSO1_SVQ5_TX_EMPTY_MASK 0x00080000 861 #define TSO1_SVQ5_TX_EMPTY_SHIFT 19 862 #define TSO1_SVQ6_TX_WATER_LEVEL_MASK 0x00300000 863 #define TSO1_SVQ6_TX_WATER_LEVEL_SHIFT 20 864 #define TSO1_SVQ6_TX_FULL_MASK 0x00400000 865 #define TSO1_SVQ6_TX_FULL_SHIFT 22 866 #define TSO1_SVQ6_TX_EMPTY_MASK 0x00800000 867 #define TSO1_SVQ6_TX_EMPTY_SHIFT 23 868 869 REG32_TSO DELTA; //38~39 870 871 REG16_TSO DELTA_CONFIG; //3a 872 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_MASK 0x0007 873 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_SHIFT 0 874 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_1 1 875 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_2 2 876 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_3 3 877 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_4 4 878 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_5 5 879 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_6 6 880 #define TSO1_DELTA_CONFIG_DELTA_CLR 0x0008 881 #define TSO1_DELTA_CONFIG_MAX_ID_MASK 0x0070 882 #define TSO1_DELTA_CONFIG_MAX_ID_SHIFT 8 883 884 REG16_TSO REG_TSO1_CFG3B_52[0x53 - 0x3B]; //3b~52 885 886 REG16_TSO REG_TSO_MIU_SEL_1; //53 887 #define REG_MIU_SEL_SVQTX1_MASK 0x0003 888 #define REG_MIU_SEL_SVQTX1_SHIFT 0 889 #define REG_MIU_SEL_SVQTX2_MASK 0x000C 890 #define REG_MIU_SEL_SVQTX2_SHIFT 2 891 #define REG_MIU_SEL_SVQTX3_MASK 0x0030 892 #define REG_MIU_SEL_SVQTX3_SHIFT 4 893 #define REG_MIU_SEL_SVQTX4_MASK 0x00C0 894 #define REG_MIU_SEL_SVQTX4_SHIFT 6 895 #define REG_MIU_SEL_SVQTX5_MASK 0x0300 896 #define REG_MIU_SEL_SVQTX5_SHIFT 8 897 #define REG_MIU_SEL_SVQTX6_MASK 0x0C00 898 #define REG_MIU_SEL_SVQTX6_SHIFT 10 899 #define REG_MIU_SEL_SVQRX_MASK 0x300 900 #define REG_MIU_SEL_SVQRX_SHIFT 12 901 #define REG_MIU_SEL_CH5FILEIN_MASK 0xC000 902 #define REG_MIU_SEL_CH5FILEIN_SHIFT 14 903 904 REG16_TSO REG_TSO_MIU_SEL_2; //54 905 #define REG_MIU_SEL_CH6FILEIN_MASK 0x0003 906 #define REG_MIU_SEL_CH6FILEIN_SHIFT 0 907 908 REG16_TSO REG_TSO1_CFG55_69[0x70 - 0x55]; //55~69 909 910 REG16_TSO REG_TSO1_PKT_TIME_THRESHOLD_CFG70; //70 911 REG16_TSO REG_TSO1_DATA_TRACING_CONFIG_CFG71; //71 912 #define TSO1_REG_DATA_TRACING_ST_CLR 0x0001 // 1: data rate trace status clear 913 #define TSO1_REG_DATA_TRACING_ST_LD 0x0002 // 1: load latest info 0: keep old info 914 #define TSO1_REG_MAX_MIN_EVER_CURRENT 0x0004 // 1: max/min ever, 0: max/min in current sample period 915 #define TSO1_REG_DATA_RATE_SRC_SEL_MASK 0x00F0 916 #define TSO1_REG_DATA_RATE_SRC_SEL_SHIFT 4 917 #define TSO1_REG_DATA_TRACING_SHIFT_VAL_MASK 0x0F00 918 #define TSO1_REG_DATA_TRACING_SHIFT_VAL_SHIFT 8 919 REG32_TSO REG_TSO1_REG_AVG_PKT_TIME; //72~73 920 REG32_TSO REG_TSO1_MIN_PKT_TIME; //74~75 921 REG32_TSO REG_TSO1_MAX_PKT_TIME; //76~77 922 923 } REG_Ctrl_TSO1; 924 925 926 //TSO2 927 typedef struct _REG_Ctrl_TSO2 928 { 929 //---------------------------------------------- 930 // 0xBF802A00 MIPS direct access 931 //---------------------------------------------- 932 933 REG16_TSO REG_TSO2_PVR1_CONFIR1; //00 934 #define TSO2_REG_PVR1_REG_PINGPONG_EN 0x0001 935 #define TSO2_REG_PVR1_STR2MI_EN 0x0002 936 #define TSO2_REG_PVR1_STR2MI_RST_WADR 0x0004 937 #define TSO2_REG_PVR1_STR2MI_PARSE 0x0008 938 #define TSO2_REG_PVR1_PKT192_EN 0x0010 939 #define TSO2_REG_PVR1_BURST_LEN_MASK 0x0060 940 #define TSO2_REG_PVR1_BURST_LEN_SHIFT 5 941 #define TSO2_REG_PVR1_LPCR1_WLD 0x0080 942 #define TSO2_REG_PVR1_PVR_ALIGN_EN 0x0100 943 #define TSO2_REG_PVR1_STR2MI_DSWAP 0x0200 944 #define TSO2_REG_PVR1_STR2MI_BT_ORDER 0x0400 945 #define TSO2_REG_REC_DATA_INV_EN 0x0800 946 #define TSO2_REG_PVR1_BLOCK_DIS 0x1000 947 #define TSO2_REG_PID_BYPASS_REC 0x2000 948 #define TSO2_REG_REC_ALL 0x4000 949 #define TSO2_REG_PVR1_LPCR1_RLD 0x8000 950 951 REG32_TSO REG_TSO2_PVR1_STR2MI_HEAD; //01~02 952 REG32_TSO REG_TSO2_PVR1_STR2MI_MID; //03~04 953 REG32_TSO REG_TSO2_PVR1_STR2MI_TAIL; //05~06 954 REG32_TSO REG_TSO2_PVR1_STR2MI_HEAD2; //07~08 955 REG32_TSO REG_TSO2_PVR1_STR2MI_MID2; //09~0A 956 REG32_TSO REG_TSO2_PVR1_STR2MI_TAIL2; //0B~0C 957 958 REG16_TSO REG_TSO2_PVR1_CONFIR2; //0D 959 #define TSO2_REG_PVR1_SRAM_SD_EN 0x0001 960 #define TSO2_REG_PVR1_FLUSH_DATA 0x0002 961 #define TSO2_REG_PVR1_STR2MI_WP_LD 0x0004 962 #define TSO2_REG_PVR1_CLR 0x0008 963 #define TSO2_REG_PVR1_DMA_FLUSH_EN 0x0010 964 #define TSO2_REG_PVR1_FORCE_SYNC_EN 0x0020 965 #define TSO2_REG_PVR1_RECORD_DIS_SYNC_EN 0x0040 966 #define TSO2_REG_PVR1_MIU_HIGHPRI 0x0080 967 #define TSO2_REG_PVR1_RECORD_ALL_OLD 0x0100 968 #define TSO2_REG_PVR1_WRITE_POINTER_TO_NEXT_ADDR_EN 0x0200 969 #define TSO2_REG_PVR1_DMAW_PROTECT_EN 0x0400 970 #define TSO2_REG_PVR1_CLR_NO_HIT_INT 0x0800 971 972 REG32_TSO REG_TSO2_PVR1_DMAW_LBUD; //0E~0F 973 REG32_TSO REG_TSO2_PVR1_DMAW_UBUD; //10~11 974 REG32_TSO REG_TSO2_PVR1_LPCR1; //12~13 975 976 REG16_TSO REG_TSO2_CFG14; //14 977 #define TSO2_REG_PVR1_SRC_MASK 0x0003 //01 : from svq merge stream, 10: MMT function 978 #define TSO2_REG_CLK_27M_90K 0x0004 // 0 : 90k, 1: 27M 979 980 REG16_TSO REG_TSO2_CFG15_1F[11]; //15~1F 981 982 REG16_TSO REG_TSO2_CFG20; //20 983 #define TSO2_REG_SYNC_RISING_DETECT 0x0001 984 #define TSO2_REG_VALID_FALLING_DETECT_INV 0x0002 985 #define TSO2_REG_FROCE_SYNCBYTE 0x0004 986 #define TSO2_REG_P_SEL 0x0008 987 #define TSO2_REG_EXT_SYNC_SEL 0x0010 988 #define TSO2_REG_DATA_CHK_2T 0x0020 989 #define TSO2_REG_SERIAL_EXT_SYNC_1T 0x0040 990 #define TSO2_REG_TSIF_EVER_OVERFLOW_CLR 0x0080 991 #define TSO2_REG_PKT_CHK_SIZE_MASK 0xFF00 992 #define TSO2_REG_PKT_CHK_SIZE_SHIFT 8 993 REG16_TSO REG_TSO2_MMT_CFG21; //21 994 #define TSO2_REG_TSO_MMT_EN 0x0001 995 #define TSO2_REG_3_WIRE_EN_MMT 0x0002 996 #define TSO2_REG_SW_RST_TS_MMT 0x0004 997 #define TSO2_REG_LOCKED_PKT_CNT_MMT_LOAD 0x0008 998 #define TSO2_REG_LOCKED_PKT_CNT_MMT_CLR 0x0010 999 REG32_TSO REG_TSO2_PVR1_DMAW_WADDR_ERR; //22~23 1000 REG16_TSO REG_TSO2_MOBF_CFG24; //24 1001 REG32_TSO REG_TSO2_STR2MI_WADR_R; //25~26 1002 REG16_TSO REG_TSO2_CFG27; //27 1003 #define TSO2_REG_TSIF_EVER_OVERFLOW_FLAG 0x0001 1004 #define TSO2_REG_FLUSH_DATA_PVR1_STATUS 0x0002 1005 #define TSO2_REG_PVR1_FIFO_STATUS_MASK 0x003C 1006 #define TSO2_REG_PVR1_FIFO_STATUS_SHIFT 2 1007 1008 REG16_TSO REG_TSO2_CFG28_2F[8]; //28~2F 1009 1010 REG16_TSO REG_TSO2_PCR_CFG30; //30 1011 #define TSO2_REG_TEI_SKIP_PKT_PCR1 0x0001 1012 #define TSO2_REG_PCR1_RESET 0x0002 1013 #define TSO2_REG_PCR1_READ 0x0004 1014 #define TSO2_REG_TEI_SKIP_PKT_PCR2 0x0010 1015 #define TSO2_REG_PCR2_RESET 0x0020 1016 #define TSO2_REG_PCR2_READ 0x0040 1017 #define TSO2_REG_TEI_SKIP_PKT_PCR3 0x0100 1018 #define TSO2_REG_PCR3_RESET 0x0200 1019 #define TSO2_REG_PCR3_READ 0x0400 1020 #define TSO2_REG_TEI_SKIP_PKT_PCR4 0x1000 1021 #define TSO2_REG_PCR4_RESET 0x2000 1022 #define TSO2_REG_PCR4_READ 0x4000 1023 REG16_TSO REG_TSO2_PCR2_CFG31; //31 1024 #define TSO2_REG_TEI_SKIP_PKT_PCR5 0x0001 1025 #define TSO2_REG_PCR5_RESET 0x0002 1026 #define TSO2_REG_PCR5_READ 0x0004 1027 #define TSO2_REG_TEI_SKIP_PKT_PCR6 0x0010 1028 #define TSO2_REG_PCR6_RESET 0x0020 1029 #define TSO2_REG_PCR6_READ 0x0040 1030 1031 REG16_TSO REG_TSO2_PIDFLT_PCR_CFG32_37[6]; //32~37 1032 #define TSO2_REG_PIDFLT_PCR_PID_MASK 0x1FFF 1033 #define TSO2_REG_PIDFLT_PCR_ENPCR 0x8000 1034 1035 REG32_TSO REG_TSO2_PCR1_LOW32_CFG38_39; //38~39 1036 REG16_TSO REG_TSO2_PCR1_VAILD_CFG3A; //3A 1037 #define TSO2_REG_PCR1_VALID_33_HIGH 0x0001 1038 #define TSO2_REG_PCR1_VALID_EXT_MASK 0x03FE 1039 #define TSO2_REG_PCR1_VALID_EXT_SHIFT 1 1040 1041 REG32_TSO REG_TSO2_PCR2_LOW32_CFG3B_3C; //3B~3C 1042 REG16_TSO REG_TSO2_PCR2_VAILD_CFG3D; //3D 1043 #define TSO2_REG_PCR2_VALID_33_HIGH 0x0001 1044 #define TSO2_REG_PCR2_VALID_EXT_MASK 0x03FE 1045 #define TSO2_REG_PCR2_VALID_EXT_SHIFT 1 1046 1047 REG32_TSO REG_TSO2_PCR3_LOW32_CFG3E_3F; //3E~3F 1048 REG16_TSO REG_TSO2_PCR3_VAILD_CFG40; //40 1049 #define TSO2_REG_PCR3_VALID_33_HIGH 0x0001 1050 #define TSO2_REG_PCR3_VALID_EXT_MASK 0x03FE 1051 #define TSO2_REG_PCR3_VALID_EXT_SHIFT 1 1052 1053 REG32_TSO REG_TSO2_PCR4_LOW32_CFG41_42; //41~42 1054 REG16_TSO REG_TSO2_PCR4_VAILD_CFG43; //43 1055 #define TSO2_REG_PCR4_VALID_33_HIGH 0x0001 1056 #define TSO2_REG_PCR4_VALID_EXT_MASK 0x03FE 1057 #define TSO2_REG_PCR4_VALID_EXT_SHIFT 1 1058 1059 REG32_TSO REG_TSO2_PCR5_LOW32_CFG44_45; //44~45 1060 REG16_TSO REG_TSO2_PCR5_VAILD_CFG46; //46 1061 #define TSO2_REG_PCR5_VALID_33_HIGH 0x0001 1062 #define TSO2_REG_PCR5_VALID_EXT_MASK 0x03FE 1063 #define TSO2_REG_PCR5_VALID_EXT_SHIFT 1 1064 1065 REG32_TSO REG_TSO2_PCR6_LOW32_CFG47_48; //47~48 1066 REG16_TSO REG_TSO2_PCR6_VAILD_CFG49; //49 1067 #define TSO2_REG_PCR6_VALID_33_HIGH 0x0001 1068 #define TSO2_REG_PCR6_VALID_EXT_MASK 0x03FE 1069 #define TSO2_REG_PCR6_VALID_EXT_SHIFT 1 1070 1071 REG16_TSO REG_TSO2_CFG4A_4F[6]; //4A~4F 1072 REG16_TSO REG_TSO2_SG_PDFLT_CONFIG0_CFG50; //50 1073 #define TSO2_REG_SG_PD_FLT_DISABLE 0x0001 1074 #define TSO2_REG_PDFLT_REC_ALL 0x0010 1075 #define TSO2_REG_PDFLT_REC_NULL 0x0020 1076 #define TSO2_REG_PDFLT_OVERFLOW_INT_EN 0x0040 1077 #define TSO2_REG_PDFLT_OVERFLOW_CLR 0x0080 1078 #define TSO2_REG_SKIP_TEI_PKT 0x0200 1079 1080 REG32_TSO REG_TSO2_SG_PDFLT_SVID_EN[2]; //51~54 1081 REG16_TSO REG_TSO2_SG_PDTABLE_RDATA_CFG55; //55 1082 REG16_TSO REG_TSO2_SG_PD_CFG56; //56 1083 #define TSO2_REG_SG_PDTABLE_RDATA_H_MASK 0x003F 1084 #define TSO2_REG_READ_SG_PDFLT_EVER_OVERFLOW 0x0100 1085 1086 } REG_Ctrl_TSO2; 1087 1088 //TSO4 1089 typedef struct _REG_Ctrl_TSO4 1090 { 1091 //---------------------------------------------- 1092 // 0xBF802A00 MIPS direct access 1093 //---------------------------------------------- 1094 1095 REG16_TSO SYNC_BYTE_1[4]; //0x00~0x03, reg_sync_byte_1_0 ~ reg_sync_byte_1_7 1096 #define TSO4_SYNC_BYTE_MASK0 0x00FF 1097 #define TSO4_SYNC_BYTE_SHIFT0 0 1098 #define TSO4_SYNC_BYTE_MASK1 0xFF00 1099 #define TSO4_SYNC_BYTE_SHIFT1 8 1100 REG16_TSO SYNC_BYTE_1_REPLACE[4]; //0x04~0x07, reg_sync_byte_1_0_replace ~ reg_sync_byte_1_7_replace 1101 #define TSO4_SYNC_BYTE_REPLACE_MASK0 0x00FF 1102 #define TSO4_SYNC_BYTE_REPLACE_SHIFT0 0 1103 #define TSO4_SYNC_BYTE_REPLACE_MASK1 0xFF00 1104 #define TSO4_SYNC_BYTE_REPLACE_SHIFT1 8 1105 REG16_TSO SYNC_BYTE_2[4]; //0x08~0x0B, reg_sync_byte_2_0 ~ reg_sync_byte_2_7 1106 REG16_TSO SYNC_BYTE_2_REPLACE[4]; //0x0C~0x0F, reg_sync_byte_2_0_replace ~ reg_sync_byte_2_7_replace 1107 REG16_TSO SYNC_BYTE_3[4]; //0x10~0x13, reg_sync_byte_3_0 ~ reg_sync_byte_3_7 1108 REG16_TSO SYNC_BYTE_3_REPLACE[4]; //0x14~0x17, reg_sync_byte_3_0_replace ~ reg_sync_byte_3_7_replace 1109 REG16_TSO SYNC_BYTE_4[4]; //0x18~0x1B, reg_sync_byte_4_0 ~ reg_sync_byte_4_7 1110 REG16_TSO SYNC_BYTE_4_REPLACE[4]; //0x1C~0x1F, reg_sync_byte_4_0_replace ~ reg_sync_byte_4_7_replace 1111 REG16_TSO SYNC_BYTE_5[4]; //0x20~0x23, reg_sync_byte_5_0 ~ reg_sync_byte_5_7 1112 REG16_TSO SYNC_BYTE_5_REPLACE[4]; //0x24~0x27, reg_sync_byte_5_0_replace ~ reg_sync_byte_5_7_replace 1113 REG16_TSO SYNC_BYTE_6[4]; //0x28~0x2B, reg_sync_byte_6_0 ~ reg_sync_byte_6_7 1114 REG16_TSO SYNC_BYTE_6_REPLACE[4]; //0x2C~0x2F, reg_sync_byte_6_0_replace ~ reg_sync_byte_6_7_replace 1115 1116 REG16_TSO REG_TSO4_CFG30_3F[16]; //30~3F reserved 1117 1118 REG16_TSO SYNC_BYTE_ENABLE_REPLACE_1; //40 1119 #define TSO4_SYNC_BYTE_0_ENABLE 0x0001 1120 #define TSO4_SYNC_BYTE_1_ENABLE 0x0002 1121 #define TSO4_SYNC_BYTE_2_ENABLE 0x0004 1122 #define TSO4_SYNC_BYTE_3_ENABLE 0x0008 1123 #define TSO4_SYNC_BYTE_4_ENABLE 0x0010 1124 #define TSO4_SYNC_BYTE_5_ENABLE 0x0020 1125 #define TSO4_SYNC_BYTE_6_ENABLE 0x0040 1126 #define TSO4_SYNC_BYTE_7_ENABLE 0x0080 1127 #define TSO4_SYNC_BYTE_0_REPLACE_ENABLE 0x0100 1128 #define TSO4_SYNC_BYTE_1_REPLACE_ENABLE 0x0200 1129 #define TSO4_SYNC_BYTE_2_REPLACE_ENABLE 0x0400 1130 #define TSO4_SYNC_BYTE_3_REPLACE_ENABLE 0x0800 1131 #define TSO4_SYNC_BYTE_4_REPLACE_ENABLE 0x1000 1132 #define TSO4_SYNC_BYTE_5_REPLACE_ENABLE 0x2000 1133 #define TSO4_SYNC_BYTE_6_REPLACE_ENABLE 0x4000 1134 #define TSO4_SYNC_BYTE_7_REPLACE_ENABLE 0x8000 1135 REG16_TSO SYNC_BYTE_ENABLE_REPLACE_2; //41 1136 REG16_TSO SYNC_BYTE_ENABLE_REPLACE_3; //42 1137 REG16_TSO SYNC_BYTE_ENABLE_REPLACE_4; //43 1138 REG16_TSO SYNC_BYTE_ENABLE_REPLACE_5; //44 1139 REG16_TSO SYNC_BYTE_ENABLE_REPLACE_6; //45 1140 1141 REG16_TSO REG_TSO4_CFG46_4F[10]; //46~4F reserved 1142 1143 REG16_TSO MERGE_PATH_1_2; //50 1144 #define TSO4_MERGE_PATH_1_DISABLE 0x0001 1145 #define TSO4_MERGE_PATH_1_BACK_BLOCK_LIVEIN 0x0002 1146 #define TSO4_MERGE_PATH_1_NON188_ENABLE 0x0004 1147 #define TSO4_MERGE_PATH_1_USE_ORG_SYNC_BYTE 0x0008 1148 #define TSO4_MERGE_PATH_2_DISABLE 0x0100 1149 #define TSO4_MERGE_PATH_2_BACK_BLOCK_LIVEIN 0x0200 1150 #define TSO4_MERGE_PATH_2_NON188_ENABLE 0x0400 1151 #define TSO4_MERGE_PATH_2_USE_ORG_SYNC_BYTE 0x0800 1152 1153 REG16_TSO MERGE_PATH_3_4; //51 1154 #define TSO4_MERGE_PATH_3_DISABLE 0x0001 1155 #define TSO4_MERGE_PATH_3_BACK_BLOCK_LIVEIN 0x0002 1156 #define TSO4_MERGE_PATH_3_NON188_ENABLE 0x0004 1157 #define TSO4_MERGE_PATH_3_USE_ORG_SYNC_BYTE 0x0008 1158 #define TSO4_MERGE_PATH_4_DISABLE 0x0100 1159 #define TSO4_MERGE_PATH_4_BACK_BLOCK_LIVEIN 0x0200 1160 #define TSO4_MERGE_PATH_4_NON188_ENABLE 0x0400 1161 #define TSO4_MERGE_PATH_4_USE_ORG_SYNC_BYTE 0x0800 1162 1163 REG16_TSO MERGE_PATH_5_6; //52 1164 #define TSO4_MERGE_PATH_5_DISABLE 0x0001 1165 #define TSO4_MERGE_PATH_5_BACK_BLOCK_LIVEIN 0x0002 1166 #define TSO4_MERGE_PATH_5_NON188_ENABLE 0x0004 1167 #define TSO4_MERGE_PATH_5_USE_ORG_SYNC_BYTE 0x0008 1168 #define TSO4_MERGE_PATH_6_DISABLE 0x0100 1169 #define TSO4_MERGE_PATH_6_BACK_BLOCK_LIVEIN 0x0200 1170 #define TSO4_MERGE_PATH_6_NON188_ENABLE 0x0400 1171 #define TSO4_MERGE_PATH_6_USE_ORG_SYNC_BYTE 0x0800 1172 1173 REG16_TSO MERGE_PATH_7_8; //53 1174 #define TSO4_MERGE_PATH_7_DISABLE 0x0001 1175 #define TSO4_MERGE_PATH_7_BACK_BLOCK_LIVEIN 0x0002 1176 #define TSO4_MERGE_PATH_7_NON188_ENABLE 0x0004 1177 #define TSO4_MERGE_PATH_7_USE_ORG_SYNC_BYTE 0x0008 1178 #define TSO4_MERGE_PATH_8_DISABLE 0x0100 1179 #define TSO4_MERGE_PATH_8_BACK_BLOCK_LIVEIN 0x0200 1180 #define TSO4_MERGE_PATH_8_NON188_ENABLE 0x0400 1181 #define TSO4_MERGE_PATH_8_USE_ORG_SYNC_BYTE 0x0800 1182 1183 REG16_TSO MERGE_CTRL; //54 1184 #define TSO4_MERGE_CTRL_STATUS_SEL_MASK 0x000F 1185 #define TSO4_MERGE_CTRL_STATUS_SEL_SHIFT 0 1186 #define TSO4_MERGE_CTRL_SW_RSTZ1 0x0100 1187 #define TSO4_MERGE_CTRL_SW_RSTZ2 0x0200 1188 #define TSO4_MERGE_CTRL_SW_RSTZ3 0x0400 1189 #define TSO4_MERGE_CTRL_SW_RSTZ4 0x0800 1190 #define TSO4_MERGE_CTRL_SW_RSTZ5 0x1000 1191 #define TSO4_MERGE_CTRL_SW_RSTZ6 0x2000 1192 #define TSO4_MERGE_CTRL_SW_RSTZ7 0x4000 1193 #define TSO4_MERGE_CTRL_SW_RSTZ8 0x8000 1194 1195 } REG_Ctrl_TSO4; 1196 1197 #endif // _TSO_REG_H_ 1198