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Searched refs:MIU_BUS (Results 1 – 25 of 71) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/tee/
H A DhalTSP_tee.c136 MS_U32 u32FwAddr = ((MS_U32)phyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_Tee_Set_FWBuf()
157 u32VQSize = ((u32Size >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_Tee_Set_VQBuf()
164 phyMiuAddr = phyVQBufStart >> MIU_BUS; in HAL_TSP_Tee_Set_VQBuf()
204 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
207 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
211 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
214 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
220 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
223 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
227 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/tee/
H A DhalTSP_tee.c136 MS_U32 u32FwAddr = ((MS_U32)phyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_Tee_Set_FWBuf()
157 u32VQSize = ((u32Size >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_Tee_Set_VQBuf()
164 phyMiuAddr = phyVQBufStart >> MIU_BUS; in HAL_TSP_Tee_Set_VQBuf()
204 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
207 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
211 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
214 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
220 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
223 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
227 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/pvr_iframelut/hal/k6lite/pvr_iframelut/
H A DhalPVR_IframeLUT.c45 #define MIU_BUS (4) macro
142 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_10_11, u32StartAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()
144 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_14_15), u32EndAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()
146 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_12_13), u32EndAddr0 >> (MIU_BUS + 1)); in _HAL_PVR_IframeLUT_SetBuf()
150 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_16_17, u32StartAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()
152 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_1A_1B, u32EndAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()
154 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_18_19), u32EndAddr0 >> (MIU_BUS + 1)); in _HAL_PVR_IframeLUT_SetBuf()
159 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_1C_1D), u32StartAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()
161 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_20_21), u32EndAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()
163 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_1E_1F), u32EndAddr0 >> (MIU_BUS + 1)); in _HAL_PVR_IframeLUT_SetBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/tee/
H A DhalTSP_tee.c135 MS_U32 u32FwAddr = ((MS_U32)phyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_Tee_Set_FWBuf()
156 u32VQSize = ((u32Size >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_Tee_Set_VQBuf()
162 phyMiuAddr = phyVQBufStart >> MIU_BUS; in HAL_TSP_Tee_Set_VQBuf()
202 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
205 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
209 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
212 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
218 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
221 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
225 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/tee/
H A DhalTSP_tee.c135 MS_U32 u32FwAddr = ((MS_U32)phyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_Tee_Set_FWBuf()
156 u32VQSize = ((u32Size >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_Tee_Set_VQBuf()
162 phyMiuAddr = phyVQBufStart >> MIU_BUS; in HAL_TSP_Tee_Set_VQBuf()
202 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
205 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
209 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
212 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
218 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
221 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
225 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/tee/
H A DhalTSP_tee.c135 MS_U32 u32FwAddr = ((MS_U32)phyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_Tee_Set_FWBuf()
156 u32VQSize = ((u32Size >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_Tee_Set_VQBuf()
162 phyMiuAddr = phyVQBufStart >> MIU_BUS; in HAL_TSP_Tee_Set_VQBuf()
202 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
205 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
209 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
212 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
218 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
221 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
225 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/tee/
H A DhalTSP_tee.c135 MS_U32 u32FwAddr = ((MS_U32)phyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_Tee_Set_FWBuf()
156 u32VQSize = ((u32Size >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_Tee_Set_VQBuf()
162 phyMiuAddr = phyVQBufStart >> MIU_BUS; in HAL_TSP_Tee_Set_VQBuf()
202 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
205 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
209 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
212 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
218 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
221 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
225 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/tee/
H A DhalTSP_tee.c135 MS_U32 u32FwAddr = ((MS_U32)phyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_Tee_Set_FWBuf()
156 u32VQSize = ((u32Size >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_Tee_Set_VQBuf()
162 phyMiuAddr = phyVQBufStart >> MIU_BUS; in HAL_TSP_Tee_Set_VQBuf()
202 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
205 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
209 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
212 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
218 phyMiuAddr = phyAddr0 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
221 phyMiuAddr = phyEnd >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
225 phyMiuAddr = phyAddr1 >> MIU_BUS; in HAL_TSP_Tee_Set_PvrBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c114 #define MIU_BUS 4UL macro
1077 …_HAL_REG32_W(&_TspCtrl[0].TsRec_Head, ((MS_U32)(phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)); … in HAL_TSP_PVR_SetBuffer()
1078 …_HAL_REG32_W(&_TspCtrl[0].TsRec_Tail, ((MS_U32)(phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)); … in HAL_TSP_PVR_SetBuffer()
1088 REG16_T(ADDR_PVR_HEAD20)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1089 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFF… in HAL_TSP_PVR_SetBuffer()
1090 REG16_T(ADDR_PVR_TAIL20)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1091 … REG16_T(ADDR_PVR_TAIL21)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1247 phyvalue = (MS_PHY)(_HAL_REG32_R(&_TspCtrl[0].TsRec_WPtr)<< MIU_BUS) + _phyPVRBufMiuOffset[0]; in HAL_TSP_PVR_GetBufWrite()
1539 *((MS_U32*)pData) = (1L << (MIU_BUS+TSP_DNLD_ADDR_ALI_SHIFT)); in HAL_TSP_GetCap()
1544 *((MS_U32*)pData) = (1L << MIU_BUS); in HAL_TSP_GetCap()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c114 #define MIU_BUS 4UL macro
1081 …_HAL_REG32_W(&_TspCtrl[0].TsRec_Head, ((MS_U32)(phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)); … in HAL_TSP_PVR_SetBuffer()
1082 …_HAL_REG32_W(&_TspCtrl[0].TsRec_Tail, ((MS_U32)(phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)); … in HAL_TSP_PVR_SetBuffer()
1092 REG16_T(ADDR_PVR_HEAD20)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1093 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFF… in HAL_TSP_PVR_SetBuffer()
1094 REG16_T(ADDR_PVR_TAIL20)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1095 … REG16_T(ADDR_PVR_TAIL21)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1251 phyvalue = (MS_PHY)(_HAL_REG32_R(&_TspCtrl[0].TsRec_WPtr)<< MIU_BUS) + _phyPVRBufMiuOffset[0]; in HAL_TSP_PVR_GetBufWrite()
1532 *((MS_U32*)pData) = (1L << (MIU_BUS+TSP_DNLD_ADDR_ALI_SHIFT)); in HAL_TSP_GetCap()
1537 *((MS_U32*)pData) = (1L << MIU_BUS); in HAL_TSP_GetCap()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c114 #define MIU_BUS 4UL macro
1078 …_HAL_REG32_W(&_TspCtrl[0].TsRec_Head, ((MS_U32)(phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)); … in HAL_TSP_PVR_SetBuffer()
1079 …_HAL_REG32_W(&_TspCtrl[0].TsRec_Tail, ((MS_U32)(phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)); … in HAL_TSP_PVR_SetBuffer()
1089 REG16_T(ADDR_PVR_HEAD20)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1090 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFF… in HAL_TSP_PVR_SetBuffer()
1091 REG16_T(ADDR_PVR_TAIL20)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1092 … REG16_T(ADDR_PVR_TAIL21)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF; in HAL_TSP_PVR_SetBuffer()
1248 phyvalue = (MS_PHY)(_HAL_REG32_R(&_TspCtrl[0].TsRec_WPtr)<< MIU_BUS) + _phyPVRBufMiuOffset[0]; in HAL_TSP_PVR_GetBufWrite()
1540 *((MS_U32*)pData) = (1L << (MIU_BUS+TSP_DNLD_ADDR_ALI_SHIFT)); in HAL_TSP_GetCap()
1545 *((MS_U32*)pData) = (1L << MIU_BUS); in HAL_TSP_GetCap()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DhalTSP.c147 #define MIU_BUS (4) macro
312 u32WritePtr = u32WritePtr + (1 << MIU_BUS); in _Adjust_PVR_WritePtr()
321 u32WritePtr = u32WritePtr + (1 << MIU_BUS); in _Adjust_PVR_WritePtr()
766 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_LoadFW()
4391 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_SetVQ()
4419 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4423 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4427 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4431 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4912 … REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c144 #define MIU_BUS (4) macro
310 u32WritePtr = u32WritePtr + (1 << MIU_BUS); in _Adjust_PVR_WritePtr()
319 u32WritePtr = u32WritePtr + (1 << MIU_BUS); in _Adjust_PVR_WritePtr()
789 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_LoadFW()
4902 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_SetVQ()
4930 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4934 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4938 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4942 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
5422 … REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c126 #define MIU_BUS (4) macro
690 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_LoadFW()
4577 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_SetVQ()
4605 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4609 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4613 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4617 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
5085 … REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5087 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5089 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c119 #define MIU_BUS (4) macro
551 u32DnldCtrl = (u32FwPhyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_LoadFW()
3379 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_SetVQ()
3407 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
3411 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
3415 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
3770 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3772 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3774 … REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32StartAddr0>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3777 … REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c113 #define MIU_BUS 4 macro
1477 _HAL_REG32_W(&_TspCtrl[0].TsRec_Head, (u32BufStart0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1478 _HAL_REG32_W(&_TspCtrl[0].TsRec_Tail, (u32BufEnd>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1488 …REG16_T(ADDR_PVR_HEAD20)= (u32BufStart1>> MIU_BUS) & (TSP_HW_PVR_BUF_HEAD20_MASK >> TSP_HW_PVR_B… in HAL_TSP_PVR_SetBuffer()
1489 REG16_T(ADDR_PVR_HEAD21)= (u32BufStart1>> (MIU_BUS+ 16)) & TSP_HW_PVR_BUF_HEAD21_MASK; in HAL_TSP_PVR_SetBuffer()
1490 …REG16_T(ADDR_PVR_TAIL20)= (u32BufEnd>> MIU_BUS) & (TSP_HW_PVR_BUF_TAIL20_MASK >> TSP_HW_PVR_BUF_… in HAL_TSP_PVR_SetBuffer()
1491 REG16_T(ADDR_PVR_TAIL21)= (u32BufEnd>> (MIU_BUS+ 16)) & TSP_HW_PVR_BUF_TAIL21_MASK; in HAL_TSP_PVR_SetBuffer()
1503 … _HAL_REG32_W(&_TspCtrl[0].Str2mi_head1_pvr2, (u32BufStart0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1504 … _HAL_REG32_W(&_TspCtrl[0].Str2mi_tail1_pvr2, (u32BufEnd>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1505 … _HAL_REG32_W(&_TspCtrl[0].Str2mi_head2_pvr2, (u32BufStart1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c115 #define MIU_BUS 4UL macro
1506 …TspCtrl[0].TsRec_Head, ((MS_U32)((phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1507 …(&_TspCtrl[0].TsRec_Tail, ((MS_U32)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1517 …REG16_T(ADDR_PVR_HEAD20)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_P… in HAL_TSP_PVR_SetBuffer()
1518 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & T… in HAL_TSP_PVR_SetBuffer()
1519 …REG16_T(ADDR_PVR_TAIL20)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_PVR_… in HAL_TSP_PVR_SetBuffer()
1520 …REG16_T(ADDR_PVR_TAIL21)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_… in HAL_TSP_PVR_SetBuffer()
1533 …[0].Str2mi_head1_pvr2, (MS_U32)(((phyBufStart0-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1534 …trl[0].Str2mi_tail1_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1535 …[0].Str2mi_head2_pvr2, (MS_U32)(((phyBufStart1-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c115 #define MIU_BUS 4UL macro
1524 …TspCtrl[0].TsRec_Head, ((MS_U32)((phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1525 …(&_TspCtrl[0].TsRec_Tail, ((MS_U32)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1535 …REG16_T(ADDR_PVR_HEAD20)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_P… in HAL_TSP_PVR_SetBuffer()
1536 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & T… in HAL_TSP_PVR_SetBuffer()
1537 …REG16_T(ADDR_PVR_TAIL20)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_PVR_… in HAL_TSP_PVR_SetBuffer()
1538 …REG16_T(ADDR_PVR_TAIL21)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_… in HAL_TSP_PVR_SetBuffer()
1555 …[0].Str2mi_head1_pvr2, (MS_U32)(((phyBufStart0-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1556 …trl[0].Str2mi_tail1_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1557 …[0].Str2mi_head2_pvr2, (MS_U32)(((phyBufStart1-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c118 #define MIU_BUS 4UL macro
1473 …TspCtrl[0].TsRec_Head, ((MS_U32)((phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1474 …(&_TspCtrl[0].TsRec_Tail, ((MS_U32)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1484 …REG16_T(ADDR_PVR_HEAD20)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_P… in HAL_TSP_PVR_SetBuffer()
1485 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & T… in HAL_TSP_PVR_SetBuffer()
1486 …REG16_T(ADDR_PVR_TAIL20)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_PVR_… in HAL_TSP_PVR_SetBuffer()
1487 …REG16_T(ADDR_PVR_TAIL21)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_… in HAL_TSP_PVR_SetBuffer()
1500 …[0].Str2mi_head1_pvr2, (MS_U32)(((phyBufStart0-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1501 …trl[0].Str2mi_tail1_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1502 …[0].Str2mi_head2_pvr2, (MS_U32)(((phyBufStart1-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DhalTSP.c127 #define MIU_BUS (4) macro
670 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_LoadFW()
1428 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK); in HAL_TSP_FILEIN_Address_Protect()
1429 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK); in HAL_TSP_FILEIN_Address_Protect()
3231 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_SetVQ()
3258 REG32_W(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
3665 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_01_02, (u32StartAddr0 >> MIU_BUS)); in HAL_PVR_SetBuf()
3667 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_05_06, (u32EndAddr0 >> MIU_BUS)); in HAL_PVR_SetBuf()
3669 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_03_04, (u32StartAddr0 >> MIU_BUS)); in HAL_PVR_SetBuf()
3672 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_07_08, (u32StartAddr1 >> MIU_BUS)); in HAL_PVR_SetBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c118 #define MIU_BUS 4UL macro
1546 …TspCtrl[0].TsRec_Head, ((MS_U32)((phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1547 …(&_TspCtrl[0].TsRec_Tail, ((MS_U32)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1557 …REG16_T(ADDR_PVR_HEAD20)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_P… in HAL_TSP_PVR_SetBuffer()
1558 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & T… in HAL_TSP_PVR_SetBuffer()
1559 …REG16_T(ADDR_PVR_TAIL20)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_PVR_… in HAL_TSP_PVR_SetBuffer()
1560 …REG16_T(ADDR_PVR_TAIL21)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_… in HAL_TSP_PVR_SetBuffer()
1577 …[0].Str2mi_head1_pvr2, (MS_U32)(((phyBufStart0-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1578 …trl[0].Str2mi_tail1_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1579 …[0].Str2mi_head2_pvr2, (MS_U32)(((phyBufStart1-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c118 #define MIU_BUS 4UL macro
1546 …TspCtrl[0].TsRec_Head, ((MS_U32)((phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1547 …(&_TspCtrl[0].TsRec_Tail, ((MS_U32)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1557 …REG16_T(ADDR_PVR_HEAD20)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_P… in HAL_TSP_PVR_SetBuffer()
1558 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & T… in HAL_TSP_PVR_SetBuffer()
1559 …REG16_T(ADDR_PVR_TAIL20)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_PVR_… in HAL_TSP_PVR_SetBuffer()
1560 …REG16_T(ADDR_PVR_TAIL21)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_… in HAL_TSP_PVR_SetBuffer()
1577 …[0].Str2mi_head1_pvr2, (MS_U32)(((phyBufStart0-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1578 …trl[0].Str2mi_tail1_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1579 …[0].Str2mi_head2_pvr2, (MS_U32)(((phyBufStart1-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c118 #define MIU_BUS 4UL macro
1603 …TspCtrl[0].TsRec_Head, ((MS_U32)((phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1604 …(&_TspCtrl[0].TsRec_Tail, ((MS_U32)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1614 …REG16_T(ADDR_PVR_HEAD20)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_P… in HAL_TSP_PVR_SetBuffer()
1615 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & T… in HAL_TSP_PVR_SetBuffer()
1616 …REG16_T(ADDR_PVR_TAIL20)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_PVR_… in HAL_TSP_PVR_SetBuffer()
1617 …REG16_T(ADDR_PVR_TAIL21)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_… in HAL_TSP_PVR_SetBuffer()
1634 …[0].Str2mi_head1_pvr2, (MS_U32)(((phyBufStart0-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1635 …trl[0].Str2mi_tail1_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1636 …[0].Str2mi_head2_pvr2, (MS_U32)(((phyBufStart1-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c118 #define MIU_BUS 4UL macro
1564 …TspCtrl[0].TsRec_Head, ((MS_U32)((phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1565 …(&_TspCtrl[0].TsRec_Tail, ((MS_U32)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A… in HAL_TSP_PVR_SetBuffer()
1575 …REG16_T(ADDR_PVR_HEAD20)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_P… in HAL_TSP_PVR_SetBuffer()
1576 …REG16_T(ADDR_PVR_HEAD21)= (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & T… in HAL_TSP_PVR_SetBuffer()
1577 …REG16_T(ADDR_PVR_TAIL20)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_PVR_… in HAL_TSP_PVR_SetBuffer()
1578 …REG16_T(ADDR_PVR_TAIL21)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_… in HAL_TSP_PVR_SetBuffer()
1595 …[0].Str2mi_head1_pvr2, (MS_U32)(((phyBufStart0-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1596 …trl[0].Str2mi_tail1_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
1597 …[0].Str2mi_head2_pvr2, (MS_U32)(((phyBufStart1-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD… in HAL_TSP_PVR_SetBuffer()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/fq/
H A DhalFQ.c129 #define MIU_BUS 4 macro
238 return _HAL_REG32_R(&(_REGFIQ[u32FQEng].Fiq2mi2_radr_r)) << MIU_BUS; in HAL_FQ_GetRead()
245 return _HAL_REG32_R(&(_REGFIQ[u32FQEng].str2mi2_wadr_r)) << MIU_BUS; in HAL_FQ_GetWrite()

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